PIC18F2455/2550/4455/4550                                         Data Sheet                            28/40/44-Pin, High...
Note the following details of the code protection feature on Microchip devices:•    Microchip products meet the specificat...
PIC18F2455/2550/4455/4550               28/40/44-Pin, High-Performance, Enhanced Flash,               USB Microcontrollers...
PIC18F2455/2550/4455/4550Pin Diagrams       28-Pin PDIP, SOIC                              MCLR/VPP/RE3                1  ...
PIC18F2455/2550/4455/4550Pin Diagrams (Continued)                                               RC1/T1OSI/CCP2(1)/UOE     ...
PIC18F2455/2550/4455/4550Table of Contents1.0 Device Overview ...............................................................
PIC18F2455/2550/4455/4550                                         TO OUR VALUED CUSTOMERS It is our intention to provide o...
PIC18F2455/2550/4455/4550NOTES:DS39632E-page 6             © 2009 Microchip Technology Inc.
PIC18F2455/2550/4455/45501.0      DEVICE OVERVIEW                                   1.1.3        MULTIPLE OSCILLATOR OPTIO...
PIC18F2455/2550/4455/45501.2      Other Special Features                           1.3       Details on Individual Family•...
PIC18F2455/2550/4455/4550TABLE 1-1:          DEVICE FEATURES             Features                PIC18F2455           PIC1...
PIC18F2455/2550/4455/4550FIGURE 1-1:                      PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM                          ...
PIC18F2455/2550/4455/4550FIGURE 1-2:                        PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM                     ...
PIC18F2455/2550/4455/4550TABLE 1-2:         PIC18F2455/2550 PINOUT I/O DESCRIPTIONS                           Pin         ...
PIC18F2455/2550/4455/4550TABLE 1-2:        PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)                            ...
PIC18F2455/2550/4455/4550TABLE 1-2:         PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)                           ...
PIC18F2455/2550/4455/4550TABLE 1-2:        PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)                            ...
PIC18F2455/2550/4455/4550TABLE 1-3:         PIC18F4455/4550 PINOUT I/O DESCRIPTIONS                              Pin Numbe...
PIC18F2455/2550/4455/4550TABLE 1-3:        PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)                            ...
PIC18F2455/2550/4455/4550TABLE 1-3:         PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)                           ...
PIC18F2455/2550/4455/4550TABLE 1-3:        PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)                            ...
PIC18F2455/2550/4455/4550TABLE 1-3:         PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)                           ...
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Pic 18 f4550 Datasheet

  1. 1. PIC18F2455/2550/4455/4550 Data Sheet 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology© 2009 Microchip Technology Inc. DS39632E
  2. 2. Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Information contained in this publication regarding device Trademarksapplications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of MicrochipMICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries.WARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded ControlINCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of MicrochipQUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serialthe buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certifiedhold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Codesuits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Totalintellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.DS39632E-page ii © 2009 Microchip Technology Inc.
  3. 3. PIC18F2455/2550/4455/4550 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt TechnologyUniversal Serial Bus Features: Peripheral Highlights:• USB V2.0 Compliant • High-Current Sink/Source: 25 mA/25 mA• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) • Three External Interrupts• Supports Control, Interrupt, Isochronous and Bulk • Four Timer modules (Timer0 to Timer3) Transfers • Up to 2 Capture/Compare/PWM (CCP) modules:• Supports up to 32 Endpoints (16 bidirectional) - Capture is 16-bit, max. resolution 5.2 ns (TCY/16)• 1 Kbyte Dual Access RAM for USB - Compare is 16-bit, max. resolution 83.3 ns (TCY)• On-Chip USB Transceiver with On-Chip Voltage - PWM output: PWM resolution is 1 to 10-bit Regulator • Enhanced Capture/Compare/PWM (ECCP) module:• Interface for Off-Chip USB Transceiver - Multiple output modes• Streaming Parallel Port (SPP) for USB streaming - Selectable polarity transfers (40/44-pin devices only) - Programmable dead time - Auto-shutdown and auto-restartPower-Managed Modes: • Enhanced USART module:• Run: CPU on, Peripherals on - LIN bus support• Idle: CPU off, Peripherals on • Master Synchronous Serial Port (MSSP) module• Sleep: CPU off, Peripherals off Supporting 3-Wire SPI (all 4 modes) and I2C™• Idle mode Currents Down to 5.8 μA Typical Master and Slave modes• Sleep mode Currents Down to 0.1 μA Typical • 10-Bit, Up to 13-Channel Analog-to-Digital Converter• Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V (A/D) module with Programmable Acquisition Time• Watchdog Timer: 2.1 μA Typical • Dual Analog Comparators with Input Multiplexing• Two-Speed Oscillator Start-up Special Microcontroller Features:Flexible Oscillator Structure: • C Compiler Optimized Architecture with Optional• Four Crystal modes, including High-Precision PLL Extended Instruction Set for USB • 100,000 Erase/Write Cycle Enhanced Flash• Two External Clock modes, Up to 48 MHz Program Memory Typical• Internal Oscillator Block: • 1,000,000 Erase/Write Cycle Data EEPROM - 8 user-selectable frequencies, from 31 kHz Memory Typical to 8 MHz • Flash/Data EEPROM Retention: > 40 Years - User-tunable to compensate for frequency drift • Self-Programmable under Software Control• Secondary Oscillator using Timer1 @ 32 kHz • Priority Levels for Interrupts• Dual Oscillator Options allow Microcontroller and • 8 x 8 Single-Cycle Hardware Multiplier USB module to Run at Different Clock Speeds • Extended Watchdog Timer (WDT):• Fail-Safe Clock Monitor: - Programmable period from 41 ms to 131s - Allows for safe shutdown if any clock stops • Programmable Code Protection • Single-Supply 5V In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins • Optional Dedicated ICD/ICSP Port (44-pin, TQFP package only) • Wide Operating Voltage Range (2.0V to 5.5V) Comparators Program Memory Data Memory MSSP EUSART 10-Bit CCP/ECCP Timers Device Flash # Single-Word SRAM EEPROM I/O SPP Master A/D (ch) (PWM) SPI 8/16-Bit (bytes) Instructions (bytes) (bytes) I2C™ PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3 PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3 PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3 PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3© 2009 Microchip Technology Inc. DS39632E-page 1
  4. 4. PIC18F2455/2550/4455/4550Pin Diagrams 28-Pin PDIP, SOIC MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 25 RB4/AN11/KBI0 RA3/AN3/VREF+ 5 24 RB3/AN9/CCP2(1)/VPO PIC18F2455 PIC18F2550 RA4/T0CKI/C1OUT/RCV 6 23 RB2/AN8/INT2/VMO RA5/AN4/SS/HLVDIN/C2OUT 7 22 RB1/AN10/INT1/SCK/SCL VSS 8 21 RB0/AN12/INT0/FLT0/SDI/SDA OSC1/CLKI 9 20 VDD OSC2/CLKO/RA6 10 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT/SDO RC1/T1OSI/CCP2(1)/UOE 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/D+/VP VUSB 14 15 RC4/D-/VM 40-Pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 37 RB4/AN11/KBI0/CSSPP RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1)/VPO RA4/T0CKI/C1OUT/RCV 6 35 RB2/AN8/INT2/VMO RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/AN10/INT1/SCK/SCL RE0/AN5/CK1SPP 8 33 RB0/AN12/INT0/FLT0/SDI/SDA PIC18F4455 PIC18F4550 RE1/AN6/CK2SPP 9 32 VDD RE2/AN7/OESPP 10 31 VSS VDD 11 30 RD7/SPP7/P1D VSS 12 29 RD6/SPP6/P1C OSC1/CLKI 13 28 RD5/SPP5/P1B OSC2/CLKO/RA6 14 27 RD4/SPP4 RC0/T1OSO/T13CKI 15 26 RC7/RX/DT/SDO RC1/T1OSI/CCP2(1)/UOE 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/D+/VP VUSB 18 23 RC4/D-/VM RD0/SPP0 19 22 RD3/SPP3 RD1/SPP1 20 21 RD2/SPP2 Note 1: RB3 is the alternate pin for CCP2 multiplexing.DS39632E-page 2 © 2009 Microchip Technology Inc.
  5. 5. PIC18F2455/2550/4455/4550Pin Diagrams (Continued) RC1/T1OSI/CCP2(1)/UOE NC/ICPORTS(2) RC2/CCP1/P1A 44-Pin TQFP RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3/SPP3 RD2/SPP2 RD1/SPP1 RD0/SPP0 VUSB 44 43 42 41 40 39 37 36 35 34 38 RC7/RX/DT/SDO 1 33 NC/ICRST(2)/ICVPP(2) RD4/SPP4 2 32 RC0/T1OSO/T13CKI RD5/SPP5/P1B 3 31 OSC2/CLKO/RA6 RD6/SPP6/P1C 4 30 OSC1/CLKI RD7/SPP7/P1D 5 PIC18F4455 29 VSS VSS 6 28 VDD VDD 7 PIC18F4550 27 RE2/AN7/OESPP RB0/AN12/INT0/FLT0/SDI/SDA 8 26 RE1/AN6/CK2SPP RB1/AN10/INT1/SCK/SCL 9 25 RE0/AN5/CK1SPP RB2/AN8/INT2/VMO 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB3/AN9/CCP2(1)/VPO 11 23 RA4/T0CKI/C1OUT/RCV 12 13 14 15 16 17 18 19 20 21 22 RB4/AN11/KBI0/CSSPP RA2/AN2/VREF-/CVREF NC/ICCK(2)/ICPGC(2) NC/ICDT(2)/ICPGD(2) RB5/KBI1/PGM MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RB6/KBI2/PGC RB7/KBI3/PGD RA3/AN3/VREF+ RC1/T1OSI/CCP2(1)/UOE RC0/T1OSO/T13CKI RC2/CCP1/P1A 44-Pin QFN RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3/SPP3 RD2/SPP2 RD1/SPP1 RD0/SPP0 VUSB 44 43 42 41 40 39 37 36 35 34 38 RC7/RX/DT/SDO 1 33 OSC2/CLKO/RA6 RD4/SPP4 2 32 OSC1/CLKI RD5/SPP5/P1B 3 31 VSS RD6/SPP6/P1C 4 30 VSS RD7/SPP7/P1D 5 PIC18F4455 29 VDD VSS 28 VDD 6 PIC18F4550 27 RE2/AN7/OESPP VDD 7 VDD 8 26 RE1/AN6/CK2SPP RB0/AN12/INT0/FLT0/SDI/SDA 9 25 RE0/AN5/CK1SPP RB1/AN10/INT1/SCK/SCL 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/C1OUT/RCV 12 13 14 15 16 17 18 19 20 21 22 RB4/AN11/KBI0/CSSPP RB3/AN9/CCP2(1)/VPO RA2/AN2/VREF-/CVREF RB5/KBI1/PGM MCLR/VPP/RE3 RA0/AN0 RA1/AN1 NC RB6/KBI2/PGC RB7/KBI3/PGD RA3/AN3/VREF+ Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features available in select circumstances. See Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for more information.© 2009 Microchip Technology Inc. DS39632E-page 3
  6. 6. PIC18F2455/2550/4455/4550Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Oscillator Configurations ............................................................................................................................................................ 233.0 Power-Managed Modes ............................................................................................................................................................. 354.0 Reset .......................................................................................................................................................................................... 455.0 Memory Organization ................................................................................................................................................................. 596.0 Flash Program Memory .............................................................................................................................................................. 817.0 Data EEPROM Memory ............................................................................................................................................................. 918.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 979.0 Interrupts .................................................................................................................................................................................... 9910.0 I/O Ports ................................................................................................................................................................................... 11311.0 Timer0 Module ......................................................................................................................................................................... 12712.0 Timer1 Module ......................................................................................................................................................................... 13113.0 Timer2 Module ......................................................................................................................................................................... 13714.0 Timer3 Module ......................................................................................................................................................................... 13915.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 14316.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 15117.0 Universal Serial Bus (USB) ...................................................................................................................................................... 16518.0 Streaming Parallel Port ............................................................................................................................................................ 19119.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 19720.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 24321.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 26522.0 Comparator Module.................................................................................................................................................................. 27523.0 Comparator Voltage Reference Module ................................................................................................................................... 28124.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 28525.0 Special Features of the CPU .................................................................................................................................................... 29126.0 Instruction Set Summary .......................................................................................................................................................... 31327.0 Development Support............................................................................................................................................................... 36328.0 Electrical Characteristics .......................................................................................................................................................... 36729.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 40730.0 Packaging Information.............................................................................................................................................................. 409Appendix A: Revision History............................................................................................................................................................. 419Appendix B: Device Differences......................................................................................................................................................... 419Appendix C: Conversion Considerations ........................................................................................................................................... 420Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 420Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 421Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 421Index .................................................................................................................................................................................................. 423The Microchip Web Site ..................................................................................................................................................................... 433Customer Change Notification Service .............................................................................................................................................. 433Customer Support .............................................................................................................................................................................. 433Reader Response .............................................................................................................................................................................. 434PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 435DS39632E-page 4 © 2009 Microchip Technology Inc.
  7. 7. PIC18F2455/2550/4455/4550 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.© 2009 Microchip Technology Inc. DS39632E-page 5
  8. 8. PIC18F2455/2550/4455/4550NOTES:DS39632E-page 6 © 2009 Microchip Technology Inc.
  9. 9. PIC18F2455/2550/4455/45501.0 DEVICE OVERVIEW 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURESThis document contains device-specific information forthe following devices: All of the devices in the PIC18F2455/2550/4455/4550 family offer twelve different oscillator options, allowing• PIC18F2455 • PIC18LF2455 users a wide range of choices in developing application• PIC18F2550 • PIC18LF2550 hardware. These include:• PIC18F4455 • PIC18LF4455 • Four Crystal modes using crystals or ceramic• PIC18F4550 • PIC18LF4550 resonators. • Four External Clock modes, offering the option ofThis family of devices offers the advantages of all using two pins (oscillator input and a divide-by-4PIC18 microcontrollers – namely, high computational clock output) or one pin (oscillator input, with theperformance at an economical price – with the addition second pin reassigned as general I/O).of high-endurance, Enhanced Flash programmemory. In addition to these features, the • An internal oscillator block which provides anPIC18F2455/2550/4455/4550 family introduces design 8 MHz clock (±2% accuracy) and an INTRCenhancements that make these microcontrollers a log- source (approximately 31 kHz, stable overical choice for many high-performance, power sensitive temperature and VDD), as well as a range ofapplications. 6 user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees an oscillator pin for1.1 New Core Features use as an additional general purpose I/O.1.1.1 nanoWatt TECHNOLOGY • A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal andAll of the devices in the PIC18F2455/2550/4455/4550 External Oscillator modes, which allows a widefamily incorporate a range of features that can signifi- range of clock speeds from 4 MHz to 48 MHz.cantly reduce power consumption during operation. • Asynchronous dual clock operation, allowing theKey items include: USB module to run from a high-frequency• Alternate Run Modes: By clocking the controller oscillator while the rest of the microcontroller is from the Timer1 source or the internal oscillator clocked from an internal low-power oscillator. block, power consumption during code execution Besides its availability as a clock source, the internal can be reduced by as much as 90%. oscillator block provides a stable reference source that• Multiple Idle Modes: The controller can also run gives the family additional features for robust with its CPU core disabled but the peripherals still operation: active. In these states, power consumption can be reduced even further, to as little as 4%, of normal • Fail-Safe Clock Monitor: This option constantly operation requirements. monitors the main clock source against a reference signal provided by the internal• On-the-Fly Mode Switching: The oscillator. If a clock failure occurs, the controller is power-managed modes are invoked by user code switched to the internal oscillator block, allowing during operation, allowing the user to incorporate for continued low-speed operation or a safe power-saving ideas into their application’s application shutdown. software design. • Two-Speed Start-up: This option allows the• Low Consumption in Key Modules: The power internal oscillator to serve as the clock source requirements for both Timer1 and the Watchdog from Power-on Reset, or wake-up from Sleep Timer are minimized. See Section 28.0 mode, until the primary clock source is available. “Electrical Characteristics” for values.1.1.2 UNIVERSAL SERIAL BUS (USB)Devices in the PIC18F2455/2550/4455/4550 familyincorporate a fully featured Universal Serial Buscommunications module that is compliant with the USBSpecification Revision 2.0. The module supports bothlow-speed and full-speed communication for all sup-ported data transfer types. It also incorporates its ownon-chip transceiver and 3.3V regulator and supportsthe use of external transceivers and voltage regulators.© 2009 Microchip Technology Inc. DS39632E-page 7
  10. 10. PIC18F2455/2550/4455/45501.2 Other Special Features 1.3 Details on Individual Family• Memory Endurance: The Enhanced Flash cells Members for both program memory and data EEPROM are Devices in the PIC18F2455/2550/4455/4550 family are rated to last for many thousands of erase/write available in 28-pin and 40/44-pin packages. Block cycles – up to 100,000 for program memory and diagrams for the two groups are shown in Figure 1-1 1,000,000 for EEPROM. Data retention without and Figure 1-2. refresh is conservatively estimated to be greater The devices are differentiated from each other in six than 40 years. ways:• Self-Programmability: These devices can write to their own program memory spaces under internal 1. Flash program memory (24 Kbytes for software control. By using a bootloader routine, PIC18FX455 devices, 32 Kbytes for located in the protected Boot Block at the top of PIC18FX550 devices). program memory, it becomes possible to create an 2. A/D channels (10 for 28-pin devices, 13 for application that can update itself in the field. 40/44-pin devices).• Extended Instruction Set: The 3. I/O ports (3 bidirectional ports and 1 input only PIC18F2455/2550/4455/4550 family introduces port on 28-pin devices, 5 bidirectional ports on an optional extension to the PIC18 instruction set, 40/44-pin devices). which adds 8 new instructions and an Indexed 4. CCP and Enhanced CCP implementation Literal Offset Addressing mode. This extension, (28-pin devices have two standard CCP enabled as a device configuration option, has modules, 40/44-pin devices have one standard been specifically designed to optimize re-entrant CCP module and one ECCP module). application code originally developed in high-level 5. Streaming Parallel Port (present only on languages such as C. 40/44-pin devices).• Enhanced CCP Module: In PWM mode, this All other features for devices in this family are identical. module provides 1, 2 or 4 modulated outputs for These are summarized in Table 1-1. controlling half-bridge and full-bridge drivers. Other features include auto-shutdown for The pinouts for all devices are listed in Table 1-2 and disabling PWM outputs on interrupt or other select Table 1-3. conditions, and auto-restart to reactivate outputs Like all Microchip PIC18 devices, members of the once the condition has cleared. PIC18F2455/2550/4455/4550 family are available as• Enhanced Addressable USART: This serial both standard and low-voltage devices. Standard communication module is capable of standard devices with Enhanced Flash memory, designated with RS-232 operation and provides support for the LIN an “F” in the part number (such as PIC18F2550), bus protocol. The TX/CK and RX/DT signals can accommodate an operating VDD range of 4.2V to 5.5V. be inverted, eliminating the need for inverting Low-voltage parts, designated by “LF” (such as buffers. Other enhancements include Automatic PIC18LF2550), function over an extended VDD range Baud Rate Detection and a 16-bit Baud Rate of 2.0V to 5.5V. Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).• 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead.• Dedicated ICD/ICSP Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other micro- controller features. Offered as an option in select packages, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit.DS39632E-page 8 © 2009 Microchip Technology Inc.
  11. 11. PIC18F2455/2550/4455/4550TABLE 1-1: DEVICE FEATURES Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHzProgram Memory (Bytes) 24576 32768 24576 32768Program Memory (Instructions) 12288 16384 12288 16384Data Memory (Bytes) 2048 2048 2048 2048Data EEPROM Memory (Bytes) 256 256 256 256Interrupt Sources 19 19 20 20I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, ETimers 4 4 4 4Capture/Compare/PWM Modules 2 2 1 1Enhanced Capture/ 0 0 1 1Compare/PWM ModulesSerial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USARTUniversal Serial Bus (USB) 1 1 1 1ModuleStreaming Parallel Port (SPP) No No Yes Yes10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input ChannelsComparators 2 2 2 2Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDTProgrammable Low-Voltage Yes Yes Yes YesDetectProgrammable Brown-out Reset Yes Yes Yes YesInstruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set enabled enabled enabled enabledPackages 28-Pin PDIP 28-Pin PDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin QFN 44-Pin QFN 44-Pin TQFP 44-Pin TQFP© 2009 Microchip Technology Inc. DS39632E-page 9
  12. 12. PIC18F2455/2550/4455/4550FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch RA0/AN0 inc/dec logic 8 8 RA1/AN1 Data Memory RA2/AN2/VREF-/CVREF (2 Kbytes) RA3/AN3/VREF+ PCLATU PCLATH 21 RA4/T0CKI/C1OUT/RCV 20 Address Latch RA5/AN4/SS/HLVDIN/C2OUT PCU PCH PCL OSC2/CLKO/RA6 Program Counter 12 Data Address<12> 31 Level Stack Address Latch 4 12 4 BSR FSR0 Access Program Memory STKPTR Bank (24/32 Kbytes) FSR1 FSR2 12 Data Latch PORTB RB0/AN12/INT0/FLT0/SDI/SDA inc/dec RB1/AN10/INT1/SCK/SCL 8 logic Table Latch RB2/AN8/INT2/VMO RB3/AN9/CCP2(3)/VPO RB4/AN11/KBI0 ROM Latch Address RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode & Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(3)/UOE (2) Internal RC2/CCP1 OSC1 Power-up Oscillator BITOP W Timer 8 RC4/D-/VM Block 8 8 OSC2(2) Oscillator RC5/D+/VP INTRC Start-up Timer RC6/TX/CK Oscillator Power-on 8 8 RC7/RX/DT/SDO T1OSI Reset 8 MHz ALU<8> T1OSO Oscillator Watchdog Timer 8 Single-Supply Brown-out MCLR(1) Reset Programming In-Circuit Fail-Safe VDD, VSS Debugger Clock Monitor PORTE USB Voltage Band Gap VUSB Regulator Reference MCLR/VPP/RE3(1) BOR Data EEPROM Timer0 Timer1 Timer2 Timer3 HLVD ADC Comparator CCP1 CCP2 MSSP EUSART USB 10-Bit Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 3: RB3 is the alternate pin for CCP2 multiplexing.DS39632E-page 10 © 2009 Microchip Technology Inc.
  13. 13. PIC18F2455/2550/4455/4550FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 Data Latch RA1/AN1 inc/dec logic 8 8 RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ PCLATU PCLATH (2 Kbytes) RA4/T0CKI/C1OUT/RCV 21 Address Latch RA5/AN4/SS/HLVDIN/C2OUT 20 PCU PCH PCL OSC2/CLKO/RA6 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/AN12/INT0/FLT0/SDI/SDA Address Latch 4 12 4 RB1/AN10/INT1/SCK/SCL BSR FSR0 Access Program Memory STKPTR Bank RB2/AN8/INT2/VMO (24/32 Kbytes) FSR1 RB3/AN9/CCP2(4)/VPO FSR2 12 RB4/AN11/KBI0/CSSPP Data Latch RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(4)/UOE IR RC2/CCP1/P1A RC4/D-/VM RC5/D+/VP 8 RC6/TX/CK Instruction State Machine RC7/RX/DT/SDO Decode & Control Signals Control PRODH PRODL PORTD 8 x 8 Multiply VDD, VSS 3 8 Internal Oscillator Power-up RD0/SPP0:RD4/SPP4 OSC1(2) Timer BITOP W Block 8 8 8 RD5/SPP5/P1B OSC2(2) Oscillator RD6/SPP6/P1C INTRC RD7/SPP7/P1D Start-up Timer T1OSI Oscillator 8 8 Power-on T1OSO 8 MHz Oscillator Reset ALU<8> Watchdog 8 ICPGC(3) Single-Supply Timer Programming Brown-out ICPGD(3) Reset PORTE In-Circuit RE0/AN5/CK1SPP ICPORTS(3) Debugger Fail-Safe RE1/AN6/CK2SPP Clock Monitor Band Gap RE2/AN7/OESPP ICRST(3) Reference MCLR/VPP/RE3(1) MCLR(1) USB Voltage Regulator VUSB BOR Data EEPROM Timer0 Timer1 Timer2 Timer3 HLVD MSSP EUSART ADC Comparator ECCP1 CCP2 USB 10-Bit Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing.© 2009 Microchip Technology Inc. DS39632E-page 11
  14. 14. PIC18F2455/2550/4455/4550TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP, Type Type SOICMCLR/VPP/RE3 1 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input.OSC1/CLKI 9 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.)OSC2/CLKO/RA6 10 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set.DS39632E-page 12 © 2009 Microchip Technology Inc.
  15. 15. PIC18F2455/2550/4455/4550TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, Type Type SOIC PORTA is a bidirectional I/O port.RA0/AN0 2 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0.RA1/AN1 3 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1.RA2/AN2/VREF-/CVREF 4 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Analog comparator reference output.RA3/AN3/VREF+ 5 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input.RA4/T0CKI/C1OUT/RCV 6 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RCV I TTL External USB transceiver RCV input.RA5/AN4/SS/ 7HLVDIN/C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output.RA6 — — — See the OSC2/CLKO/RA6 pin.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set.© 2009 Microchip Technology Inc. DS39632E-page 13
  16. 16. PIC18F2455/2550/4455/4550TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, Type Type SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.RB0/AN12/INT0/FLT0/ 21SDI/SDA RB0 I/O TTL Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input (CCP1 module). SDI I ST SPI data in. SDA I/O ST I2C™ data I/O.RB1/AN10/INT1/SCK/ 22SCL RB1 I/O TTL Digital I/O. AN10 I Analog Analog input 10. INT1 I ST External interrupt 1. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode.RB2/AN8/INT2/VMO 23 RB2 I/O TTL Digital I/O. AN8 I Analog Analog input 8. INT2 I ST External interrupt 2. VMO O — External USB transceiver VMO output.RB3/AN9/CCP2/VPO 24 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. VPO O — External USB transceiver VPO output.RB4/AN11/KBI0 25 RB4 I/O TTL Digital I/O. AN11 I Analog Analog input 11. KBI0 I TTL Interrupt-on-change pin.RB5/KBI1/PGM 26 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin.RB6/KBI2/PGC 27 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin.RB7/KBI3/PGD 28 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set.DS39632E-page 14 © 2009 Microchip Technology Inc.
  17. 17. PIC18F2455/2550/4455/4550TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, Type Type SOIC PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI 11 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input.RC1/T1OSI/CCP2/UOE 12 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. UOE O — External USB transceiver OE output.RC2/CCP1 13 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.RC4/D-/VM 15 RC4 I TTL Digital input. D- I/O — USB differential minus line (input/output). VM I TTL External USB transceiver VM input.RC5/D+/VP 16 RC5 I TTL Digital input. D+ I/O — USB differential plus line (input/output). VP O TTL External USB transceiver VP input.RC6/TX/CK 17 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see RX/DT).RC7/RX/DT/SDO 18 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see TX/CK). SDO O — SPI data out.RE3 — — — See MCLR/VPP/RE3 pin.VUSB 14 P — Internal USB 3.3V voltage regulator output, positive supply for internal USB transceiver.VSS 8, 19 P — Ground reference for logic and I/O pins.VDD 20 P — Positive supply for logic and I/O pins.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set.© 2009 Microchip Technology Inc. DS39632E-page 15
  18. 18. PIC18F2455/2550/4455/4550TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type TypeMCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input.OSC1/CLKI 13 32 30 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.)OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.DS39632E-page 16 © 2009 Microchip Technology Inc.
  19. 19. PIC18F2455/2550/4455/4550TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTA is a bidirectional I/O port.RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0.RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1.RA2/AN2/VREF-/ 4 21 21CVREF RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Analog comparator reference output.RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input.RA4/T0CKI/C1OUT/ 6 23 23RCV RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RCV I TTL External USB transceiver RCV input.RA5/AN4/SS/ 7 24 24HLVDIN/C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output.RA6 — — — — — See the OSC2/CLKO/RA6 pin.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.© 2009 Microchip Technology Inc. DS39632E-page 17
  20. 20. PIC18F2455/2550/4455/4550TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.RB0/AN12/INT0/ 33 9 8FLT0/SDI/SDA RB0 I/O TTL Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. FLT0 I ST Enhanced PWM Fault input (ECCP1 module). SDI I ST SPI data in. SDA I/O ST I2C™ data I/O.RB1/AN10/INT1/SCK/ 34 10 9SCL RB1 I/O TTL Digital I/O. AN10 I Analog Analog input 10. INT1 I ST External interrupt 1. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode.RB2/AN8/INT2/VMO 35 11 10 RB2 I/O TTL Digital I/O. AN8 I Analog Analog input 8. INT2 I ST External interrupt 2. VMO O — External USB transceiver VMO output.RB3/AN9/CCP2/VPO 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. VPO O — External USB transceiver VPO output.RB4/AN11/KBI0/CSSPP 37 14 14 RB4 I/O TTL Digital I/O. AN11 I Analog Analog input 11. KBI0 I TTL Interrupt-on-change pin. CSSPP O — SPP chip select control output.RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin.RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin.RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.DS39632E-page 18 © 2009 Microchip Technology Inc.
  21. 21. PIC18F2455/2550/4455/4550TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input.RC1/T1OSI/CCP2/ 16 35 35UOE RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. UOE O — External USB transceiver OE output.RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O TTL Enhanced CCP1 PWM output, channel A.RC4/D-/VM 23 42 42 RC4 I TTL Digital input. D- I/O — USB differential minus line (input/output). VM I TTL External USB transceiver VM input.RC5/D+/VP 24 43 43 RC5 I TTL Digital input. D+ I/O — USB differential plus line (input/output). VP I TTL External USB transceiver VP input.RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see RX/DT).RC7/RX/DT/SDO 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see TX/CK). SDO O — SPI data out.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.© 2009 Microchip Technology Inc. DS39632E-page 19
  22. 22. PIC18F2455/2550/4455/4550TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). These pins have TTL input buffers when the SPP module is enabled.RD0/SPP0 19 38 38 RD0 I/O ST Digital I/O. SPP0 I/O TTL Streaming Parallel Port data.RD1/SPP1 20 39 39 RD1 I/O ST Digital I/O. SPP1 I/O TTL Streaming Parallel Port data.RD2/SPP2 21 40 40 RD2 I/O ST Digital I/O. SPP2 I/O TTL Streaming Parallel Port data.RD3/SPP3 22 41 41 RD3 I/O ST Digital I/O. SPP3 I/O TTL Streaming Parallel Port data.RD4/SPP4 27 2 2 RD4 I/O ST Digital I/O. SPP4 I/O TTL Streaming Parallel Port data.RD5/SPP5/P1B 28 3 3 RD5 I/O ST Digital I/O. SPP5 I/O TTL Streaming Parallel Port data. P1B O — Enhanced CCP1 PWM output, channel B.RD6/SPP6/P1C 29 4 4 RD6 I/O ST Digital I/O. SPP6 I/O TTL Streaming Parallel Port data. P1C O — Enhanced CCP1 PWM output, channel C.RD7/SPP7/P1D 30 5 5 RD7 I/O ST Digital I/O. SPP7 I/O TTL Streaming Parallel Port data. P1D O — Enhanced CCP1 PWM output, channel D.Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.DS39632E-page 20 © 2009 Microchip Technology Inc.

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