MICROPROCESSORS AND MICROCONTROLLERS ASSIGNMENT PRESENTATION – II GROUP 8 ARM INSTRUCTIONS SUBMITTED BY, L.ANITHA (1OL104) C.SANDHYA SREE (1OL141) G.SRIRANJANI (1OL144) S.SAVITHA (1OL151) N.D.VARTHANA (1OL155) S.DURGA DEVI (11L405)
INTRODUCTION: Advanced RISC Machine First RISC microprocessor for commercial purpose Used for low-power and cost-sensitive embedded applicationsFEATURES: All instructions are 32 bits long. Most instructions execute in a single cycle. Architectural simplicitywhich allows Very small implementations which result in Very low power consumptionARM Instruction types: Data Processing Instructions Data Transfer Instructions Control Flow InstructionsData Processing InstructionsData processing instructions to perform arithmetic and logical operations.These instructions typically require 2 operands and produce a single result.Ex: ADD r0,r1,r2 ; simply takes the values in 2 reg’s (r1 & r2) , adds themtogether , and places the result in a third reg. (r0)Classified as, Arithmetic operations Bit-wise logical operations Register movement operations Comparison operations
Arithmetic operations ADD r0, r1, r2 ; r0 r1 + r2 ; simple addition ADC r0, r1, r2 ; r0 r1+r2 + C ; add with carry SUB r0, r1, r2 ; r0 r1-r2 ; subtract SBC r0, r1, r2 ; r0 r1 - r2 + C – 1 ; subtract with carry RSB r0, r1, r2 ; r0 r2 – r1 ; reverse subtraction RSC r0, r1, r2 ; r0 r2-r1+C-1 ; reverse subtract with carryBit-wise logical operations AND r0, r1, r2 ; r0 r1 AND r2 ; AND operation ORR r0, r1, r2 ; r0 r1 OR r2 ; OR operation EOR r0, r1, r2 ; r0 r1 XOR r2 ; EXOR operation BIS r0, r1, r2 ; r0 r1 AND NOT r2 ; ‘Bit clear’ where every ‘1’ in the second operand clears the corresponding bit in the first.Register movement operationsThese instructions ignore the first operand, which is omitted from the assemblylanguage format, and simply move the second operand to the destination. MOV r0, r2 ; r0 r2 ; move operation MVN r0, r2 ; r0 not r2 ; move negatedComparison operationsThese instructions do not produce a result but just set the condition code bits inthe CPSR (current program status reg) according to the selected operation. CMP CMN r1, r2 ; set cc on r1-r2 ; compare TST TEQ r1, r2 ; set cc on r1+r2 ; compare negated
r1, r2 ; set cc on r1 and r2 ; test(bit) r1, r2 ; set cc on r1 xor r2 ; test equalBarrel Shifter The ARM doesn’t have actual shift instructions. Instead it has a barrel shifter which provides a mechanism to carry out shifts as part of other instructions. LSL : logical shift left by 0 t0 31 places; fill the vacated bits at the least significant end of the word with zeros. LSR : logical shift right by 0 to 32 places; fill the vacated bits at the most significant end of the word with zeros. ASL : arithmetic shift left; this is a synonym for LSL ASR : arithmetic shift right by 0 to 32 places; fill the vacated bits at the most significant end of the word with zeros if the source operand was positive, or with ones if the source operand was negative.