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Final Paper
1. Effects of Annealing in Indium Arsenide grown on Silicon Semiconductor
Materials Science and Engineering
Israel Vega
2. Abstract
Name: Israel Vega
High School: Immokalee High School
ResearchAdvisor: Dr. Kevin S. Jones, University of Florida, Gainesville
ResearchSite: Department of Materials Science and Engineering, University of Florida,
Gainesville
As time progresses, transistors in integrated circuits continue to have more computing
power to perform faster computations in integrated circuits. According to Moore’s Law, the
number of transistor’s per square inch in integrated circuits doubles every year. For this trend to
continue, semiconductor materials must be improved to fabricate smaller faster transistors. This
is why there is a high interest of using novel materials, specifically N-type InAs grown on Si. N-
type InAs has a higher concentration of free electrons since dopants are introduced to modify its
electrical properties. InAs has a high electron mobility and narrow band gap that allows fast
transfer of electrons to operate signals. InAs and Si both have a diamond cubic crystalline
structure which is ideal, because similar crystal lattices between semiconductors will avoid
crystallographic defects such as vacancies and misalignments in the structure of atoms. Defects
in crystal lattice degrade the performance of the semiconductors conductivity. InAs has a larger
diamond cubic structure than Si which limits its performance to be used in transistors. N-type
MOCVD grown thin films of InAs were annealed at a higher temperature than they were grown
in to observe changes in their structure. Samples of annealed and non-annealed InAs were
analyzed for their electrical properties by using Hall Effect Measurements to determine
conductivity, carrier concentration, electron mobility, and sheet resistance. Plan view TEM
observations were conducted to analyze its microstructure for differences in defect density.
3. Introduction
All of electronic devices are made up of transistors that amplify or block electrical
signals which operate in a binary system of on and off signals (Callister, 2007).With
many networking transistors, signals can be sent, stored and translated into complex
combinations to perform operations on your electronic devices like cell phones and
computers. Transistors are made of semiconductor material which uses both its
conductive and insulating properties to amplify or block electrical signals in devices.
These transistors are fabricated on pure semiconductor wafers, which have too low of a
conductivity to be used as a circuit element in electronics. This pure semiconductor wafer
must then be doped with other elements or compound’s to enhance the wafers electrical
properties.
Figure 1: Silicon doped with Arsenic.
Consider what happens when small amounts of pentavalent elements are
introduced into a pure crystal. In figure 1, Arsenic has five valence electrons whereas Si
4. has four. Thus, it has one electron left unbounded which makes the doped semiconductor
more conductive with excess electrons (Kasap, 2006). Because doping involves different
semiconductors being introduced to each other, crystal structure defects, like vacancies
and misalignments of the atoms, are expected which can degrade the electrical properties
of the semiconductor. Semiconductors have their own arrangement of atoms when they
form into a crystal. Doping can result with the crystal arrangement stressing and straining
to accommodate for the differences in crystal lattices if the selected semiconductors do
not have similar crystal structures. If there are minimal defects and variances from
doping, then the semiconductor has better electrical properties since the semiconductor
has had electron impurities introduced to have more conductivity such as the doped Si in
Figure 1. There is even better performance in devices when the size of their transistors
shrinks to allow more transistors on the device, leading to faster, more powerful circuits.
An observation known as Moore’s Law is a trend that the amount of transistors that can
fit on a circuit has doubled every year. For this trend to continue, semiconductor
materials must be improved for smaller and faster transistors, which is why there is a high
interest in using N-type InAs grown on Si. N-type InAs has high electron mobility and a
narrow band gap to allow faster transfer of electrons. InAs and Si both have a diamond
cubic crystalline structure; however InAs has a larger diamond cubic structure than Si
which limits its performance to be used as a semiconductor since it causes defects in the
crystal structure. In this project, thin films of InAs grown on Si were annealed and
analyzed using Hall Effect Measurements and TEM observation for the effects of
annealing on the InAs’s conductivity, carrier concentration, and electron mobility. The
Hall Effect applies a magnetic field across the sample that pushes carriers in the –y
5. direction, which can be used to measure electrical properties (Haller and McCluskey,
2012).
Methods
Samples of N-Type InAs grown on Si wafer were prepared in 1cm² squares for Hall
Effect Measurement and Plane View TEM observation. A non-annealed sample served as a
control that had MOCVD InAs grown on Si between 300°C and 350°C and was analyzed for its
electrical properties through a Hall Effect Measurement by setting the sample on a four probe
Hall Effect sensor as seen in Figure 1.
Figure 2: A 1cm² InAs Sample is set on a Hall Effect sensor for Hall Effect Analysis.
Each corner was coated with the soft metal Indium to connect contacts with the four
probes. The sensor applied a magnetic field across the corners of the sample that stimulates the
Hall Effect phenomena. It’s important that the contacts on each of the corners are ohmic to
receive an accurate reading from Hall Effect measurement and can be determined by using a
curve tracer. An ohmic contact means an equal amount of current between the probes. These
6. samples need to be coated with an atomic layer deposition of Aluminum Oxide to keep the
Arsenide from evaporating during the annealing process.
Figure 3: Samples are placed 2 feet deep into the furnace at 550°C and annealed under an
Argon purge.
The sample is then annealed in a furnace at 550°C for 10 minutes with Argon purging to
keep the sample from reacting with the atmosphere at this high temperature. The sample is then
left to cool at room temperature. After cooling, the annealed sample is bathed in a buffered oxide
etch with hydrofluoric acid for 10 minutes to remove the Aluminum Oxide coating. The
annealed sample is bathed in water to remove the acid and then dried.
7. Figure 4: Annealed Samples are bathed in Hydrofluoric Acid to remove Aluminum Oxide
layer.
A Hall Effect Measurement is conducted on the annealed sample to analyze conductivity,
carrier concentration, electron mobility, and sheet resistance. Both annealed and non-annealed
samples are prepared for Plane-view TEM analysis. Before using a Focused Ion Beam, the
annealed sample is polished on its ends in order to mill out an even piece of its surface. The
sample is held on a stub and polished with a 30 micron grit at 200 RPM in running water. Nine,
three, one and .25 micron grits are then used to make a smooth finish on the sample.
Figure 5: Samples are polished on micron grits to remove rough edges for Focused Ion
Beam preparation
8. Figure 6: A cross section pattern is milled near the surface of the InAs sample. The milled
surface is then removed using a micro manipulator to be placed on a TEM grid.
Using a Focused Ion Beam, a surface of the InAs layer is milled out that is about
100 Nanometers thick so electrons can pass through the sample to view internal defects
clearly under Transmission Electron Microscopy. The milled surface is pulled out using a
micro manipulator that uses microscopic glass rods to remove the milled surface. The
milled surface is placed onto a TEM grid to be able to observe defect density using TEM
analysis.
10. Image of Annealed Sample
Hall Effect Measurements show that annealed samples have higher sheet resistance and
lower mobility than non-annealed samples. In fact, the average mobility of non-annealed InAs
was -29.633 (cm2/Vs), average sheet number was -2.6E13 (cm-2) and the average sheet
resistance was 8,283.5 (Ohm/cm2). The average mobility of the annealed sample was -
27.4383(cm2/Vs), average sheet number was -3.0945E13 (cm-2) and average sheet resistance
was 13,189.5 (Ohm/cm2). This a 7% decrease of mobility in the annealed sample, 19% increase
in sheet number, and a 59% increase in sheet resistance. The Hall Effect Analysis also shows
miniscule change in the amount of carriers, which suggests annealing at 550°C does not
dramatically deactivate or activate dopants. The decrease in mobility of the annealed sample can
be seen in the TEM images. Strains and defects are still distributed across the annealed sample.
11. Because the annealed sample has a lower mobility than the non-annealed, there must be a higher
defect concentration in the annealed sample than the non-annealed.
Discussion
Annealing is a type of heating treatment that can relieve the stresses and strains in the
crystal lattice of semiconductors. The intense heat diffuses the arrangement of atoms and
rearranges the crystal lattice. This heat treatment alters the electrical properties and can reduce
crystallographic defects in semiconductors. InAs grown on Si has a high interest to be used in
semiconductor material since it has a narrow band gap and high electron mobility. InAs and Si
both have a diamond cubic crystal structure; however InAs has a larger diamond cubic structure
than Si. The difference in size lattices between the InAs and Si limits its electrical properties
because it will cause variances in its structure. The heat treatment given to InAs grown Si did
not improve its electrical properties. There was lower mobility due to more defects in the crystal
lattice and higher sheet resistance. Since InAs has a larger diamond cubic structure than Si, InAs
has to stress and strain to grow onto the small Si crystal lattice. TEM images of the annealing
treatment suggest that the stresses in the InAs were relieved, which caused defects to form as the
crystal lattice diffused and rearranged. Any heat treatment in the fabrication of growing InAs on
Si should be avoided. Heat treatment has a negative effect on the mobility and resistance in thin
20 nanometer InAs grown on Si.
12.
13. References
Callister, W. D. (2007). Materials science and engineering : An introduction (7th ed. ed.). New York:
John Wiley & Sons. Retrieved from
http://www.loc.gov/catdir/enhancements/fy0814/2005054228-b.html;
http://www.loc.gov/catdir/enhancements/fy0625/2005054228-d.html;
http://www.loc.gov/catdir/enhancements/fy0625/2005054228-t.html
Coblenz, A., & Owens, H. L. j. a. (1955). Transistors: Theory and applications (1st ed. ed.). New York:
McGraw-Hill. Retrieved from University of Florida Library Catalog; Mango Discovery;
http://uf.catalog.fcla.edu/permalink.jsp?20UF000046482
Crystal lattice defects.(1969). Retrieved from University of Florida Library Catalog; Mango Discovery;
http://uf.catalog.fcla.edu/permalink.jsp?20UF024267439 database.
Dienes, G. J. Defects in crystals. Upton, N.Y: Brookhaven National Laboratory. Retrieved from
http://hdl.handle.net/2027/mdp.39015086582627
Hummel, R. E., & SpringerLink (Online service). (2011). Electronic properties of materials (4th ed.
ed.). New York: Springer. Retrieved from http://dx.doi.org/10.1007/978-1-4419-8164-6
International Conference on Defect Recognition and Image Processing,in Semiconductors, Donecker,
J., & Rechenberg, I. (1998). Defect recognition and image processing in semiconductors 1997 :
Proceedings of the 7th international conference on defect recognition and image porcessing in
semiconductors (DRIP VII) held in templin, germany, 7-10 september 1997. Bristol ;
Philadelphia: Institute of Physics Pub. Retrieved from University of Florida Library Catalog; Mango
Discovery; http://uf.catalog.fcla.edu/permalink.jsp?20UF025392669
Kasap, S. O. (. (2006). Principles of electronic materials and devices (3rd ed. ed.). Boston: McGraw-
Hill. Retrieved from http://catdir.loc.gov/catdir/toc/ecip056/2005000842.html;
http://catdir.loc.gov/catdir/toc/ecip056/2005000842.html
14. Krimmel, E. F., Siffert, P., & Siffert, P. (. (2004). Silicon : Evolution and future of a technology. Berlin:
New York : Springer. Retrieved from University of Florida Library Catalog; Mango Discovery;
http://uf.catalog.fcla.edu/permalink.jsp?20UF022154445
McCluskey, M. D., & Haller, E. E. (2012). Dopants and defects in semiconductors. Boca Raton, FL: CRC
Press. Retrieved from University of Florida Library Catalog; Mango Discovery;
http://uf.catalog.fcla.edu/permalink.jsp?20UF030369308
Ravi, K. V. (1981). Imperfections and impurities in semiconductor silicon. New York: Wiley. Retrieved
from University of Florida Library Catalog; Mango Discovery;
http://uf.catalog.fcla.edu/permalink.jsp?20UF026089152
Smith, R. A. (. (1978). Semiconductors (2d ed. ed.). Cambridge ; New York: Cambridge University
Press. Retrieved from University of Florida Library Catalog; Mango Discovery;
http://uf.catalog.fcla.edu/permalink.jsp?20UF024414455
