1. GOVERNMENT OF KARNATAKA
DEPARTMENT OF TECHNICAL EDUCATION
GOVERNMENT ENGINEERING COLLEGE
Affiliated to Visvesvaraya Technological University, Belagavi ,
Approved by AICTE and Accredited by NAAC, New Delhi
Talakal,Koppal-583238.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
MINI PROJECT ON
TRAFFIC LIGHT CONTROLLER USING VERILOG
Presented By:
SAVITA HIREMATH 2LG20EC012
GOURAVVA G 2LG21EC402
NAGARATNA K 2LG21EC408
SAVITA DATTAWADE 2LG21EC417
Under The Guidance OF:
VIJAY M PEERAPUR (M.Tech)
Assistant Professor
3. 1.0 PROBLEM STATEMENT
Design a Traffic Light Controller using Verilog that controls the traffic flow at an intersection with two roads.
The traffic light controller should support two roads, denoted as North-South (NS) and East-West (EW).
Each road will have two lanes: one for traffic flow in each direction.
The traffic light system should cycle through the following states: NS Green, NS Yellow, EW Green, EW
Yellow, and repeat. The initial state of the system should be NS Green and EW Red.
The duration of each state is as follows:
NS Green: 5 seconds.
NS Yellow: 1 seconds.
EW Green: 5seconds.
EW Yellow: 1 seconds.
Transitions between states should occur smoothly, with a 1-second delay between each state change.
When NS Green is active, EW should be Red, and vice versa.
4. 2.0 INTRODUCTION
Traffic Lights are used to control the vehicular traffic. In the modern area, everyone has
different types of vehicles resulting in rise to the numbers of vehicles.
There are three lights in the traffic signal, having different message for the drivers.
Red light asks the driver to yield at the intersection.
green light gives the driver free license to drive through the intersection.
yellow light alerts the driver to wait if the next light is red one or get ready to go or
turn the engine ON if the green light is next.
Population can be predicted using GPS tracking and thus we can easily estimate the
amount of time to be taken for delay.
A perfect aligning of cars, bikes, cycles, trucking with orderly flow by giving right of
way, this makes the process very systematic and even in the presence of heavy traffic
accident rate goes down which is one of the biggest advantage.
5. 3.0 LITERATURE SURVEY
“Design and Implementation of a Traffic Light Controller using Verilog HDL" by N. P. Sudha
and M. Senthil Kumar (2018): This paper presents the design and implementation of a traffic
light controller using Verilog HDL. The authors discuss the state diagram and the Verilog code
for the controller. They also provide simulation results and a hardware implementation on an
verilog platform.
1. "Traffic Light Controller Design and Implementation Using verilog" by P. Shinde and R.
Gade (2016): The paper presents the design and implementation of a traffic light controller
on an Verilog using Verilog. It discusses the state machine design, the Verilog code, and the
simulation results. The authors also describe the hardware Implementation and provide
performance analysis.
2. "Design and Implementation of Verilog Based Traffic Light Controller Using Verilog" by
G. Ananth, A. Deepthi, and B. Sravani (2017): This paper presents the design and
implementation of a traffic light controller on an verilog using Verilog. The authors discuss
the design process, including the state machine design, the Verilog code, and the simulation
results. They also provide a hardware implementation on a verilog board.
6. 4.0 OBJECTIVES
The objectives of designing a traffic light controller using Verilog can vary depending
on the specific requirements and constraints of the project. However, here are some
common objectives that you may consider when designing a traffic light controller:
State Transitions: Implement the logic to control the state transitions of the traffic light
controller based on the predefined timing requirements. The traffic light typically
transitions between states such as Red, Red-Yellow, Green, and Yellow.
Timing Control: Ensure that the traffic lights stay in each state for the required duration.
The timing can be controlled using counters or timers based on the specific timing
specifications for each state.
Output Control: Control the outputs of the traffic light controller based on the current
state. Typically, the outputs include signals to control the Red, Yellow, and Green lights
of the traffic light system.
Synchronization: Ensure synchronization with the system clock to maintain proper
timing and reliable operation. Use clock signals to drive the state machine and
synchronize the state transitions and output control.
7. 5.0 ICARUS VERILOG
Icarus Verilog is an open-source hardware description language (HDL) compiler and
simulator used for designing and testing digital circuits. It supports the Verilog
hardware description language and provides a range of features to facilitate the
development of digital designs. Here are some notable features of Icarus Verilog
Icarus Verilog is an implementation of the Verilog hardware description language
compiler that generates netlists in the desired format (EDIF).
8. 5.1 FEATURES OF ICARUS VERILOG
Verilog Support: Icarus Verilog fully supports the IEEE 1364-2005 Verilog standard and
offers compatibility with later versions, including SystemVerilog constructs.
Compiler: It includes a Verilog compiler that translates the hardware description into an
intermediate form, which is then used for simulation and synthesis.
Simulator: Icarus Verilog provides an event-driven simulator, which allows you to simulate
the behavior of digital circuits. It supports both interactive and batch simulation
modes.Testbench
Support: The tool enables the creation of testbenches, which are modules used to verify the
functionality of the design under test (DUT). Testbenches can be written in Verilog or other
supported languages.
Code Coverage: Icarus Verilog supports code coverage analysis, which helps you determine
the extent to which your design has been exercised by the testbench. It can generate reports
on statement, branch, condition, and toggle coverage.
9. 5.2 USE OF ICARUS
Design Entry: Write or import your digital circuit design using the Verilog HDL. This involves
describing the behavior and structure of the circuit using modules, signals, and assignments.
Compilation: Use the Icarus Verilog compiler (command: iverilog) to compile your Verilog source
code. The compiler analyzes the design, checks for syntax errors, and generates an intermediate
form known as a VVP file.
Testbench Creation: Create a testbench, which is a Verilog module that provides stimuli to the
design under test (DUT) and verifies its behavior. The testbench contains input stimulus
generation, signal monitoring, and assertions to check the correctness of the DUT.
Simulation: Run the compiled VVP file (command: vvp) using the Icarus Verilog simulator. The
simulator executes the design and the testbench together, simulating the behavior of the digital
circuit. It evaluates the design based on the input stimuli and generates output signals.
Waveform Visualization: Icarus Verilog generates a Value Change Dump (VCD) file during
simulation, which captures the values of signals over time. You can use waveform viewer tools,
such as GTKWave or ModelSim, to visualize and analyze the waveforms to debug and verify the
circuit's functionality.
Debugging and Analysis: Analyze the simulation results, waveform data, and any error messages
or assertions triggered during the simulation. Debug and troubleshoot any issues or unexpected
behavior in your design.
12. 7.0 APPLICATIONS
Digital circuit design: Verilog is widely used for designing digital circuits, such as processors, memory units,
communication interfaces, and digital signal processing (DSP) systems.
FPGA and ASIC development: Verilog is extensively used for programming Field-Programmable Gate Arrays
(FPGAs) and Application-Specific Integrated Circuits (ASICs), enabling the implementation of custom digital
logic. SoCs, which integrate multiple components, such as processors, memories, peripherals, and interfaces,
into a single chip.
Verification and simulation: Verilog is utilized in simulation and verification environments, allowing engineers
to test and verify the functionality, timing, and performance of digital systems before hardware implementation.
Digital signal processing: Verilog is utilized in the design and implementation of digital signal processing
algorithms, enabling tasks like audio and video processing, image recognition, and communications.
Networking and communication systems: Verilog is used in the design of networking and communication
systems, including routers, switches, protocol stacks, and wireless communication modules.
Hardware emulation and prototyping: Verilog is employed in hardware emulation and prototyping platforms to
emulate the behavior of complex digital systems before committing to physical fabrication.
13. 8.0 CONCLUSION
In conclusion, Verilog serves as a powerful hardware description language for
designing and implementing digital systems, including traffic light controlling projects.
Its specialized nature allows for precise modeling, modular design, and efficient digital
logic implementation. Verilog offers benefits such as simulation and testing capabilities,
integration with hardware platforms, and scalability for handling various traffic
scenarios. However, it also comes with challenges like a steep learning curve, potential
for errors, and limited debugging support. As an industry-standard language, Verilog
enables efficient collaboration, compliance with standards, and access to a supportive
community. With careful consideration of its advantages and limitations, Verilog can be
a valuable tool for creating robust and reliable traffic light controllers and a wide range
of digital systems.
