74HC123.PDF

1. General description
The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output
pulse width control by three methods:
1. The basic pulse is programmed by selection of an external resistor (REXT) and
capacitor (CEXT).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
3. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in the function table.
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered
via the reset input.
2. Features
n DC triggered from active HIGH or active LOW inputs
n Retriggerable for very long pulses up to 100 % duty factor
n Direct reset terminates output pulse
n Schmitt-trigger action on all inputs except for the reset input
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Rev. 05 — 13 July 2009 Product data sheet

74HC_HCT123_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 13 July 2009 2 of 24
NXP Semiconductors 74HC123; 74HCT123
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC123N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT123N
74HC123D −40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT123D
74HC123DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT123DB
74HC123PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT123PW
74HC123BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
Fig 1. Functional diagram
1Q
Q
2RD
RD
S
13
1REXT/CEXT
15
1CEXT
14
1Q
Q
4
9
001aaa610
1RD
2A
1
1A
10
2B
2
11
3
1B
T
Q
RD
S
2REXT/CEXT
7
2CEXT
6
2Q
5
Q 2Q
12
T

Fig 2. Logic symbol Fig 3. IEC logic symbol
1Q
Q
2RD
RD
S
2REXT/CEXT
13
7
1REXT/CEXT 15
2CEXT 6
1CEXT 14
2Q 5
1Q
Q
4
2Q 12
9
mna515
1RD
2A
1 1A
10 2B
2
11
3
1B
T
mna516
CX
&
6
5
12
RCX
R
7
9
11
10
CX
&
14
13
4
RCX
R
15
1
3
2
Fig 4. Logic diagram
mna518
nREXT/CEXT
VCC
VCC
VCC
R
nRD
nA
nB
R
CL
CL CL
CL CL
nQ
nQ
R
R

5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 5. Pin configuration for DIP16, SO16, SSOP16
and TSSOP16
Fig 6. Pin configuration for DHVQFN16
74HC123
74HCT123
1A VCC
1B 1REXT/CEXT
1RD 1CEXT
1Q 1Q
2Q 2Q
2CEXT 2RD
2REXT/CEXT 2B
GND 2A
001aaa698
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aaf046
74HC123
2REXT/CEXT 2B
2CEXT 2RD
2Q 2Q
1Q 1Q
1RD 1CEXT
1B 1REXT/CEXT
GND
2A
1A
V
CC
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
VCC
(1)
Table 2. Pin description
Symbol Pin Description
1A 1 negative-edge triggered input 1
1B 2 positive-edge triggered input 1
1RD 3 direct reset LOW and positive-edge triggered input 1
1Q 4 active LOW output 1
2Q 5 active HIGH output 2
2CEXT 6 external capacitor connection 2
2REXT/CEXT 7 external resistor and capacitor connection 2
GND 8 ground (0 V)
2A 9 negative-edge triggered input 2
2B 10 positive-edge triggered input 2
2RD 11 direct reset LOW and positive-edge triggered input 2
2Q 12 active LOW output 2
1Q 13 active HIGH output 1
1CEXT 14 external capacitor connection 1
1REXT/CEXT 15 external resistor and capacitor connection 1
VCC 16 supply voltage

6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition;
= one HIGH level output pulse; = one LOW level output pulse.
[2] If the monostable was triggered before this condition was established, the pulse will continue as programmed.
7. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
Table 3. Function table[1]
Input Output
nRD nA nB nQ nQ
L X X L H
X H X L[2] H[2]
X X L L[2] H[2]
H L ↑
H ↓ H
↑ L H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA
IO output current except for pins nREXT/CEXT;
VO = −0.5 V to (VCC + 0.5 V)
- ±25 mA
ICC supply current - 50 mA
IGND ground current - −50 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation
DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
SSOP16 package [3] - 500 mW
TSSOP16 package [3] - 500 mW
DHVQFN16 package [4] - 500 mW

8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions 74HC123 74HCT123 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
∆t/∆V input transition rise and
fall rate
nRD input
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC123
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = −4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage
current
VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 8.0 - 80 - 160 µA

CI input
capacitance
- 3.5 - - - - - pF
74HCT123
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V
IO = −4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
II input leakage
current
VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 8.0 - 80 - 160 µA
∆ICC additional
supply current
per input pin; IO = 0 A;
VI = VCC − 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins nA, nB - 35 125 - 160 - 170 µA
pin nRD - 50 180 - 225 - 245 µA
CI input
capacitance
- 3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
74HC123
tpd propagation
delay
nRD, nA, nB to nQ or nQ;
CEXT = 0 pF;
REXT = 5 kΩ;
see Figure 9
[1]
VCC = 2.0 V - 83 255 - 320 - 385 ns
VCC = 4.5 V - 30 51 - 64 - 77 ns
VCC = 5 V; CL = 15 pF - 26 - - - - - ns
VCC = 6.0 V - 24 43 - 54 - 65 ns
nRD (reset) to nQ or nQ;
CEXT = 0 pF;
REXT = 5 kΩ;
see Figure 9
VCC = 2.0 V - 66 215 - 270 - 325 ns
VCC = 4.5 V - 24 43 - 54 - 65 ns
VCC = 5 V; CL = 15 pF - 20 - - - - - ns
VCC = 6.0 V - 19 37 - 46 - 55 ns
tt output
transition time
see Figure 9 [1]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tW pulse width nA LOW; see Figure 10
VCC = 2.0 V 100 8 - 125 - 150 - ns
VCC = 4.5 V 20 3 - 25 - 30 - ns
VCC = 6.0 V 17 2 - 21 - 26 - ns
nB HIGH; see Figure 10
VCC = 2.0 V 100 17 - 125 - 150 - ns
VCC = 4.5 V 20 6 - 25 - 30 - ns
VCC = 6.0 V 17 5 - 21 - 26 - ns
nRD LOW; see Figure 11
VCC = 2.0 V 100 14 - 125 - 150 - ns
VCC = 4.5 V 20 5 - 25 - 30 - ns
VCC = 6.0 V 17 4 - 21 - 26 - ns
nQ HIGH and nQ LOW;
VCC = 5.0 V;
see Figure 10 and 11
[2]
CEXT = 100 nF;
REXT = 10 kΩ
- 450 - - - - - µs
CEXT = 0 pF;
REXT = 5 kΩ
- 75 - - - - - ns

trtrig retrigger time nA, nB; CEXT = 0 pF;
REXT = 5 kΩ; VCC = 5.0 V;
see Figure 10
[3][4] - 110 - - - - - ns
REXT external timing
resistor
see Figure 7
VCC = 2.0 V 10 - 1000 - - - - kΩ
VCC = 5.0 V 2 - 1000 - - - - kΩ
CEXT external timing
capacitor
VCC = 5.0 V; see Figure 7 [4] - - - - - - - pF
CPD power
dissipation
capacitance
per monostable;
VI = GND to VCC
[5] - 54 - - - - - pF
74HCT123
tPHL HIGH to LOW
propagation
delay
CEXT = 0 pF; REXT =
5 kΩ; see Figure 9
VCC = 4.5 V - 30 51 - 64 - 77 ns
VCC = 5 V; CL = 15 pF - 26 - - - - - ns
CEXT = 0 pF;
REXT = 5 kΩ;
see Figure 9
VCC = 4.5 V - 27 46 - 58 - 69 ns
VCC = 5 V; CL = 15 pF - 23 - - - - - ns
tPLH LOW to HIGH
propagation
delay
CEXT = 0 pF;
REXT = 5 kΩ;
see Figure 9
VCC = 4.5 V - 28 51 - 64 - 77 ns
VCC = 5 V; CL = 15 pF - 26 - - - - - ns
CEXT = 0 pF; REXT =
5 kΩ; see Figure 9
VCC = 4.5 V - 23 46 - 58 - 69 ns
VCC = 5 V; CL = 15 pF - 23 - - - - - ns
tt output
transition time
VCC = 4.5 V; see Figure 9 [1] - 7 15 - 19 - 22 ns
Table 7. Dynamic characteristics …continued

[1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH
[2] For other REXT and CEXT combinations see Figure 7. If CEXT > 10 nF, the next formula is valid.
tW = K × REXT × CEXT, where:
tW = typical output pulse width in ns;
REXT = external resistor in kΩ;
CEXT = external capacitor in pF;
K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
[3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be
extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF,
the next formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid:
trtrig = 30 + 0.19 × REXT × CEXT
0.9 + 13 × REXT
1.05, where:
trtrig = retrigger time in ns;
CEXT = external capacitor in pF; REXT = external resistor in kΩ.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF.
[4] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC
2 × fi + ∑(CL × VCC
2 × fo) + 0.75 × CEXT × VCC
2 × fo + D × 16 × VCC where:
fi = input frequency in MHz;
fo = output frequency in MHz;
D = duty factor in %;
CL = output load capacitance in pF;
VCC = supply voltage in V;
CEXT = timing capacitance in pF;
∑(CL × VCC
2 × fo) sum of outputs.
tW pulse width VCC = 4.5 V
nA LOW; see Figure 10 20 3 - 25 - 30 - ns
nB HIGH; see Figure 10 20 5 - 25 - 30 - ns
nRD LOW; see Figure 11 20 7 - 25 - 30 - ns
nQ HIGH and nQ LOW;
VCC = 5.0 V;
see Figure 10 and 11
[2]
CEXT = 100 nF;
REXT = 10 kΩ
- 450 - - - - - µs
CEXT = 0 pF;
REXT = 5 kΩ
- 75 - - - - - ns
trtrig retrigger time nA, nB; CEXT = 0 pF;
REXT = 5 kΩ; VCC = 5.0 V;
see Figure 10
[3][4] - 110 - - - - - ns
REXT external timing
resistor
VCC = 5.0 V; see Figure 7 2 - 1000 - - - - kΩ
CEXT external timing
capacitor
VCC = 5.0 V; see Figure 7 [4] - - - - - - - pF
CPD power
dissipation
capacitance
per monostable;
VI = GND to VCC
[5] - 56 - - - - - pF
Table 7. Dynamic characteristics …continued

VCC = 5.0 V; Tamb = 25 °C.
(1) REXT = 100 kΩ
(2) REXT = 50 kΩ
(3) REXT = 10 kΩ
(4) REXT = 2 kΩ
CEXT = 10 nF; REXT = 10 kΩ to 100 kΩ.
Tamb = 25 °C.
Fig 7. Typical output pulse width as a function of the
external capacitor value
Fig 8. 74HC123 typical ‘K’ factor as function of VCC
001aaa611
103
102
105
104
106
tW
(ns)
10
CEXT (pF)
1 104
103
10 102
(2)
(3)
(4)
(1)
VCC (V)
0 8
6
2 4
001aaa612
0.4
0.2
0.6
0.8
'K' factor
0

11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times
001aaa771
nB input
tW
tW
tPLH
VM
VOH
VM
VM
tW
tPLH
tTHL
tW
tPHL
tPHL
VM
tW
tPLH
nA input
nRD input
nQ output
nQ output
VM
tTLH
VY
VX
VY
VX
tPHL
tPHL tPLH
(reset)
(reset)
VOL
VOH
VOL
VI
VI
VI
GND
GND
GND

nRD = HIGH
Fig 10. Output pulse control using retrigger pulse
mna521
tW tW
tW
tW
tW
nB input
nA input
nQ output
trtrig
nA = LOW
Fig 11. Output pulse control using reset input nRD
mna522
tW tW
tW
nB input
nRD input
nQ output

Test data is given in Table 8.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 12. Test circuit for measuring switching times
VM VM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VM VM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VI VO
RT
RL S1
CL
open
G
Table 8. Test data
Type Input Load S1 position
VI tr, tf CL RL tPHL, tPLH
74HC123 VCC 6 ns 15 pF, 50 pF 1 kΩ open
74HCT123 3 V 6 ns 15 pF, 50 pF 1 kΩ open

12. Application information
12.1 Timing component connections
The basic output pulse width is essentially determined by the values of the external timing
components REXT and CEXT.
12.2 Power-up considerations
When the monostable is powered-up it may produce an output pulse, with a pulse width
defined by the values of REXT and CEXT. This output pulse can be eliminated using the
circuit shown in Figure 14.
(1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT)
externally to pin 8 (GND).
Fig 13. Timing component connections
001aaa854
CEXT REXT
nA
nB
VCC
nCEXT
nRD
nREXT/CEXT
nQ
nQ
GND
123 13 (5)
4 (12)
15 (7)
14 (6)
3 (11)
8
1 (9)
2 (10)
(1)
Fig 14. Power-up output pulse elimination circuit
001aaa613
VCC
RESET
nRD
CEXT REXT
nA
nB
VCC
nCEXT
GND nREXT/CEXT
nQ
nQ
123 13 (5)
4 (12)
15 (7)
14 (6)
8
1 (9)
2 (10)
3 (11)

12.3 Power-down considerations
A large capacitor CEXT may cause problems when powering-down the monostable due to
the energy stored in this capacitor. When a system containing this device is
powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain
damage, due to the capacitor discharging through the input protection diodes. To avoid
this possibility, use a damping diode (DEXT) preferably a germanium or Schottky type
diode able to withstand large current surges and connect as shown in Figure 15.
Fig 15. Power-down protection circuit
001aaa614
DEXT
nRD
CEXT REXT
nA
nB
VCC
nCEXT nREXT/CEXT
nQ
nQ
123 13 (5)
4 (12)
15 (7)
1 (9)
2 (10)
3 (11)
GND
14 (6)
8

13. Package outline
Fig 16. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT38-4
95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating
plane
A1
w M
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT
A
max.
1 2 b1
(1) (1) (1)
b2 c D E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max. b
max.
w
ME
e1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.254
2.54 7.62
8.25
7.80
10.0
8.3
0.76
4.2 0.51 3.2
inches 0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12
0.01
0.1 0.3
0.32
0.31
0.39
0.33
0.03
0.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Fig 17. Package outline SOT109-1 (SO16)
X
w M
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A1 A2 A3 bp c D(1) E(1) (1)
e HE L Lp Q Z
y
w
v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1
99-12-27
03-02-19
076E07 MS-012
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Fig 18. Package outline SOT338-1 (SSOP16)
UNIT A1 A2 A3 bp c D(1) E (1) e HE L Lp Q Z
y
w
v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.13
0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1
99-12-27
03-02-19
(1)
w M
bp
D
HE
E
Z
e
c
v M A
X
A
y
1 8
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2

Fig 19. Package outline SOT403-1 (TSSOP16)
UNIT A1 A2 A3 bp c D (1) E (2) (1)
e HE L Lp Q Z
y
w
v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.1
0.2
1
Notes
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153
99-12-27
03-02-18
w M
bp
D
Z
e
0.25
1 8
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index

Fig 20. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.5
1
A1 Eh
b
UNIT y
e
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4
1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00
0.05 0.1
SOT763-1 MO-241 - - -
- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
A
A1
c
detail X
y
y1 C
e
L
Eh
Dh
e
e1
b
2 7
15 10
9
8
1
16
X
D
E
C
B A
terminal 1
index area
A
C
C
B
v M
w M
E(1)
Note
D(1)
02-10-17
03-01-27

14. Abbreviations
15. Revision history
Table 9. Abbreviations
Acronym Abbreviation
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT123_5 20090713 Product data sheet - 74HC_HCT123_4
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3 “Ordering information” and Section 13 “Package outline”, package version
SOT38-1 changed to SOT38-4
74HC_HCT123_4 20060616 Product data sheet - 74HC_HCT123_3
74HC_HCT123_3 20040511 Product specification - 74HC_HCT123_CNV_2
74HC_HCT123_CNV_2 19980708 Product specification - -

16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 July 2009
Document identifier: 74HC_HCT123_5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Application information. . . . . . . . . . . . . . . . . . 15
12.1 Timing component connections . . . . . . . . . . . 15
12.2 Power-up considerations . . . . . . . . . . . . . . . . 15
12.3 Power-down considerations . . . . . . . . . . . . . . 16
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
17 Contact information. . . . . . . . . . . . . . . . . . . . . 23
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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