1. 1
1
Today: Integer Arithmetic
(H&H 5.1-5.2)
Next: continued
Lecture Topics
2
Self-study module #3
Project #2 scores sent via email
Project #3 (due no later than 9/19)
Project #4 (due no later than 9/26)
Announcements
2. 2
3
We need to distinguish between three things
when talking about a data item:
Value
External representation
Internal representation
Data Representation
4
External representations:
12 base 10
C base 16
1100 base 2
(many others)
Internal representation (in 8 bits):
00001100
Example: the value twelve
3. 3
5
Computing systems can directly process:
Boolean data
Character data
Unsigned integer data
Signed integer data
Floating point data
First four processed in integer circuits, last
one processed in floating point circuits
Fundamental Data Types
6
Only two values: false, true
Normally stored in 8-bit byte or 32-bit word:
false: 0
true: any other bit pattern
Processed as unsigned integers in circuits
Boolean Data
4. 4
7
Internal representation uses a fixed number
of bits to represent each character in the set
ASCII (7 bits): 128 characters and control
codes
Unicode (8, 16 or 32 bits): more than
136,00 characters as of Version 10.
Character Data
8
Expressed in base 2, with leading zeroes
Set of values starts at zero, limited by
number of bits available for storage
Example: 8-bit bytes
min: 00000000 0
max: 11111111 255 (28 – 1)
Unsigned Integers
5. 5
9
Natural mapping of binary numbers into N
bits of storage (with leading zeroes)
Examples (16 bits):
0 0000000000000000
1 0000000000000001
2 0000000000000010
3 0000000000000011
4 0000000000000100
Summary: Unsigned Integers
10
Several different systems developed:
Sign and magnitude (signed magnitude)
One’s complement
Two’s complement
Half of the bit patterns are used to represent
negative numbers
Signed Integers
6. 6
11
Most significant (leftmost) bit used to
indicate sign (0 for positive, 1 for negative)
Example (assume 8 bits):
+25 00011001
-25 10011001
Sign and Magnitude
12
Range (assume 8 bits):
max 01111111 +(27 – 1)
min 11111111 -(27 – 1)
Two representations of zero (assume 8 bits):
+0 00000000
-0 10000000
Sign and Magnitude
7. 7
13
Negative representation formed by applying
one’s complement operation to all bits in
positive representation (flip all bits)
Example (assume 8 bits):
+25 00011001
-25 11100110
One’s Complement
14
Range (assume 8 bits):
max 01111111 +(27 – 1)
min 10000000 -(27 – 1)
Two representations of zero (assume 8 bits):
+0 00000000
-0 11111111
One’s Complement
8. 8
15
Negative representation formed by applying
two’s complement operation to all bits in
positive representation (flip all bits, add 1)
Example (assume 8 bits):
+25 00011001
-25 11100111
Two’s Complement
16
Range (assume 8 bits):
max 01111111 +(27 – 1)
min 10000000 -(27)
One representation of zero (assume 8 bits):
+0 00000000
-0 00000000
Two’s Complement
10. 10
19
Internal representation (8 bits):
+0: 00000000
flip bits: 11111111
add 1: 1
--------
-0: 00000000
Example: -0 base 10
20
Assume 4 bits. Start with representation for +0
(0000), flip all bits, add 1 (assume 4 bits)
1111
+ 0001
----
0000
Example: negating zero
11. 11
21
Add least significant bits, generate sum bit and
carry bit (carry into next position)
1
1111
+ 0001
----
0
Example: negating zero
22
Add carry and next pair of bits, generate sum bit
and carry bit (carry into next position)
11
1111
+ 0001
----
00
Example: negating zero
12. 12
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Add carry and next pair of bits, generate sum bit
and carry bit (carry into next position)
111
1111
+ 0001
----
000
Example: negating zero
24
Add carry and next pair of bits, generate sum bit
and carry bit (carry into next position)
1111
1111
+ 0001
----
0000
Example: negating zero
13. 13
25
Summary: start with least significant bits, move
towards most significant bits (ripple carry addition)
1111
1111
+ 0001
----
0000
Example: negating zero
26
Assume 4 bits. Start with representation for +4
(0100), flip all bits, add 1
1011
+ 0001
----
1100
Example: negating four
14. 14
27
Add least significant bits, generate sum bit and
carry bit (carry into next position)
1
1011
+ 0001
----
0
Example: negating four
28
Add carry and next pair of bits, generate sum bit
and carry bit (carry into next position)
11
1011
+ 0001
----
00
Example: negating four
15. 15
29
Add carry and next pair of bits, generate sum bit
and carry bit (carry into next position)
011
1011
+ 0001
----
100
Example: negating four
30
Add carry and next pair of bits, generate sum bit
and carry bit (carry into next position)
0011
1011
+ 0001
----
1100
Example: negating four
17. 17
33
Two's complement representation used on
most microprocessors
In C/C++, type "int" is typically 32 bits wide
Internal representation
~cse320/Examples/example04.pdf
Summary: Signed Integers
34
Arithmetic operations:
NEG (negation)
ADD (addition)
SUB (subtraction)
MUL (multiplication)
DIV (division)
Negation is a unary operation (one operand)
Operations on Integers
18. 18
35
Bitwise operations:
NOT
AND
OR
XOR
NOT is a unary operation (one operand)
Operations on Integers
36
Shift operations:
SLL (shift left logical)
SRL (shift right logical)
SRA (shift right arithmetic)
No need for “shift left arithmetic” – same as
“shift left logical”
Operations on Integers
19. 19
37
Math unit:
addition and subtraction
bitwise operations
Shift unit:
shift operations
Multiply and Divide unit:
multiplication and division
Integer Circuits
38
Assume two’s complement for signed integers
Negation: flip all bits, add 1
Addition: ripple-carry adder (or faster alternative)
Subtraction: variation on addition
Multiplication: sequential logic
Division: sequential logic
Arithmetic Operations
20. 20
39
00011100 carry bits
00011101
+ 00010110
--------
00110011
Addition of two’s complement values is the same
as addition of unsigned values
One approach: ripple carry addition:
Two’s Complement Addition
40
Full
Adder
A B
SCout
CinCin A B Cout S(um)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full Adder
21. 21
41
A B
CinCout
S
S0
A0 B0
A B
CinCout
S
S1
A1 B1
A B
CinCout
S
S2
A2 B2
FA
A B
CinCout
S
FA FA FA
S3
A3 B3
Carry
Ripple-Carry Adder (4 bits)
42
00000100
(+5) 00000101
+ (+6) + 00000110
---- --------
(+11) 00001011
Example: (+5) + (+6)
24. 24
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Result would be OK if there were more bits
available to store the sum.
10001110
11001111
+ 10000010
--------
01010001
01111110
01111111
+ 00000010
--------
10000001
Overflow occurs when the result is too large.
Overflow
48
Human: sign of result is different than sign of
operands (overflow cannot occur if signs of
operands are different)
Machine: carry into most significant bit (sign bit) is
different than carry out of MSB
Test: Cn-2 XOR Cn-1
Detecting Overflow
26. 26
51
One approach: circuit to perform ripple borrow
subtraction
Alternative: use existing ripple carry adder
A - B = A + (-B)
= A + (~B + 1)
Negate B by flipping all the bits, adding 1
Two’s Complement Subtraction
52
1 000000011
(+5) 00000101
+ (~6) + 11111001
---- --------
(-1) 11111111
Ex: (+5) - (+6) = (+5) + (~6+1)
27. 27
53
1 111110111
(-5) 11111011
+ (~6) + 11111001
---- --------
(-11) 11110101
Ex: (-5) - (+6) = (-5) + (~6) + 1
54
SUB control signal: 0 means Add, 1 means Subtract
A B
CinCout
S
S0
A0
A B
CinCout
S
S1
A1
FA
A B
CinCout
S
FA FA
S2
A2
FA
A B
CinCout
S
S3
A3
B0B1B2B3
Carry
SUB
Combined Adder/Subtractor (4 bits)
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Useful to track status with addition
NZCV bits:
N: result was negative
Z: result was zero
C: copy of carry out
V: overflow occurred
Status Bits
56
Determining NZCV bits for addition:
N: copy of Sn-1 (most significant bit of result)
Z: NOR of all bits in result
C: copy of Cn-1
V: XOR of Cn-2 and Cn-1 (last two carrys)
Status Bits
29. 1
1
Today: Integer Arithmetic
(H&H 5.1-5.2)
Next: continued
Lecture Topics
2
Self-study module #4
Project #4 (due no later than 9/26)
Project #5 (due no later than 10/3)
Announcements
30. 2
3
Computing systems can directly process:
Boolean data
Character data
Unsigned integer data
Signed integer data
Floating point data
First four processed in integer circuits, last
one processed in floating point circuits
Fundamental Data Types
4
Two's complement representation used on
most microprocessors
Negative representation formed by applying
two’s complement operation to all bits in
positive representation (flip all bits, add 1)
In C/C++, type "int" is typically 32 bits wide
Signed Integers
31. 3
5
+4 00000004 00000000000000000000000000000100
+3 00000003 00000000000000000000000000000011
+2 00000002 00000000000000000000000000000010
+1 00000001 00000000000000000000000000000001
+0 00000000 00000000000000000000000000000000
-1 ffffffff 11111111111111111111111111111111
-2 fffffffe 11111111111111111111111111111110
-3 fffffffd 11111111111111111111111111111101
-4 fffffffc 11111111111111111111111111111100
Twos Complement
6
Arithmetic operations:
NEG (negation)
ADD (addition)
SUB (subtraction)
MUL (multiplication)
DIV (division)
Negation is a unary operation (one operand)
Operations on Integers
32. 4
7
Bitwise operations:
NOT
AND
OR
XOR
NOT is a unary operation (one operand)
Operations on Integers
8
Shift operations:
SLL (shift left logical)
SRL (shift right logical)
SRA (shift right arithmetic)
No need for “shift left arithmetic” – same as
“shift left logical”
Operations on Integers
33. 5
9
Math unit:
addition and subtraction
bitwise operations
Shift unit:
shift operations
Multiply and Divide unit:
multiplication and division
Integer Circuits
10
With some additional logic, one circuit can be used
for both addition and subtraction
Note that subtraction can be expressed in terms of
addition:
A - B = A + (-B)
= A + (~B + 1)
Negate B by flipping all the bits, adding 1
Addition and Subtraction
34. 6
11
SUB control signal: 0 means Add, 1 means Subtract
A B
CinCout
S
S0
A0
A B
CinCout
S
S1
A1
FA
A B
CinCout
S
FA FA
S2
A2
FA
A B
CinCout
S
S3
A3
B0B1B2B3
Carry
SUB
Combined Adder/Subtractor (4 bits)
12
Useful to track status with Adder
NZCV bits:
N: result was negative
Z: result was zero
C: copy of carry out
V: overflow occurred
Status Bits
35. 7
13
Determining NZCV bits for addition:
N: copy of Sn-1 (most significant bit of result)
Z: NOR of all bits in result
C: copy of Cn-1
V: XOR of Cn-2 and Cn-1 (last two carrys)
Status Bits
14
Bitwise operations:
NOT
AND
OR
XOR
NOT is a unary operation (one operand)
Operations on Integers
36. 8
15
Bitwise Operations
Assume 8-bit values
NOT 01101010
--------
10010101
01101010
AND 01011110
--------
01001010
01101010
OR 01011110
--------
01111110
01101010
XOR 01011110
--------
00110100
16
ASCII uses 7 bits – when stored in a byte of
memory, room for 1 parity bit.
Even parity: total number of 1's in byte is an
even number (force with parity bit).
Examples:
'B' = 0x42 P1000010 (set P to 0)
'C' = 0x43 P1000011 (set P to 1)
Application: process ASCII chars
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17
Remove parity bit:
PXXXXXXX (generic ASCII char)
AND 01111111 (mask)
--------
0XXXXXXX (char without parity bit)
Example:
11000001 AND 01111111 = 01000001 ('A')
Application: process ASCII chars
18
Convert case (lower to upper):
011XXXXX (lower case ASCII char)
AND 01011111 (mask)
--------
010XXXXX (upper case ASCII char)
Example:
01100010 AND 01011111 = 01000010 ('B')
Application: process ASCII chars
38. 10
19
Convert case (upper to lower):
010XXXXX (upper case ASCII char)
OR 00100000 (mask)
--------
011XXXXX (lower case ASCII char)
Example:
01000011 OR 00100000 = 01100011 ('c')
Application: process ASCII chars
20
C/C++ bitwise operations:
NOT ~
AND &
OR |
XOR ^
Examples:
~cse320/Examples/example05.pdf
~cse320/Examples/example06.pdf
Bitwise Operators in C/C++
40. 12
23
Shift operations move bit patterns to the left
or the right within a register.
Example (assuming 8 bits):
00110011
SLL 2: 11001100
Shift count: 0 to N-1 (where N is number of bits)
Shift Operations
24
Move bit pattern to the left, fill with zeroes on
the right.
Examples (assuming 8 bits):
00110011 11001010
SLL 1: 01100110 SLL 5: 01000000
Shift Left Logical (SLL)
41. 13
25
Move bit pattern to the right, fill with zeroes
on the left.
Examples (assuming 8 bits):
00110011 11001010
SRL 1: 00011001 SRL 5: 00000110
Shift Right Logical (SRL)
26
Move bit pattern to the right, fill with copies of
the sign bit on the left.
Examples (assuming 8 bits):
00110011 11001010
SRA 1: 00011001 SRA 5: 11111110
SRA preserves the original sign of the value.
Shift Right Arithmetic (SRA)
42. 14
27
Use masking and shifting to count number of
bits which are 1 in an ASCII character:
total = 0
loop 7 times:
mask off least significant bit
if bit is a 1, increment total
shift char right by 1 position
Application: count bits
28
C/C++ shift operations:
SLL <<
SRL >> (when value is unsigned)
SRA >> (when value is signed)
Example:
~cse320/Examples/example07.pdf
Bitwise Operators in C/C++
43. 15
29
Logarithmic barrel shifter: for N bit register,
use log2 N levels of multiplexers
Example: 8 bit register ==> 3 levels
1st level – shift 4 bits
2nd level – shift 2 bits
3rd level – shift 1 bit
Shift Circuits
8-bit right logical shifter
44. 16
31
Control signal (2 bits):
No shift
Shift left logical
Shift right logical
Shift right arithmetic
Combined shift circuits
32
Require several steps
Simple versions use sequential logic
Multiply: N bits X N bits ==> 2N bits
Divide: 2N bits / N bits ==> N bits
Multiplication and Division
46. 18
35
Unsigned Serial Division
36
Serial multiply (and divide) require sequence
of steps
Signed multiply (and divide) must account
for sign bits
More complex circuits can reduce number of
steps
Summary
