Recommended
Recommended
More Related Content
What's hot
What's hot (20)
Similar to Automotive network and gateway simulation
Similar to Automotive network and gateway simulation (20)
More from Deepak Shankar
More from Deepak Shankar (20)
Recently uploaded
Recently uploaded (20)
Automotive network and gateway simulation
- 1. ACCURATE AND RAPID MODELING OF AUTOMOTIVE NETWORKS AND GATEWAYS Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 2. Logistics of the Webinar 2 To ask a question, click on Cloud Chat sign and type the question. Folks are standing by to answer your questions. There will also be a time at the end for Q&A
- 3. ACCURATE AND RAPID MODELING OF AUTOMOTIVE NETWORKS AND GATEWAYS Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 4. Agenda Traditional network modeling approach New Generation requirements Application Example New Generation modeling methodology Experiments and Trade-off Studies
- 5. Traditional Auto Networking Create a single protocol traffic model with single Gateway Statistics: network latency and throughput Optimize: Routing Table for signal and message transfer Bottleneck: Determine network capacity Arrangement: Assign sensors and ECU to network segments
- 6. New Generation Auto Network Multi-Protocol Model for internal and external network ◦ Wireless and Wired ◦ 4G/5G, WiFi, V2V ◦ Ethernet, CAN, FlexRay, LIN, Bluetooth, NFC Autonomous Driving ◦ Concurrently receive data from sensors, cloud and road infrastructure ◦ Distributed processing with significant data movement New exploration ◦ Cyber security, AI algorithms for optimal routing ◦ Failure detection and security ◦ Dynamic allocation of processing and storage resources Support for new network devices ◦ Security gateway Infotainment and Safety on the network ◦ Data center access, Apps support
- 7. Introduction to VisualSim Network Solution Background • Communication architectures need to reduce wiring weight and support high-speed data • Add TSN (Time Sensitive Networking) for time-critical data at Gateway Using VisualSim • Estimate time slot configuration, credit configuration, and other system definitions • Observe the deterministic and non-deterministic behavior of time-critical applications using the CAN/Ether/Gateway model.
- 8. Gateway Modeling User can access all the modules required for designing their TSN compliant network from the library folder Users can use the “find” feature to find the module directly
- 10. Automotive Network Statistics o Take a look at the Gate Control List (GCL), we can see: o Time Slot T1 has CDT frames. T1 period = 2.0e-3 o Time Slot T2 AVB and BE. T2 period = 8.0e-3 o Guradband period sent to be 5 usec o So roundtrip time = T1+T2+Guardband Period = 10.005 msec
- 11. Understanding Stats - Latency Notice spike in latency every roundtrip period (10.005 msec). This is because during T1 slot, only CDT can be sent out. So Latency for the AVB or BE frames coming in at that time will increase as it has to wait for T2 slot
- 12. What happened here? Latency for CDT spiked • CDT frame misses the time slot Evaluation on BW,MIF,TAS,CBS gives us idea on what could happen with a worst case scenario Simulation Time ( Sec ) Latency(Sec)
- 14. Auto Network of CAN, Gateway and TSN Strict adherence to time-critical control Applications such as braking and airbag control require predictable delay. CAN Bus CAN Bus CAN Bus Gateway CAN Bus Gateway ECU ECU ECU ECU ETH ETH Examination of frame specifications corresponding to time-critical control • TAS (Time Aware Shaper) Appropriate time slot design • Appropriate time slot specifications with no delay in CDT frames • Appropriate credit specifications for class A / B frames (hiCredit / loCredit / idle / Slope) • Buffer overflow • MIF (Maximum Interval Frame) optimum value
- 15. Network Requirements Purpose • Examination of TSN slot specifications in CAN-Ether network • Analyze response time of the CDT frame during network congestion • Optimal solution search is performed by changing the scheduling method (TAS slot) of the software running on the HW architecture. VisualSim models • Display CAN / Ether frame delay result when passing through Gateway Observation point (report) • Observe the CAN output port of the Gateway model and inside of Gateway • Frame Latency • Buffer Occupency • SendSlope,idleSlope Demo system CAN Bus CAN Bus Gateway Gateway ECU ECU ECU ETH ETH CAN Bus CAN Bus Frame Latency BufferOccupency, SendSlope/idleSlope Report Frame Latency Buffer Occupency Slope Power Consume
- 16. VisualSim Network Model of the Auto System CAN Bus • 11 bit and 29 bit • Power calculation • Bus off • Data Frame, Remote frame, Overload Frame , Error Frame Gateway • Ethernet as backbone • IEEE 802.1 (TSN) • TAS • Redundancy • Credit shaper • BW checks Databases • BW allocations • Time Aware Shaper specifications • Signal vs Message routing Parameters • Each Linked to a feature • Ease of evaluation Library provides various types of schedulers • IEEE 802.1Q • WFQ • WRR • DRR • Strict Priority • FCFS • RR • RR Priority
- 17. Gateway model Confidential Has 5 CAN bus interfaces and 2 Ethernet interfaces by default • Set the routing table, TAS slot, etc. with parameters easily. CAN CAN Ether Ether Gateway inputs TSN architecture TAS slot DB(GateControlList） EtherIF parameters hi/loCredit idleSlope/ SendSlope
- 18. Baseline specification scenarios and results • CAN message periodically sends MSG of each frame type, TAS slot configuration is assumed to be OK 2019-MM-DD © 2019 ESOL TRINITY CO., LTD. 18 Scenario Results Frame Delay idleSlope/SendSlope 10.0005ms Buffer Occupency • Notice spike in the buffer usage at every roundtrip time (10.005 msec). • This is because, at those times, T1 slot will be active and CDT frames will be processed. So the AVB and BE frames have to wait in buffer till their slots (Gate) become active CDT frame on schedule CDT frame on schedule CDT AVB/BE GB CDT AVB/BE GB CDT AVB A AVB B AVB B CDT BE 7 AVB B AVB A TAS 2ms 8ms 500ns 0ms CAN MSG (CDT/AVB-AB,BE） 50.0025ms 50.3ms300us ・・・ ・・・・・・・・・・ ・・・ Time • Notice spike in latency every roundtrip period (10.005 msec). • This is because during T1 slot, only CDT can be sent out. • So Latency for the AVB or BE frames coming in at that time will increase as it has to wait for T2 slot • Notice that the credit builds up to the max credit on every roundtrip time (10.005msec) • This is because during T1, only CDT frames are allowed and so the AVB frames will be waiting. So during this wait period , the credit for AVB frames will build up
- 19. Worst case scenarios and results • The CAN message scenario is the same as the baseline specification, and the CDT slot is changed to the worst specification. 2019-MM-DD © 2019 ESOL TRINITY CO., LTD. 19 Scenario Results 8.7005ms CDT frame on schedule CDT frame does not on schedule Frame Delay idleSlope/SendSlope Buffer Occupency • Delays per round trip period (10.0005ms) reduced, however, CDT frame misses the slot occurs. CDT AVB/BE GB AVB/BE GB CDT AVB A AVB B AVB B CDT BE 7 AVB B AVB A CDTTAS slot 700us 8ms 500ns 0ms CAN MSG (CDT/AVB-AB,BE） 52.203ms 50.3ms303us Time ・・・ ・・・・・・・・・・ ・・・ Exploleration result: Inappropriate CDT slot specifications Add a scenario and explorer again to find the optimal solution
- 20. Explore system using VisualSim • Determine baseline specifications and identify system specification candidates based on relative trends 2019-MM-DD © 2019 ESOL TRINITY CO., LTD. 20 Baseline(TAS slot) • CDT : 2.0ms • AVB/BE: 8.0ms • GB : 500ns Expl.1 : Worst case scenario(TAS slot) • CDT : 700us • AVB/BE : 8.0ms • GB : 500ns Expl.ｎ：Change other TSN specifications, scenarios, etc. • ．．．．． • ．．．．． Goal: • Explorer for TSN network specifications with low delay without missing time slots for CDT frames Judging from relative tendency of exploration results, final specifications are derived. • CDT : 2.0ms • AVB/BE : 8.0ms • GB : 500ns • Others : ……… 1cycle＝10.0005ms 1cycle＝8.7005ms CDT AVB/BE GBTAS slot 1cycle 2ms 8ms 500ns 10.0005ms ・・・
- 21. Application-Level Analysis- Braking System with ECU and Sensors CAN Bus CAN Bus CAN BusWheel 1 Wheel 2 Wheel 3 Wheel 4 Break Pedal Proximit y Sensor Gyro Sensor Brake ECU Road sensor Engine CAN ECU CAN ECU CAN ECU N N N N NN NN NN N N Gateway N
- 22. Power, Heat, Functional and Timing
- 23. Adding Innovation to Network Simulation
- 24. Network Systems Engineering Process Multi-domain models – common tool (Visualsim)ARXMLandOther formats ECU Software Cyber Security RoutingTables Network ADAS CPU,Sensors, Memory AIAlgorithmsTrafficTracesFailure Domain level models – native tools (no change) Map Flow-down Map Flow-down Flow-down Map Map Flow-down System model – VisualSim Test 3 Test 1 Test 1 Test cases VisualSim has capability to model the entire Network Gateways
- 25. Throughput Application Latency Power System Requirements Power Service Latency Reliability Achieving Timing Constraints is Design Goal Deadline Requirements for Software + t3 Expected t3 Actual Tracing the cause of the system bottleneck
- 27. Failure without resolution Failure with resolution Network Failure , depicts Congestion on the Network Congestion at Node2 Network Failure In VisualSim Flow 1 Flow 2 Red – Flow 1 Blue - Flow2
- 28. Cyber Security Test the AI algorithms for Cyber Security on a target network with real network traces ◦ Current tests limited to algorithm correctness using Google tools ◦ Expand testing to evaluate real-time network impact Determine response times based on software performance on Gateway ECU Impact of routine AI algorithms on network throughput Pseudo Code for testing the AI Algorithms LABEL:BEGIN if(input.TIMESTAMP < Max_time){ check =find(Protocol_list,input.Protocol) if(check.length()!=0 ){ if(input.Destination == "10.0.0.10" || input.Destination == "Broadcast"){ input.Task_Destination = "Eth0" } else if(input.Destination == "10.0.0.8"){ input.Task_Destination = "wifi" } WAIT(input.TIMESTAMP) SEND(output,port_token) } else{ Dest= getColumn("Table", "Destination") D = find(Dest,input.Destination) if(P.length!=0 && S.length!=0 && D.length!=0){ WAIT(input.TIMESTAMP) SEND(output,port_token) } } } else{ SEND(Drop, port_token) }
- 29. ADAS Hardware-Software Partitioning Engine function Brake function EPS function Body function ADAS function1 Other functions Engine ECU Brake ECU EPS ECU ADAS ECU ADAS function2 ADAS function3 ADAS functions Other ECU Gateway ECU Other ECU Logical arch Physical arch Other ECU Move to another network layer Map to physical ECU CAN BUS LIN
- 30. Hardware-Software Mapping for ADAS
- 31. Integrating AUTOSAR and other OS into VisualSim Automotive Network Model 11/5/2020 MIRABILIS DESIGN INC. CONFIDENTIAL
- 32. VisualSim Latency and Functional Exploration Reports 11/5/2020 MIRABILIS DESIGN INC. CONFIDENTIAL
- 33. Wireless and Data Center Access
- 34. Remote Processing of ADAS Requests Interface 1 Interface 2 Interface 3 Interface n . . . OS1 OS2 OS3 OSn Task lookup Hypervisor Proc Core1 Proc Core2 Proc Core3 Proc Core4 Proc Core n SSD1 SSD2 SSD n HDD 1 HDD 2 HDD nDatacenter Automotive Network
- 36. Results
- 37. About Mirabilis Design and VisualSim COMPANY OVERVIEW
- 38. Company Milestones VisualSim Aerospace Simulator of the Year Hardware Modeling 2003 Company Incorporated 2005 Modeling Services 1st Customer 2008 Stochastic Modeling Innovation Award 2010 Integration API 10th customer 2011 Network modeling University program 20132015 2018 Best ESL at DAC 2nd at Arm TechCon Functional Safety 2019 VisualSim Automotive 250 products built Started Europe operations 2020 VisualSim Virtual Proto Started Asia Operations Mirabilis Design Inc. 38
- 39. Wide Range of Customer Successes Mirabilis Design Inc. 39
- 40. VisualSim software with libraries Training: Training and modelling support- user builds the components and models Services: Develop custom library- User assembles the models Develop custom libraries and models - User conducts parameter study Model-based Systems Engineering simplified and made easy-to-adopt Mirabilis Design Software and Solutions
- 41. Introduction to VisualSim Architect ◦ Architect processors, hardware systems, software and network ◦ Map algorithms on integrated and distributed systems ◦ Compute resource requirements for application task graphs ◦ Test compliance to standards and generation of diagnostics Timing and Throughput Power measurement, management and Battery Entire EE to Semiconductor Functional and Safety Analysis Libraries Hardware, Software and Network Graphical Modeling Functional, timing and power analysis to existing Model-based System Design
- 42. Largest Systems-Level Model Library Largest library of traffic, resources, hardware, software and analysis Traffic • Distribution • Sequence • Trace file • Instruction profile Reports • Timing and Buffer • Throughput/Util • Ave/peak power • Statistics Power • State power table • Power management • Energy harvesters • Battery • RegEx operators SoC Buses • AMBA and Corelink • AHB, AB, AXI, ACE, CHI, CMN600 • Network-on-Chip • TileLink System Bus • PCI/PCI-X/PCIe • Rapid IO • AFDX • OpenVPX • VME • SPI 3.0 • 1553B Processors • GPU, DSP, mP and mC • RISC-V • Nvidia- Drive-PX • PowerPC • X86- Intel and AMD • DSP- TI and ADI • MIPS, Tensilica, SH ARM • M-, R-, 7TDMI • A8, A53, A55, A72, A76, A77 Custom Creator • Script language • 600 RegEx fn • Task graph • Tracer • C/C++/Java • Python Support • Listener and Trace • Debuggers • Assertions Stochastic • FIFO/LIFO Queue • Time Queue • Quantity Queue • System Resource • Schedulers • Cyber Security RTOS • Template • ARINC 653 • AUTOSAR Memory • Memory Controller • DDR DRAM 2,3,4, 5 • LPDDR 2, 3, 4 • HBM, HMC • SDR, QDR, RDRAM Storage • Flash & NVMe • Storage Array • Disk and SATA • Fibre Channel • FireWire Networking • Ethernet & GiE • Audio-Video Bridging • 802.11 and Bluetooth • 5G • Spacewire • CAN-FD • TTEthernet • FlexRay • TSN & IEEE802.1Q FPGA • Xilinx- Zynq, Virtex, Kintex • Intel-Stratix, Arria • Microsemi- Smartfusion • Programmable logic template • Interface traffic generator Software • GEM5 • Software code integration • Instruction trace • Statistical software model • Task graph Interfaces • Virtual Channel • DMA • Crossbar • Serial Switch • Bridge RTL-like • Clock, Wire-Delay • Registers, Latches • Flip-flop • ALU and FSM • Mux, DeMux • Lookup table
- 43. ACCURATE AND RAPID MODELING OF AUTOMOTIVE NETWORKS AND GATEWAYS Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com