Artificial Neural Network Implementation on FPGA

1. Artificial Neural Network
Implementation on FPGA
D Kim
자료출처 : http://www.aistudy.com/neural/theory_oh.htm#_bookmark_2443ce0

2. Contents
1. Background
2. Paper Review
3. Experiment
4. Future work
자료출처 : http://www.aistudy.com/neural/theory_oh.htm#_bookmark_2443ce0
x : Length
Sample

3. 1. Feed Forward

4. 1. Back Propagation
W : 연결강도
△ W : 연결강도 변화량
γ : 학습신호
α : 학습률 (Learning rate)
Hebb 학습법
W : 연결강도
△ W : 연결강도 변화량
γ : 학습신호
α : 학습률 (Learning rate)
Perceptron 학습법

5. OUT
w1x1 : pulse rising time
w2x2 : pulse amplitude
𝑂𝑈𝑇 = f(w1x1 + w2x2 + b)
1. Mechanism
“공간을 왜곡하면 오른쪽과 같이 아름답게 구
분선을 그릴 수 있습니다. 이처럼 인공신경망
은 선 긋고, 구기고, 합하는 과정을 반복하여
데이터를 처리합니다. (이미지 출처: colah’s
blog)”
- 필자: Terry 작성일: 2015-05-29
w1x1 : pulse rising time
OUT
𝑂𝑈𝑇 = f(w1x1 + b)
1
0.5
10

6. w1x1
OUT1
𝑂𝑈𝑇 = f(w1x1 + b)
OUT2
10 0
x2
x1

8. 2. Paper Review

9. 2. Paper Review

10. 2. Paper Review

11. 2. Paper Review

14. 3. Experiment

15. 3. Experiment - Result
Problems
- Monolithic scintillator
- Large number of Input feature
- xy-coordinate positioning
- Computing power

16. 4. Future Work – ANN FPGA Implementation
Neuron
Activation Function
Back Propagation
Neuron
Activation Function
Back Propagation
=

17. 4. Future Work – ANN FPGA Implementation
참조 : http://www.matlabinuse.com/10359
http://www.binaryconvert.com/result_float.html?decimal=049048

18. 4. Future Work
Multiplier Fixed Point (32 bit) Floating Point (32 bit)
Range -2,147,483,648~2,147,438,647 1.2E-38 ~ 3.4E38
Precision (dependent) 0.00000012
Slice 21 (2) 57 (9) 1 : 2.70
FFs 66 (2) 90 (5) 1 : 1.37
LUT 24 (2) 125 (31) 1 : 5.21
Requirement 10 ns (Minimum Period) , 100 MHz (Maximum Frequency)
Speed 7.562 ns , 132.240 MHz 12.019 ns , 83.202 MHz
Logic Number used Slice FFs
Adder/Sub 14 128 240
Multiplier 28 57 (190) 109 (517)
Register 36 26 32
DSP48A1s 90 (50%)

19. 4. Paper Reivew

20. 4. Paper Reivew

21. 4. Paper Reivew

22. 4. Paper Reivew

23. 4. Paper Reivew