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1
CACHE MEMORY ORGANIZATION
AND DIFFERENT CACHE
MAPPING TECHNIQUES AND
TECHNIQUES TO REDUCE
CACHE MISS
Click to edit Master title style
2
WHAT IS CACHE MEMORY ?
• Very high speed memory
• Used to reduce the average time to access data from the main memory
• Smaller and faster memory which stores copies of the data from frequently used
main memory locations
• Used to speed up and synchronizing with high speed CPU
2
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3
WHAT ARE THE LEVELS OF MEMORY ?
3
• Level 1 or Register :
I. Data is stored and accepted and accepted that are immediately stored in CPU
ii. Most commonly used register is accumulator, address register etc.
• Level 2 or Cache Memory :
i. Fastest Memory which has faster access time
ii. Data temporarily stored for faster access
• Level 3 or main Memory :
i. Here computer works properly
ii. Small in size and once power is off, data is no longer stays in the memory
• Level 4 or Secondary Memory :
i. External type memory
ii. Not fast as main memory but data stays permanently in this memory
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4
WHAT IS CACHE MAPPING ?
4
• A technique by which the contents of main memory are brought into
cache memory
WHAT ARE TH DIFFERENT TECHNIQUES OF CACHE MAPPING ?
• DIRECT MAPPING
• ASSOCIATIVE MAPPING
• SET ASSOCIATIVE MAPPING
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5
WHAT IS DIRECT MAPPING ?
5
• We assign each memory block to a specific line in the cache
• The old block is trashed, when the line is previously taken by memory block and the
new block needs to be loaded
• An address is split into two parts i.e. index field and tag field
• It is directly proportional to hit ratio
• Each main memory address can be viewed as consisting of three
fields
• The least significant w bits identify a unique word or byte within a
block of main memory
• Remaining s bits specify one of the 2^s blocks of main memory
• There is also a field of r bits and this field identifies one of the 2^r
lines of the cache
Click to edit Master title style
6
WHAT IS ASSOCIATIVE MAPPING ?
6
• The associative memory is used to sore content and addresses of the memory
word
• Any block can go into any line in the cache
• The word bits are used to identify which word in the block is needed, but the tag becomes all
of the remaining bits
• This enables the placement of any word at any place in the cache
memory
• It is considered to be the fastest and the most flexible mapping form
Click to edit Master title style
7
WHAT IS SET ASSOCIATIVE MAPPING ?
7
• This form of mapping is an enhanced form of direct mapping where the drawbacks
of direct mapping are removed
• It addresses the problem of possible thrashing in direct mapping method
• Instead of having exactly one line that a block can map to the cache, we will group a few lines
together creating a set
• It allows that each word is present in the cache can have two or more
words in main memory for same index addresses
• It combines the best of direct and associative mapping techniques
Click to edit Master title style
8
CACHE PERFORMANCE
8
• When the processor needs to read or write a location in main memory, it first
checks for a corresponding entry in the cache
• If the processor finds that the memory location is in the cache, a cache hit has
occurred and data is read from cache
• If the processor does not find the memory location in the cache, a cache miss has
occurred
• For a cache miss, the cache allocates a new entry and copies in data from main memory
• The performance of cache memory is frequently measured in terms of a quantity called Hit Ratio.
Hit ratio = hit / (hit + miss) = no. of hits/total accesses
Click to edit Master title style
9
WHAT IS CACHE MISS ?
9
• It is an event which a system makes a request to retrieve data from a cache,
but the data is not present in the cache memory
• WHAT ARE THE DIFFERENT TECHNIQUES TO REDUCE CACHE MISS ?
• FIFO ALGORITHM
• OPTIMAL PAGE REPLACEMENT ALGORITHM
• LRU ALGORITHM
Click to edit Master title style
10
FIFO ALGORITHM (FIRST IN FIRST OUT)
10
Hit Ratio=(5/20*100)%=25%
Miss Ratio=(15/20*100)%=75%
Click to edit Master title style
11
OPR ALGORIHM (OPTIMAL PAGE REPLACEMEMNT)
11
Hit Ratio=(9/18*100)%= 50%
Miss Ratio=(9/18*100)=50%
Click to edit Master title style
12
LRU ALGORITHM (LEAST RECENTLY USED)
12
Hit Ratio=(8/20*100)%=40%
Miss Ratio= (12/20*100)%=60%
Click to edit Master title style
13
THANK YOU
RITESH KUMAR SHAW-13000220104
AMBARISH ADAK-13000220105
ABHISEKH KUMAR GUPTA-13000320018

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GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptx

  • 1. Click to edit Master title style 1 CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES AND TECHNIQUES TO REDUCE CACHE MISS
  • 2. Click to edit Master title style 2 WHAT IS CACHE MEMORY ? • Very high speed memory • Used to reduce the average time to access data from the main memory • Smaller and faster memory which stores copies of the data from frequently used main memory locations • Used to speed up and synchronizing with high speed CPU 2
  • 3. Click to edit Master title style 3 WHAT ARE THE LEVELS OF MEMORY ? 3 • Level 1 or Register : I. Data is stored and accepted and accepted that are immediately stored in CPU ii. Most commonly used register is accumulator, address register etc. • Level 2 or Cache Memory : i. Fastest Memory which has faster access time ii. Data temporarily stored for faster access • Level 3 or main Memory : i. Here computer works properly ii. Small in size and once power is off, data is no longer stays in the memory • Level 4 or Secondary Memory : i. External type memory ii. Not fast as main memory but data stays permanently in this memory
  • 4. Click to edit Master title style 4 WHAT IS CACHE MAPPING ? 4 • A technique by which the contents of main memory are brought into cache memory WHAT ARE TH DIFFERENT TECHNIQUES OF CACHE MAPPING ? • DIRECT MAPPING • ASSOCIATIVE MAPPING • SET ASSOCIATIVE MAPPING
  • 5. Click to edit Master title style 5 WHAT IS DIRECT MAPPING ? 5 • We assign each memory block to a specific line in the cache • The old block is trashed, when the line is previously taken by memory block and the new block needs to be loaded • An address is split into two parts i.e. index field and tag field • It is directly proportional to hit ratio • Each main memory address can be viewed as consisting of three fields • The least significant w bits identify a unique word or byte within a block of main memory • Remaining s bits specify one of the 2^s blocks of main memory • There is also a field of r bits and this field identifies one of the 2^r lines of the cache
  • 6. Click to edit Master title style 6 WHAT IS ASSOCIATIVE MAPPING ? 6 • The associative memory is used to sore content and addresses of the memory word • Any block can go into any line in the cache • The word bits are used to identify which word in the block is needed, but the tag becomes all of the remaining bits • This enables the placement of any word at any place in the cache memory • It is considered to be the fastest and the most flexible mapping form
  • 7. Click to edit Master title style 7 WHAT IS SET ASSOCIATIVE MAPPING ? 7 • This form of mapping is an enhanced form of direct mapping where the drawbacks of direct mapping are removed • It addresses the problem of possible thrashing in direct mapping method • Instead of having exactly one line that a block can map to the cache, we will group a few lines together creating a set • It allows that each word is present in the cache can have two or more words in main memory for same index addresses • It combines the best of direct and associative mapping techniques
  • 8. Click to edit Master title style 8 CACHE PERFORMANCE 8 • When the processor needs to read or write a location in main memory, it first checks for a corresponding entry in the cache • If the processor finds that the memory location is in the cache, a cache hit has occurred and data is read from cache • If the processor does not find the memory location in the cache, a cache miss has occurred • For a cache miss, the cache allocates a new entry and copies in data from main memory • The performance of cache memory is frequently measured in terms of a quantity called Hit Ratio. Hit ratio = hit / (hit + miss) = no. of hits/total accesses
  • 9. Click to edit Master title style 9 WHAT IS CACHE MISS ? 9 • It is an event which a system makes a request to retrieve data from a cache, but the data is not present in the cache memory • WHAT ARE THE DIFFERENT TECHNIQUES TO REDUCE CACHE MISS ? • FIFO ALGORITHM • OPTIMAL PAGE REPLACEMENT ALGORITHM • LRU ALGORITHM
  • 10. Click to edit Master title style 10 FIFO ALGORITHM (FIRST IN FIRST OUT) 10 Hit Ratio=(5/20*100)%=25% Miss Ratio=(15/20*100)%=75%
  • 11. Click to edit Master title style 11 OPR ALGORIHM (OPTIMAL PAGE REPLACEMEMNT) 11 Hit Ratio=(9/18*100)%= 50% Miss Ratio=(9/18*100)=50%
  • 12. Click to edit Master title style 12 LRU ALGORITHM (LEAST RECENTLY USED) 12 Hit Ratio=(8/20*100)%=40% Miss Ratio= (12/20*100)%=60%
  • 13. Click to edit Master title style 13 THANK YOU RITESH KUMAR SHAW-13000220104 AMBARISH ADAK-13000220105 ABHISEKH KUMAR GUPTA-13000320018