CMOS fabrication video

1. 1Lecture 5: IC Fabrication
The Transistor Revolution
First transistor
Bell Labs, 1948
© Rabaey: Digital Integrated Circuits2nd

2. 2Lecture 5: IC Fabrication
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
© Rabaey: Digital Integrated Circuits2nd

3. 3Lecture 5: IC Fabrication
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
© Rabaey: Digital Integrated Circuits2nd

4. 4Lecture 5: IC Fabrication
Moore’s Law
16
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12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2OFTHENUMBEROF
COMPONENTSPERINTEGRATEDFUNCTION
Electronics, April 19, 1965.
© Rabaey: Digital Integrated Circuits2nd

5. 5Lecture 5: IC Fabrication
Silicon IC processing
Similar to photographic printing
Expose the silicon wafer through a mask
Process the silicon wafer
Repeat sequentially to pattern all the layers
Layout: A set of masks that tell a fabricator what to
pattern
For each layer in your circuit
Layers are metal, drain/source implants, gate, etc.
You draw the layers
Subject to vendor-supplied spacing rules

6. 6Lecture 5: IC Fabrication
The wafer
Czochralski process
Melt silicon at 1425 °C
Add impurities (dopants)
Spin and pull crystal
Slice into wafers
0.25mm to 1.0mm thick
Polish one side

7. 7Lecture 5: IC Fabrication

8. 8Lecture 5: IC Fabrication
Crystal and wafer
Wand
(a finished 250lb crystal)
A polished wafer

9. 9Lecture 5: IC Fabrication
4X reticle
Wafer
The mask
Illuminate reticle on wafer
Typically 4× reduction
Typical image is 25×25mm
Limited by focus
Step-and repeat across
wafer
Limited by mechanical
alignment

10. 10Lecture 5: IC Fabrication Reference: FULLMAN KINETICS
Lithography
Patterning is done by exposing photoresist with light
Requires many steps per “layer”
Example: Implant layer

11. 11Lecture 5: IC Fabrication
Grow Oxide Layer
Reference: FULLMAN KINETICS

12. 12Lecture 5: IC Fabrication Reference: FULLMAN KINETICS
Add Photoresist

13. 13Lecture 5: IC Fabrication Reference: FULLMAN KINETICS
Mask

14. 14Lecture 5: IC Fabrication Reference: FULLMAN KINETICS
Animation

15. 15Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

16. 16Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

17. 17Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

18. 18Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

19. 19Lecture 5: IC Fabrication
9/03 IEEE spectrum

20. 20Lecture 5: IC Fabrication
Patterning
How we pattern and
expose the resist
To make the patterns
we want on the silicon
IEEE Spectrum, 7/99, p. 41

21. 21Lecture 5: IC Fabrication 9/03 IEEE spectrum

22. 22Lecture 5: IC Fabrication
Detailed process sequence
1. Grow epi layer
Ultra-pure single-crystal
silicon
2. Implant n-well

23. 23Lecture 5: IC Fabrication
Detailed process sequence (con’t)
3. Define active area
4. Grow field oxide
For isolation

24. 24Lecture 5: IC Fabrication
Detailed process sequence (con’t)
5. Grow gate oxide
6. Pattern polysilicon

25. 25Lecture 5: IC Fabrication
Detailed process sequence (con’t)
7. Form pFETs
8. Form nFETs

26. 26Lecture 5: IC Fabrication
Detailed process sequence (con’t)
9. Deposit LTO by CVD
LTO is low-temperature
oxide
CVD is chemical vapor
deposition
10. Deposit Metal1
Usually aluminum

27. 27Lecture 5: IC Fabrication
Detailed process sequence (con’t)
11. Via definition
Deposit LTO
Make via cuts
12. Deposit Metal2
Usually aluminum
13. Overglass (not shown)
Coat entire chip with Si3N4
Make pad openings in Si3N4

28. 28Lecture 5: IC Fabrication
An inverter

29. 29Lecture 5: IC Fabrication
Figure courtesy
Yan Borodovsky,
Intel
A Pentium cutaway

30. 30Lecture 5: IC Fabrication
National 0.18µm process cutaway

31. 31Lecture 5: IC Fabrication
Advanced Metallization - Copper
Copper versus Aluminum
~ 40% lower resistivity
~ 10× less electromigration

32. 32Lecture 5: IC Fabrication
Interconnect Impact on Chip

33. 33Lecture 5: IC Fabrication
10 100 1,000 10,000 100,000
Length (u)
Noofnets
(LogScale)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Nature of Interconnect
Local Interconnect
Global Interconnect
SLocal = STechnology
SGlobal = SDie
Source:Intel

34. 34Lecture 5: IC Fabrication

35. 35Lecture 5: IC Fabrication
Permittivity

36. 36Lecture 5: IC Fabrication

37. 37Lecture 5: IC Fabrication

38. 38Lecture 5: IC Fabrication

39. 39Lecture 5: IC Fabrication

40. 40Lecture 5: IC Fabrication
Projections
Simulated distribution of dopant
atoms in a 0.05m nFET
red: acceptor atom
blue: donor atom
All figures from IEEE Spectrum, 7/99

41. 41Lecture 5: IC Fabrication
An AMD 50nm transistor

42. 42Lecture 5: IC Fabrication
Frequency
P6
Pentium ® proc
486
386
28680868085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Frequency(Mhz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
© Rabaey: Digital Integrated Circuits2nd

43. 43Lecture 5: IC Fabrication
Power Dissipation
P6
Pentium ® proc
486
386
2868086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
Power(Watts)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
© Rabaey: Digital Integrated Circuits2nd

44. 44Lecture 5: IC Fabrication
Power density
4004
8008
8080
8085
8086
286
386
486
Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
PowerDensity(W/cm2)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
Courtesy, Intel
© Rabaey: Digital Integrated Circuits2nd

45. 45Lecture 5: IC Fabrication
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
x
xx
x
xx
x
21%/Yr. compound
Productivity growth rate
x
58%/Yr. compounded
Complexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
LogicTransistorperChip(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Productivity
(K)Trans./Staff-Mo.
Source: Sematech
Complexity outpaces design productivity
Complexity
Courtesy, ITRS Roadmap
© Rabaey: Digital Integrated Circuits2nd

46. 46Lecture 5: IC Fabrication
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

47. 47Lecture 5: IC Fabrication
NRE Cost is Increasing
© Rabaey: Digital Integrated Circuits2nd

48. 48Lecture 5: IC Fabrication
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
© Rabaey: Digital Integrated Circuits2nd