Know the Bipolar Junction Transistor

1. UNIT III
BJT AND ITS BIASING
ANALOG ELECTRONICS

2. Classification of Transistor
 Two types of transistor as
 Unipolar junction transistor
 Current conduction due to only majority carrier. Commonly known as
FET. It is voltage operated devices
 FET can classified as
 Junction Field Effect Transistor (JFET)
 Metal Oxide Semiconductor FET (MOSFET)
 Metal semiconductor FET (MESFET)
 Biploar junction transistor
 Current conduction due to both holes and electrons. It is current
operated devices and classified as npn, pnp

3. Classification of Transistor

4. TRANSISTOR (BJT)
 Transistor construction
 Types as n-p-n and p-n-p transistor
 Three region as
 Emitter (E)
 Base (B)
 Collector (C)
 Emitter
 It placed one side, which supplies charge carrier to other
region. It is heavily doped
 Base
 It is middle in region forms two PN junction. It is lightly
doped and thinner region
 Collector
 It is opposite to the emitter and collect charge. It is larger
region compared to other two. Doping level is intermediate.

5. Standard transistor symbol
 It has two junction like two diode
 JE as emitter diode and act as F.B
 JC as collector diode and act as R.B

6. Modes of operation
 If transistor operate as an amplifier, it biased with
external voltages.
 Depends on external bias voltage polarity, transistor
works as any one of the three region

7. Transistor operation
 E-B junction as F.B and C-B junction as R.B.
 Ie flows through the collector region.
 Working as npn transistor:
 E-B junction as F.B and C-B junction as R.B
 Electrons in n-region(E) flows in to p-region(B)
 B- lightly doping so that small electrons only recombine to
holes and remaining current flows to n-region (C)
 IE=IB+IC
 IC has minority carrier and majority carrier current

8.  Working as pnp transistor:
 E-B junction as F.B and C-B junction as R.B
 Holes in p-region(E) flows in to n-region(B)
 B- lightly doping so that small holes only recombine to
electrons and remaining holes current flows to p-region
(C)
 Current conduction takes place only by holes
 But external wiring still current be electron.

9. Types of configuration
 Connection of transistor circuit as
 One terminal is i/p
 Other terminal is o/p
 Other terminal common between i/p and o/p
S.No Configuration Input Output Common
terminal
Also Called as
1 CB E C B Grounded Base
Configuration
2 CE B C E Grounded Emitter
Configuration
3 CC B E C Grounded
Collector
Configuration

10. Common Base configuration
 I/p applied as E-B
 O/p taken as C-B
 Base is common for i/p and o/p

11.  Current amplification factor (α):
 Ratio of o/p current to i/p current is nothing but α.
 α< unity. α↑ by IB↓. Α range as 0.9 to 0.99
 Expression for collector current:
 Total collector current consist of
 Part of IE reaches to C terminal (αIE)
 Ileakage due to minority carrier in B-C jn on account of R.B
 Ileakage =ICBO (C-B current with E open)

12. Common Base Characteristics
 I/p characteristics
 It relates as i/p current (IE) with i/p voltage (VBE) for varies
output voltage (VCB)

13.  Observation as
 Point 1
 IE ↑ rapidly after cut in voltage with small ↑VBE
 Indicate Rin is small.
 Dynamic i/p resistance as
 Point 2
 ↑VCB then slight ↑IE
 Reason as VCB ↑, then width of depletion region (Jc
junction) changed under R.B condition.
 Depletion width in Je junction small due to F.B

14.  O/p Characteristics
 It relates as o/p current (IC) with o/p voltage (VCB) for varies
input current (IE). In diagram Y-axis as IC (wrong)

15.  Observation as
 Active region
 IC ↑ with equal to IE. IC independent on VCB
 Relationship as
 B-E jn as F.B and C-B jn as R.B
 Cut-off region
 IE=0, IC=ICBO due to reverse saturation current.
 ICBO as on order of μA or nA. Here IC≈0
 B-E jn and C-B jn both as R.B

16.  Saturation region
 This is the region as left of VCB=0
 B-E jn and C-B jn both as F.B
 Early effect or base width modulation
 VC ↑, R.B ↑, then (depletion width between C-B)↑
 As result in base width ↓
 Causes of base width ↓ as
 Less chances of recombination in B- region, then α ↑ with VCB ↑
 Charge gradient ↑ in B-region, minority carrier I injected in E-region ↑
 Large VC, B-width ↓ effectively (may be zero), causes B.D voltage in
transistor. This phenomenon called punch through.

17.  Transistor parameters
 Slope of CB char gives different parameter. Which is
nothing but h-parameter.
 i/p impedance
 Typical value as 20Ω to 50Ω
 O/p admittance
 Typical value as 0.1μΩ to 10μΩ
 Forward current gain
 Typical value as 0.9 to 1.0
 Reverse voltage gain
 Typical value as 10^-5 to 10^-4

18. Common Emitter Configuration
 I/p applied as B-E and o/p applied as C-E
 E is common for both i/p and o/p

19.  Base current amplification factor (β):
 Ratio of change in o/p current to change in input current.
 Relationship between α and β
If α=1 then β=Ꚙ
Conclusion:
Β of CE config is high and so
95% used in this transistor
Configuration.

20.  Expression for collector current:

21. Common Emitter Characteristics
 I/p characteristics
 Relates i/p current (IB) to i/p voltage (VBE) for varies level
of o/p voltage (VCE) (here Y-axis is IB)

22.  Observation as
 Point 1
 IB ↑ rapidly after cut-in voltage of VBE.
 So Rin is small.
 Point 2
 VCE ↑, IB ↓, here VBE=const
 Reason of IB ↓ as R.B ↑ at Jc junction which means C-B
junction.
 Then depletion layer width ↑
 Width of B-region ↓ and ↓ of recombination in B-region

23.  O/p Characteristics
 It relates as o/p current (IC) with o/p voltage (VCE) for varies
input current (IB).

24.  Observation as
 Active region
 B-E as F.B and C-B as R.B
 VCE ↑, then R.B ↑. Due to Early effect width of depletion
region ↑ and base width ↓ then recombination in base↑
 Small change in α result large change in β
 Compare to CB config when CE config o/p char slope is
large
 Cut-off region
 B-E and C-B both as R.B
 IB=0, IC=ICEO (reverse leakage current) which is very small.

25.  The region below IB=0 is known as cut-off region
 Saturation region
 B-E and C-B both as F.B
 Region to left of VCE(sat) is called the saturation region.
 VCE ↓ very less, then C-B junction as become F.B
 Ranges of VCE as 0.1 to 0.3V

26.  Transistor parameters
 Slope of CB char gives different parameter. Which is
nothing but h-parameter.
 i/p impedance
 Typical value as 500Ω to 2000Ω
 O/p admittance
 Typical value as 0.1μΩ to 10μ mho
 Forward current gain
 Typical value as 20 to 200
 Reverse voltage gain
 Typical value as 10^-5 to 10^-4

27. Common collector
configuration
 I/p applied as B-C and o/p taken as E-C
 C is common for both i/p and o/p

28.  Current amplification factor (ꝩ)
 Ratio of change in IE to change in IB
 Relation among α, β and ꝩ

29.  Expression for the output current

30. Characteristics
 I/p characteristics
 Relates i/p current (IB) to i/p voltage (VBC) for varies level of
o/p voltage (VEC)

31.  I/p Char of CC config as differ from CE and CB config.
The reason as follows
 VBC ↑, with VEC=const, then VEB↓ and IB ↓
 Which explain slope of CC i/p char.

32.  O/p Characteristics
 It relates as o/p current (IE) with o/p voltage (VCE) for
varies input current (IB).
 Its char is similar to CE configuration.

33. Comparison of CE, CB and CC
configuration

34. Commonly used transistor connection
 CE config only used most 90-95%. The reason as
follows
 High current gain
 In CE config, IC (o/p)>>IB (i/p) due to large β
 So gain is high = 20 to 500
 High voltage and power gain
 Due to high current gain there will be a high voltage gain
 Moderate o/p to i/p impedance relation
 In CE config the ratio of o/p impedance to i/p impedance
small (around 50)
 This arrangement used to coupling between varies
transistor stages.

35. TWO PORT DEVICES AND HYBRID
MODEL
 Behavior of two port model is analyzed using current
and voltage parameter at i/p and o/p port.
 Which is namely as Iin, Vin, Io, Vo.
 From these
 Two parameter as independent
 Other two as dependent. Which expressed in terms of
independent parameter
 Two port network as shown

36.  Here independent variable as i/p current (i1) and o/p
voltage (V2)
 i/p voltage (V1) and o/p current i2 can be written as

37.  Dimension of h-parameter are as follows
 Hybrid parameter as
 An alternative subscript notation recommended by IEEE is
commonly used

38.  Based on definition of h-parameter the mathematical
model for two-port networks knows as h-parameter
model can be developed as shown.
 The above two equation as satisfied by taking KVL in i/p
loop and KCL in o/p loop.

39. h- parameter model of BJT for CE
configuration
 In CE configuration
 B- i/p terminal
 C- o/p terminal
 E- common for both i/p and o/p
 Dependent variable as--------VB, iC
 Independent variable as--------iB, VC
 The equation for CE configuration can be written as

40.  The h-parameter model for CE configuration is
 The subscript “e” indicates that the h-parameters are
for CE-configuration
hie= i/p impedance when C-E terminal is S.C
hre= revere voltage gain when B-E terminal is O.C
hfe= forward current gain when C-E terminal is S.C
hoe= o/p admittance when B-E terminal is O.C

41. h- parameter model of BJT for CB
configuration
 In CB configuration
 E- i/p terminal
 C- o/p terminal
 B- common for both i/p and o/p
 Dependent variable as--------VE, iC
 Independent variable as--------iE, VC
 The equation for CB configuration can be written as

42.  The h-parameter model for CB configuration is
 The subscript “b” indicates that the h-parameters are
for CB-configuration
hib= i/p impedance when C-B terminal is S.C
hrb= revere voltage gain when E- terminal is O.C
hfb= forward current gain when C-B terminal is S.C
hob= o/p admittance when E- terminal is O.C

43. h- parameter model of BJT for CC
configuration
 In CC configuration
 B- i/p terminal
 E- o/p terminal
 C- common for both i/p and o/p
 Dependent variable as--------VB, iE
 Independent variable as--------iB, VE
 The equation for CC configuration can be written as

44.  The h-parameter model for CC configuration is
 The subscript “c” indicates that the h-parameters are
for CC-configuration
hic= i/p impedance when E-C terminal is S.C
hrc= revere voltage gain when B- terminal is O.C
hfc= forward current gain when E-C terminal is S.C
hoc= o/p admittance when B- terminal is O.C

45. ANALYSIS OF A TRANSISTOR
AMPLIFIER CIRCUIT USING h-
PARAMETERS
 Basic amplifier circuit as shown fig (1).
 For form proper amplifier, then need of connect load
and source circuit with proper biasing

46.  This circuit can be replacing with its small signal hybrid
model as shown in fig (2)
 For analysis of hybrid model find current gain, i/p
resistance, voltage gain and o/p resistance

47.  Current gain (Ai)

48.  Current gain (Ais) taking into account the source
resistance Rs:
 This model is driven as current source instead of voltage
source and which is given as

49.  From this figure (b) using current divider rule get
as follows

50.  Input impedance (Zi):
 From the figure (2), look at i/p side
It is from figure (1)

51. Taken from current gain
derivation

52.  Voltage gain (AV):
 It is ratio of o/p voltage (V2) to i/p voltage (V1)
 Voltage gain (AVS) taking into account the source
resistance RS:

53.  By applying voltage division rule as

54.  Output admittance (Y0):
 It is ratio of o/p current I2 to o/p voltage V2

55.  Power gain (AP):
 It is ratio of average power deliver to load RL, to i/p power.
 o/p power is given as

56.  Conclusion of small signal analysis of a
transistor amplifier as

58. Methods of Transistor Biasing
 Following methods are used
 Fixed bias (or) Base resistor method
 Fixed bias with emitter resistor
 Collector-to-Base bias (or) Biasing with feedback
resistor
 Collector-Emitter feedback bias
 Voltage divider bias (or) Self bias

59. Fixed Bias
 Fixed bias circuit as shown
 It is also called fixed
current bias or base
resistor biasing circuit.
 VCC=VBE=RB=RC=const.
Then IB remains fixed level.
So called fixed bias. For
select proper RB value,
then got IB level.
 RB fixed as high (several
100KΩ). For selecting
proper value of RB, then
required value IB can be
made flow

60.  Circuit analysis
 B-E loop
 Write KVL as shown fig, VCC-IBRB_VBE=0, IB=VCC-
VBE/RB
 RB value is high, causes more voltage drop across it.
 So less drop across B-E jn. So RB set the level of IB.

61.  C-E loop
 Magnitude of IC=βIB
 β =const, then IC is function of IB. Here IC not change w.r.to RC
 RC use to find level of VCE.
 As per KVL in loop, VCE+ICRC-VCC=0, VCE=VCC-ICRC
 So RC set the level of VCE

62.  Stability factor (S)
 General formula for stability factor as
 In a fixed bias IB is independent of IC (i.e) IC=VCC-VBE/RB
 So =0, so S=β+1. So stability factor is β+1
times as much as any change in ICO

63.  Stability factor (S’)

64.  Stability factor (S’’)

65.  Advantages
 It is very simple biasing circuit, as only RB is needed.
 Biasing condition can be easily set and calculations are
simple.
 Disadvantages
 This methods provide poor stabilization. IC ↑, due to temp
not able to control.
 Stability factor is very high. So there is strong chances of
thermal runaway.
 Due to this demerit, this method of biasing is rarely
used.

66. Fixed bias with Emitter resistor
(Emitter stabilized bias circuit)
 Fixed bias emitter resistor
circuit as shown
 Also called emitter feedback
bias.
 RE introduced to provide better
bias stability.
 Current gain β↑ due to temp,
then IC also ↑. It provides more
V.D across RE and ↓ V.D across
RB. Causes IB ↓ and IC ↓.
 So if IC ↑ only way to ↑RE.
 But practically RE make small
to avoid transistor operate in

67.  B-E loop
 Apply KVL in loop
The only difference between the equation
Compared in fixed bias as (1+β) RE

68.  C-E loop

69.  Stability factor (S)

71. Collector to Base Bias (DC bias
with voltage feedback)
 Also called as Base bias with
collector feedback or collector
feedback bias.
 RB connect to C. But it improve
bias stability, V.D across RB
purely depends on VCE.
 If IC larger then design value
causes to ↑ V.D across RC. This
result small value of VCE, so that
IB small than design value. Then
IC also ↓.
 Although Q-point is not totally
independent of beta, the
sensitivity to changes in beta

72.  B-E loop
 If writing KVL as

73.  C-E loop
 Apply KVL in loop as

74.  Stability Factor (S)

76.  Stability Factor (S’)

77.  Stability Factor (S’’)

79.  Advantages
 It is simple method and require only RB
 This circuit provides stabilization of operating circuit
 Disadvantages
 This circuit not provide good stabilization because of
stability factor is fairly high, though it is lesser than that
fixed bias. So operating change, due to temp variations
and other effects.
 Circuit provide –ve feedback which reduce the gain of
amplifier. During +ve half cycle of signal, IC ↑. Which result
larger drop across RC. This will ↓IB & IC↓

80. Collector –Emitter Feedback Bias
 Fig shows C-E f/b circuit
apply both Collector f/b and
Emitter f/b
 RB provide Collector f/b
which connect between C &
B
 RE provide Emitter f/b which
connect between E &
ground.
 Both f/b used to control IC &
IB in opposite direction to
increase stability.

81.  Apply KVL to loop then get

82.  Base Circuit
 KVL in circuit as

83.  Collector Circuit
 Apply KVL in collector circuit as

84. Voltage Divider Bias (or) Self
Bias
 Also called as self bias (or)
potential divider bias.
 Most used method of biasing
and stabilizing the transistor
 R1 & R2 connected across Vi
to provide biasing
 RE provide stabilization
 Voltage divider forms by R1 &
R2. V.D across R2 gives F.B of
B-E junction.
 Current flows through RE
causes V.D in which R.B of E-
jn. So transistor remains in
active region
 IC↑, due to ICO↑ with temp, IE
↑. So V.D across RE ↑, and

85.  Analysis
 i/p side of n/w redrawn as shown.
 Thevinin equivalent n/w for left of B-terminal can be found
as follows
For finding RTH as shown

86.  For finding ETH as shown Thevinin Equivalent circuit as sh

87.  C-E loop
 Apply KVL in loop as

88.  Stability Factor (S)
 Apply KVL in Thevinin equivalent circuit

89. •This is smallest value of S and leads to
max thermal stability
•If RTH/RE is not neglected, then circuit
have stability factor around 10.

90.  Stability Factor (S’)

91.  Stability Factor (S’’)

94.  Advantages of voltage divider bias over other
types of biasing
 In fixed Bias
 Stability factor, S=1+β. So β is large, then circuit
provides poor stability
 In Collector to Base Bias
 RC is very small. S≈1+β. Which is equal to fixed bias.
So this method is not preferable.
 In Self Bias
 When RB/RE is very small. S≈1 which provides good
stability.
 Comparing to other method then voltage
divider method is best method.

95. BJT AS AN AMPLIFIER
 A transistor acts as an amplifier by raising the strength of
a weak signal.
 The DC bias voltage applied to the emitter base junction
makes it remain in forward biased condition.
 This forward bias is maintained regardless of the polarity
of the signal.
 The below figure shows how a transistor looks like when
connected as an amplifier. The low resistance in input
circuit lets any small change in input signal to result in an
appreciable change in the output.
 The emitter current caused by the input signal
contributes the collector current, which when flows
through the load resistor RL, results in a large voltage
drop across it.

97. SMALL SIGNAL ANALYSIS OF CE
AMPLIFIER
 Varies types as
 CE amplifier with Fixed Bias
 CE amplifier with Unbypassed Emitter Resistor
 CE amplifier with Voltage-Divider Bias
 CE amplifier with Collector to Base Bias

98. CE amplifier with Fixed Bias
 The circuit diagram as shown
 The ac equivalent circuit of the amplifier can be drawn
by the steps mentioned as follows
 Remove d.c effects of power supply (VCC) by grounding
them
 Replace the capacitor (C1 and C2) by S.C

99.  Circuit reduces the
equivalent circuit as shown
 Substituting the
approximate hybrid
model for the transistor,
the circuit reduces to as
shown

100.  Input impedance
 Output impedance
 It is the impedance
determined with Vi=0. with
Vi=0, Ib=0 and hfeIb=0
indicating an O.C of
current source in
equivalent circuit
 Current gain
 Voltage gain

101. CE amplifier with Unbypassed Emitter
Resistor
 Equivalent circuit as shown  AC equivalent amplifier
redrawn as shown

102.  By substituting hybrid model of circuit which reduces
as shown

103.  Input impedance  Output impedance

104.  Voltage gain  Current gain

105. CE amplifier with Voltage Divider Bias
 The circuit diagram as
shown
 AC equivalent circuit by
substituting hybrid
model as shown

106.  Input impedance
 Output impedance
 Voltage gain
 Current gain

107. CE amplifier with Collector to
Base Bias
 The Figure shows the common emitter amplifier with
collector to base bias.
 The resistance RF is connected between input and
output.
 For the analysis of this circuit it is necessary to split this
resistance for input and output. This can be achieved by
using Miller’s Theorem.

108. Miller’s Theorem:
 In general, Miller theorem is used for converting any
circuit having configuration of Figure (a) to another
configuration of Figure (b).
 If Z is the impedance connected between two nodes,
node 1 and node 2, it can be replaced by two separate
impedances Z1 and Z2. Where Z1 is connected between
node 1 and ground and Z2 is connected between node 2
and ground.

109.  The Vi and V0 are the voltages at the node 1 and
node 2respectively. The values of Z1 and Z2 can
be derived from the ratio of V0 and Vi(V0/Vi),
denoted as k.
 The values of impedances Z1 and Z2 are given as,