MOORE FSM SEQUENCE DETECTOR • OBJECTIVE • INTRODUCTION • FSM(FINITE STATE MACHINE) • SEQUENCE DETECTOR • MEALY MACHINE AND MOORE MACHINE • VERILOG CODE • TEST BENCH • RTL SCHEMATIC ➢This Verilog project is to present a full Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector is also provided for simulation. ➢The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes high only when a "1011" the sequence is detected. ➢ The Moore FSM output depends on only the current state of the FSM. The state diagram of the Moor FSM for the sequence detector is as follows: Next state of the Moore FSM depends on the sequence input and the current state. ➢ The output of the Moore FSM only depends on the current state. ➢ The output of the sequence detector only goes high when the "1011" sequence is detected There are basically two types of sequence detector depending on the type of sequence they identify, which are as follows: • Overlapping Sequence Detector • Non-Overlapping Sequence Detector: Mealy machine: A simple Mealy machine has one input and one output. Each transition edge is labeled with the value of the input (shown in red) and the value of the corresponding output (shown in blue). The machine starts in state Si.

1. PONDICHERRY UNIVERSITY
DEPARTMENT OF ELECTRONICS
ENGINEERING
SUBMITTED TO:
PROF. DR. K ANUSUDHA
DEPT. OF ELECTRONICS ENGINEERING
SUBMITTED BY:
AWANISH KUMAR
M.TECH(ECE)-1st Year
21304006
MOORE FSM SEQUENCE DETECTOR

2. CONTENTS
• OBJECTIVE
• INTRODUCTION
• FSM(FINITE STATE MACHINE)
• SEQUENCE DETECTOR
• MEALY MACHINEAND MOORE MACHINE
• VERILOG CODE
• TEST BENCH
• RTL SCHEMATIC
• CONCLUSION
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3. OBJECTIVE
➢This Verilog project is to present a full Verilog code for Sequence
Detector using Moore FSM. A Verilog Testbench for the Moore FSM
sequence detector is also provided for simulation.
➢The Moore FSM keeps detecting a binary sequence from a digital
input and the output of the FSM goes high only when a "1011"
sequence is detected.
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4. INTRODUCTION
➢ The Moore FSM output depends on only the current state of the
FSM. The state diagram of the Moor FSM for the sequence detector
is as follows: Next state of the Moore FSM depends on the sequence
input and the current state.
➢ The output of the Moore FSM only depends on the current state.
➢ The output of the sequence detector only goes high when the
"1011" sequence is detected
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5. SEQUENCE DETECTOR
• There are basically two types of
sequence detector depending on
the type of sequence they identify,
which are as follows:
• Overlapping Sequence
Detector
• Non-Overlapping Sequence
Detector:
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Figure : - Sequence Detector

6. MEALY MACHINE AND MOORE MACHINE
Mealy machine: A simple Mealy machine has one input and one output.
Each transition edge is labelled with the value of the input (shown in red) and the
value of the corresponding output (shown in blue).
The machine starts in state Si.
Figure : - Mealy Machine

7. MOORE MACHINE
• Simple Moore machines have one input and one output. Output
depends only upon the present state.
• Generally, it has more states than Mealy Machine. Input change can
cause change in output change as soon as logic is done.
• In Moore machines, more logic is needed to decode the outputs since
it has more circuit delays.
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8. VERILOG CODE
module
sequence_detector_moore(sequence_in,clock,reset,detector_out);
input clock;
input reset;
input sequence_in;
output reg detector_out;
parameter Zero=3'b000,
One=3'b001,
OneZero=3'b011,
OneZeroOne=3'b010,
OneZeroOneOne=3'b110;
reg [2:0] current_state, next_state;
// sequential memory of the Moore FSM
always @(posedge clock, posedge reset)
begin
if(reset==1)
current_state <= Zero;
// when reset=1, reset the state of the FSM to "Zero" State
else
current_state <= next_state; // otherwise, next state
end
always
@(current_state,sequence_in)
begin
case(current_state)
Zero:begin
if(sequence_in==1)
next_state = One;
else
next_state = Zero;
end
One:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = Zero;
end
One:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end
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9. One:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end
OneZero:begin
if(sequence_in==0)
next_state = Zero;
else
next_state = OneZeroOne;
end
OneZeroOne:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = OneZeroOneOne;
end
OneZeroOneOne:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end
default:next_state = Zero;
endcase
end
always @(current_state)
begin
case(current_state)
Zero: detector_out = 0;
One: detector_out = 0;
OneZero: detector_out = 0;
OneZeroOne: detector_out = 0;
OneZeroOneOne: detector_out = 1;
default: detector_out = 0;
endcase
end
endmodule
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10. TEST BENCH
module tb_Sequence_Detector_Moore;
// Inputs
reg sequence_in;
reg clock;
reg reset;
// Outputs
wire detector_out;
// Instantiate the Unit Under Test
sequence_detector_moore uut (
.sequence_in(sequence_in),
.clock(clock),
.reset(reset),
.detector_out(detector_out));
clock = 0;
forever #5 clock = ~clock;
end
initial begin
// Initialize Inputs
sequence_in = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#30;
reset = 0;
#40;
sequence_in = 1;
#10;
sequence_in = 0;
#10;
sequence_in = 1;
#20;
sequence_in = 0;
#20;
sequence_in = 1;
#20;
sequence_in = 0;
end
endmodule
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11. RTL SCHEMATIC
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12. RTL SCHEMATIC
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15. CONCLUSION
➢ The simulation waveform of the sequence detector shows exactly
how a Moore FSM works.
➢ Next state of the Moore FSM depends on the sequence input and the
current state.
➢ The output of the Moore FSM only depends on the current state.
➢ The output of the sequence detector only goes high when the "1011"
sequence is detected.

16. THANK YOU
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