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© Barry Wilkinson 2009. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed. slides4-1.fm-1
Instructions
In the following, we will use a simple instruction formats quite similar
to the G4/G5 PowerPC and SUN Sparc processors (so-called
reduced instruction set computer, RISC) and also similar but not
identical to that used in the course textbook.

Some Key Processor Features
1. Thirty-two 32-bit integer registers called R0 to R31
2. One register, R0, holds zero permanently
3 All arithmetic done only between registers
- Three-register format
(op-code destination register, source 1 register, source 2 register)
or
- Immediate addressing
(op-code destination, source 1 register, constant)
4. Memory operations limited to load register and store register
using register indirect addressing plus offset only.

Data Transfer
Instructions that copy the contents of one location to another
location.
Examples
MOV R1,R2 ;R1 = R2
LD R3,100[R2] ;Contents of memory whose address is
;given by 100 + R2 copied to R3.
ST [R5],R4 ;Contents of R4 copied to memory location
;whose address is held in R5. (Offset = 0)
Note LD and ST cause 32-bit transfers. Use LB and SB to cause 8-
bit transfers.
Instruction Comments

Arithmetic Instructions
Performs an arithmetic operation such as addition, subtraction,
multiplication or division.
Examples
ADD R1,R2,R3 ;R1 = R2 + R3
SUB R5,R4,3 ;R5 = R4 - 3

Assembly Language Notation
Differences in assembly language notation.
SUB R5,R4,3 ;R5 = R4 - 3
might be written as:
SUB R5,R4,#3 ;R5 = R4 - 3
or
SBI R5,R4,3 ;R5 = R4 - 3
depending upon assembly language.

Logical Instructions
Performs bit-wise logical operation such as AND, OR, exclusive-
OR, or NOT. AND, OR, exclusive-OR operate upon pairs of bits of
two operands.
Bit-wise AND, OR, Ex-OR, and NOT are available in C and Java
(although you probably did not come across them!):
C/Java Language Examples
y = y & 1 ;bit-wise AND y with the number 1
z = z | 2 ;bit-wise OR z with the number 2

Machine Instruction Examples
AND R1,R2,R3 ;R1 = R2 “AND” R3
if R2 = 10100010100101011000010100001111
R3 = 01011011111010100010100010111010
then R1 = 00000010100000000000000000001010
OR R1,R2,R3 ;R1 = R2 “OR” R3
if R2 = 10100010100101011000010100001111
R3 = 01011011111010100010100010111010
then R1 = 11111011111111111010110110111111

Shift Instructions
Moves the bits of a location one or more places left or right.
Again available in C/Java (although you probably did not come
across them!):
Example
y = y << 1 ;shift y 1 place left 1
z = z >> 2 ;shift z 2 places right

Machine Instruction Examples
Examples
SHL R1,R1,1 ;Shift R1 left one place
SHR R1,R1,1 ;Shift R1 right one place
1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1
0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1 X
1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1
X 1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0
X - see next slide

Arithmetical and Logical Shifts
Two types of shift usually provided:
“Logical” shift (SHL, SHR)
Fill free end with 0, i.e. X = 0.
“Arithmetic” shift (SAL, SAR)
Arithmetic shifts multiple/divide by 2.
Arithmetic shift right maintains value of sign bit, i.e. X = value of
original sign bit.

Example
Starting with a number 9 000 ... 0001001
Shift arithmetic left one place. Get 18 000 ... 0010010
Shift arithmetic right two places. Get 4 000 ... 0000100
i.e. lose the 0.5.

Question
What is the difference, if any, between arithmetic shift left and
logical shift left, i.e. what is the difference, if any, between:
SHL R1, R1, 1
and
SAL R1, R1, 1
Answer

Arithmetic shift left same as logical shift left (except arithmetic
overflow may be detected).

Note: Java has logical shift right - called unsigned right shift, >>>.
Example
x = x >>> 2;

Question
What is the effect of the sequence?
SAL R1, R1, 1
SAR R1, R1, 1
Answer

Rotate Instructions
Moves bits of location one or more places left of right in a circular
fashion.
Examples
ROL R1,R1,1 ;Rotate R1 left one place
ROR R1,R1,1 ;Rotate R1 right one place
1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1
0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1 1
1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0 1
1 1 0 1 0 1 1 1 1 0 1 0 1 . . . 1 1 0

Control Flow
Compilers must translate statements such as:
if ((x != y) && (z < 0)) {
a = b + 5;
b = b + 1;
}
into machine instructions.
Unreasonable to try to provide a unique machine instruction for this
IF statement because of the vast number of possible IF statements.
Need to extract essential primitive operations for machine
instructions.

Decompose into simple IF statements of the form:
if (x relation y) goto L1;
where:
relation is any of usual relations allowed in high level languages
(<, >, >=, <=, ==, !=)
L1 is a label prefixed to an instruction to identify it.

i.e. translate
if ((x != y) && (z < 0)) {
a = b + 5;
b = b + 1;
}
...
into
if (x == y) goto L1;
if (z >= 0) goto L1;
a = b + 5;
b = b + 1;
L1: ...
Label

There is several ways of implementing the IF statement.
Here we will consider two ways:
1. Using one branch instruction.
2 Using two instructions, one to determine whether relationship is
true, and another to branch to L1 if true.

1. Using one branch instruction
Single “branch” machine instruction compares two registers and
goes to the labeled location if the condition is true, i.e.
Bcond Rs1, Rs2, L1
changes the execution sequence to the instruction labeled L1 if Rs1
cond Rs2 is true, where cond can be any of six possible
conditions, and Rs1 and Rs2 can be any of the 32 registers.

Conditional Branch Instruction op-codes
Bcond
Bcond Condition High level language
notation
BL Branch if less than <
BG Branch if greater than >
BGE Branch if greater or equal to >=
BLE Branch if less or equal to <=
BE Branch if equal ==
BNE Branch if not equal !=

Example
To implement
...
L1:
by a single machine instruction, we get:
BE R1,R2,L1
...
L1:
where the compiler allocates R1 for x and R2 for y.

Machine Instruction Encoding
The instruction
Bcond Rs1,Rs2,L1
requires an op-code (Bcond), the two source registers Rs1 and
Rs2, and L1 to be specified.
Op-code
Rs1 Rs2 L1Bcond
Note: Bcond is either BL, BG, BGE, BLE, BE, or BNE

Specifying “target” location L1
Several ways L1 could be specified in instruction:
Absolute (direct) addressingThe address of L1held in instruction.
(PC) Relative addressing The distance from branch instruction to
labeled instruction stored in instruction.
Program counter, see later

Absolute (direct) addressing
BE R1,R2,120
...
L1: ;location 120 say
Op-code
Rs1 Rs2 120Bcond
Note: Absolute addressing not used in our design.

(PC) Relative Addressing
BE R1,R2,+30 ;location 90 say
...
L1: ;location 120 say
Op-code
Rs1 Rs2 30Bcond
Actual number in instruction may be
different, see later.
Offset/displacement

Question
Devise possible binary encodings for branch instructions described.
Give the number of bits in each field, making any necessary
assumptions (The complete instruction has 32 bits.)
Answer

Question
How would one code:
if (x > y) x = 10;
with machine instructions where x and y are stored in R2 and R3
respectively?
Answer

2. Condition Code Register Approach
In this approach, we determine whether the Boolean condition in
is true by subtracting y from x and recognizing whether the result is
positive or negative, zero, or not zero:
relation x - y
< negative
> positive and not zero
>= positive or zero
<= negative or zero
== zero
!= not zero

Condition Code Register
The condition code register (CCR) contains a set of flags (single
bits) set in a fashion to be able to recognize the different possible
relationships (<, >, >=, <=, ==, !=), principally negative/posiitive and
zero/not zero.
Flags in condition code register indicate a particular aspect of the
result of the last arithmetic instruction. Usually a form of subtract
operation is first performed, although technically other arithmetic
and logical operations can affect the condition code register.

Sign Flag (S or N flag)
Indicates whether previous arithmetic result is negative or positive.
S = 1 for negative result
S = 0 for positive result.
S is actually the most significant (sign) bit of the result

Zero Flag
Zero flag, Z:
Z = 1 for result = 0
Z = 0 for result != 0
(Note zero is a positive number.)

Condition Code Register
Condition Code register normally closely linked to the ALU
(Arithmetic and Logic Unit):
ALU
Condition code
Internal buses
register
ZS
S – Sign flag
Z – Zero flag
Sample allocation of bits
Processor
(There are other bits used not yet described)
AnswerSource operands

,
Using Condition Code Register
Decompose IF statement such as:
if (x relation y) goto L1
into two sequential operations:
1. Subtract y from x which sets condition code register
according to result
2. Read condition code register and “branch” to L1 if specific
condition indicated

Step 1 Subtract and Set Condition Code Register
All arithmetic instructions set condition code register according to
the result of the arithmetic operation, but a compare instruction is
specifically provided, which is similar to a subtract instruction except
the result is not stored anywhere, only the CCR flags are set
according to the result.
Example
CMP R1, R2 ;R1 - R2, sets CCR flags

Step 2 Reading Condition Code Register and
Branching
A conditional branch instruction used to examine the values stored
in the condition code register to determine whether the specific
condition exists and to branch if it does.
All six conditions usually available:
BL Branch if less than
BG Branch if greater than
BGE Branch if greater or equal to
BLE Branch if less or equal to
BE (or BZ) Branch if equal
BNE (or BNZ) Branch if not equal

Example
Suppose x held in R1 and y held in R2. The if statement:
could be implemented by sequence of two instructions, CMP and BE:
CMP R1,R2 ;Compare contents of R1, R2 (x, y)
BE L1 ;Go to L1 if equal
L1:

Example
L1:
Z
Write
Condition code register
Z = 1 if R1 - R2 = zero otherwise Z = 0S

Example
L1:
Condition code register
Z = 1 if R1 - R2 = zero otherwise Z = 0
Read
Z
Write
S

Another Example
The if statement:
if (x < y) goto L1;
could be implemented by:
BL L1 ;Go to L1 if x less than y
L1:

Question
A processor uses a condition code register approach for branch
instructions. Write an assembly language sequence for the C/Java
code:
if ((a < b) && (a > 0)) b = a;
assuming that the variables a and b are assigned to registers R1
and R2 respectively. Provide comments. Use any reasonable
hypothetical instructions. (Note && is the symbol for the logical AND
operation.)

Answer

More complex constructions
if - then - else
Suppose we had to implement:
if (a < b) c = a; else a = c;
...
assuming that the variables a, b, and c are assigned to registers
R1, R2, and R3 respectively. Provide comments. Use any
reasonable hypothetical instructions.

Leads to:
CMP R1,R2 ;Compare R1, R2 (x, y)
BL L1 ;Go to L1 if a less than b
MOV R1, R3 ;a = c
L1: MOV R3,R1 ;c = a;
L2: ...
We need to alter the instruction sequence unconditionally. With the
instructions we know about so far, it could be done with:
CMP R1, R1
BE L2 ;if (x == x) goto L2;
but there is a special instruction called a jump instruction to do it.
skip over c = a

JUMP Instructions
Causes an unconditional change of execution sequence to a new
location. Necessary to implement more complicated IF constructs,
FOR, and WHILE loops.
Using J as the opcode mnemonic, the jump instruction is:
J L1 ;goto to L1

With jump instruction:
CMP R1,R2 ;Compare R1, R2 (x, y)
BL L1 ;Go to L1 if a less than b
MOV R1, R3 ;a = c
J L2
L1: MOV R3,R1 ;c = a;
L2: ...
goto L2

For loops
Suppose we had to implement the C/Java code sequence:
for (i = 1; i < 10; i++)
a = a * i;
...
The variable i is held in register R1, and the variable x is held in
register R2.
Possible solution
MOV R1, 1 ;i = 1
L2: CMP R1,10 ;Compare R1 with 10
BGE L1 ;Go to L1 if end of loop
MUL R2,R2,R1 ;a = a * i
ADD R1,R1,1 ;increment i
J L2
L1: ...

Mostly, conditional branch instructions used to implement small
changes in sequences or program loops of relatively short length,
so distance from the branch/jump to the target (label) quite small
(compared to full address of the labeled instruction).
Also good programming practice to limit sequence changes to
short distance from current location to avoid difficult to read code.
Relative addressing
Specify target location as number of instructions from branch/jump
instruction.
Also makes code relocatable. (i.e. code can be loaded anywhere in
memory without altering brancj/jump instructions.)

Program Counter (PC)
A register within the processor that holds the address of the next
instruction to execute.
PC-Relative Addressing
The number of locations to the target is held in the instruction as an
offset.
Offset is added to the program counter to obtain the effective
address.
Branch op-code Offset

Program Counter
Details
Let’s assume all instructions are 32 bits (four bytes) and each
addressable memory location is one byte.
PC hold address of instruction to be fetched from memory.
After the instruction fetched, PC incremented by 4 before executing
instruction.

Example code sequence
Address Instruction
72 MOV R1, 1
76 CMP R1,10
80 BGE L1
84 MUL R2,R2,R1
98 .
.
.
120 L1: ...
Program counter
80
Before instruction
BGE L1 fetched
from memory

Address Instruction
72 MOV R1, 1
76 CMP R1,10
80 BGE L1
84 MUL R2,R2,R1
88 .
.
.
120 L1: ...
Program counter
84
After instruction
BGE L1 fetched
from memory

Address Instruction
72 MOV R1, 1
76 CMP R1,10
80 BGE L1
84 MUL R2,R2,R1
88 .
.
.
120 L1: ...
Program counter
120
After instruction
BGE L1 executed

PC-Relative Addressing
Suppose the instruction BE L1 is at location whose address is 80
and L1 refers to location 120. The machine instruction might be as
below:
80: BE +36
120:
Program counter
84
Gives address of next
instruction to fetch after
current instruction fetched
+
address
of L1

Jump Instruction with Register-Indirect Addressing
An “address register” specified in instruction holds the address of
the location holding the next instruction to be executed.
Examples
J [R1] ;jump to location whose address in R1
J 100[R1] ;jump to location whose address given
;by R1 + 100
Target address specified as absolute address, rather than relative
address.
Used to implement high level language SWITCH statements. Also
return from procedures see next section.

Avoiding Condition Code Register
It turns out that the CCR approach has disadvantages when one
tries to implement a high performance processor, as we shall later.
It requires two sequential instructions with no instructions allowed in
between that affect the CCR. (All arithmetic/logic instruction affect
CCR.)
Alternative -- use a general purpose register in place of CCR to hold
“conditions.”

One solution -- Simplified version of branch
instruction
Bcond Rs1, L1
where Rs1 is compared against zero rather than Rs2.
Do subtract operation previous to this instruction, placing result in
Rs1.

Question
How would one code:
if (x > y) goto L1;
where x and y are stored in R2 and R3 respectively using previous
simplified version of branch instruction?
Answer

One version of branch instruction used in textbook
(MIPS processor)
Use a general pupose register set to 1 of 0 if one register is less
than another.
SLT Rs1,Rs2,Rs3 ;Rs1 = 1 if Rs2 < Rs3
together with a simple branch instruction that only tests condition
equal or not equal, i.e.:
BEQ Rs1, Rs2, L1 ;goto L1 if Rs1 = Rs2
and
BNE Rs1, Rs2, L1 ;goto L1 if Rs1 != Rs2

Using MIPS Branch Instruction
To do
if (x < y) goto L1;
where x and y are stored in R2 and R3 respectively, we might write:
SLT R1,R2,R3 ;R1 = 1 if R2 < R3
BNE R1,R0,L1 ;goto L1 if R1 != 0

Although MIPS approach for implementing if statements used in the
textbook, it is much more common to use a condition code register.
Pentium uses condition code register for historical reasons.
However, the condition code register approach makes it more
difficult to design a high-performance processor -- In our design
subsequently, we will use Bcond Rs1, L1 approach.

Sample exam questions

1. Write a suitable assembly language/machine instruction
sequence to implement the high level code sequence:
do {
a = a + b;
b++;
} while (b < 100);
assuming a load/store architecture. Variables a and b are declared
as integers and are held in processor registers R1, and R2,
respectively. Use any hypothetical but reasonable assembly
language. Provide comments.

Answer

2. A processor uses a condition code register approach for branch
instructions. Write an assembly language sequence for the C/Java
code:
do {
a = a - 2;
} while ((a < b) || (a > 0));
assuming that the variables a and b are assigned to registers R1
and R2 respectively. Provide comments. Use any reasonable
hypothetical instructions. (Note || is the symbol for the logical OR
operation.)

Answer

3. Write a suitable assembly language sequence to implement the
high level code sequence:
if (x > 10) a[x] = a[x + 1];
assuming a load/store architecture with only two instructions to
access memory, load a register from memory (LD) and store a
register into memory (ST) and both using register indirect
addressing plus offset. There are 32 registers R0 - R31. Register
R0 holds zero permanently. The array a is declared as a character
array and stored in memory starting at location 100, and x is held in
register R2. Make any necessary assumptions but state them. Use
any reasonable assembly language and provide comments.

Answer

4. Write a suitable assembly language sequence to implement the
C/Java code sequence:
for (i = 0; i < 10; i++)
a[x] = b[x];
assuming a load/store architecture -- Load (LD, LB), and store (ST,
SB) to access memoryusing register indirect addressing plus offset.
There are 32 registers R0 - R31. Register R0 holds zero
permanently. Array a and b are declared as character arrays and
stored in memory starting at memory addresses 100 and 200
respectively. The variable i is held in register R1, and the variable x
is held in register R2. Make any necessary assumptions but state
them. Use any reasonable assembly language and provide
comments.

Answer

Branches

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