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COGNITIVE POWER MANAGEMENT

                            Ahmed Eltawil
                            Professor
                            UC Irvine



Wednesday, November 7, 12
Cognitive Power
              Management
                            Ahmed Eltawil
                            Fadi Kurdahi
                            Muhammad S. Abdelghaffar
                            Amr M. Hussien


Wednesday, November 7, 12
The Power Challenge




                            3
Wednesday, November 7, 12
The Power Challenge




                            3
Wednesday, November 7, 12
The Power Challenge




                            Logic vs memory power
                            (ITRS)




                                                    3
Wednesday, November 7, 12
The Power Challenge

                            Power density limit of handheld




                               Logic vs memory power
                               (ITRS)




                                                              3
Wednesday, November 7, 12
The Power Challenge

                            Power density limit of handheld




                               Logic vs memory power
                               (ITRS)




                                                              3
Wednesday, November 7, 12
The Power Challenge

                                         Power density limit of handheld




                      1. Power is the key   Logic vs memory power
                      2. Embedded memories are
                                            (ITRS)




                         dominant



                                                                           3
Wednesday, November 7, 12
Concept                                                                          System Model

                                       Noisy
               Noisy                  Wireless
              Wireless                Receiver
              Channel

          Noise is
    uncontrollable and is
      a function of the     Errors are controllable!
        environment.           Errors and power
                               consumption are
                               inversely related.

           Current Design Approach

                            Specs

                                                        Overdriven Vdd
                                                         Nominal Vdd
                                                         Low Vdd
                                                                                                                                     Memory typically consumes
                                                         Aggressively                                                                        approximately
                                                         Low Vdd                                   Memory Array                   50% of the chip area and/or power


                                                                             x
                                                                                                                          Management Cycle
       System Design:                Circuit Design:               Memory noise and power                     ü Observe the channel statistics and system state
      Assume worst case
      wireless conditions
                                    Minimize noise at             consumption can be directly                 üTake the action and modulate the supply voltage
                                    expense of power
                                                                controlled by the supply voltage              ü Monitor performance metrics such as BER, PSNR and




Wednesday, November 7, 12
CPM Approach
   n     Created a statistical model for both
          Channel+HW noise
   n     Created a new class of FEC decoders for
          combined Channel and hardware noise
          q     Viterbi, Turbo, LDPC
          q     Negligible hardware overhead 0.013%-0.65%
   n     Created a design exploration framework
          for designers to easily experiment with
          different power management schemes by
          propagating error statistics through the
          system.
   n     Approach is not limited to data path
          memories but can be extended to control
          memories and logic with some
          modifications.




Wednesday, November 7, 12
CPM Approach
   n     Created a statistical model for both
          Channel+HW noise
   n     Created a new class of FEC decoders for
          combined Channel and hardware noise
          q     Viterbi, Turbo, LDPC
          q     Negligible hardware overhead 0.013%-0.65%
   n     Created a design exploration framework
          for designers to easily experiment with
          different power management schemes by
          propagating error statistics through the
          system.
   n     Approach is not limited to data path
          memories but can be extended to control
          memories and logic with some
          modifications.




Wednesday, November 7, 12
Technology Demonstration




                  Matlab
                  Demonstration             Experimental FEC
            http://www.youtube.com/watch?   Demonstration
            v=XI9E7Fr5TNY.                  http://www.youtube.com/watch?v=h1yKDcGLLb0




Wednesday, November 7, 12
Wednesday, November 7, 12
Wednesday, November 7, 12

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COGNITIVE POWER MANAGEMENT from Mobilize 2012

  • 1. COGNITIVE POWER MANAGEMENT Ahmed Eltawil Professor UC Irvine Wednesday, November 7, 12
  • 2. Cognitive Power Management Ahmed Eltawil Fadi Kurdahi Muhammad S. Abdelghaffar Amr M. Hussien Wednesday, November 7, 12
  • 3. The Power Challenge 3 Wednesday, November 7, 12
  • 4. The Power Challenge 3 Wednesday, November 7, 12
  • 5. The Power Challenge Logic vs memory power (ITRS) 3 Wednesday, November 7, 12
  • 6. The Power Challenge Power density limit of handheld Logic vs memory power (ITRS) 3 Wednesday, November 7, 12
  • 7. The Power Challenge Power density limit of handheld Logic vs memory power (ITRS) 3 Wednesday, November 7, 12
  • 8. The Power Challenge Power density limit of handheld 1. Power is the key Logic vs memory power 2. Embedded memories are (ITRS) dominant 3 Wednesday, November 7, 12
  • 9. Concept System Model Noisy Noisy Wireless Wireless Receiver Channel Noise is uncontrollable and is a function of the Errors are controllable! environment. Errors and power consumption are inversely related. Current Design Approach Specs Overdriven Vdd Nominal Vdd Low Vdd Memory typically consumes Aggressively approximately Low Vdd Memory Array 50% of the chip area and/or power x Management Cycle System Design: Circuit Design: Memory noise and power ü Observe the channel statistics and system state Assume worst case wireless conditions Minimize noise at consumption can be directly üTake the action and modulate the supply voltage expense of power controlled by the supply voltage ü Monitor performance metrics such as BER, PSNR and Wednesday, November 7, 12
  • 10. CPM Approach n Created a statistical model for both Channel+HW noise n Created a new class of FEC decoders for combined Channel and hardware noise q Viterbi, Turbo, LDPC q Negligible hardware overhead 0.013%-0.65% n Created a design exploration framework for designers to easily experiment with different power management schemes by propagating error statistics through the system. n Approach is not limited to data path memories but can be extended to control memories and logic with some modifications. Wednesday, November 7, 12
  • 11. CPM Approach n Created a statistical model for both Channel+HW noise n Created a new class of FEC decoders for combined Channel and hardware noise q Viterbi, Turbo, LDPC q Negligible hardware overhead 0.013%-0.65% n Created a design exploration framework for designers to easily experiment with different power management schemes by propagating error statistics through the system. n Approach is not limited to data path memories but can be extended to control memories and logic with some modifications. Wednesday, November 7, 12
  • 12. Technology Demonstration Matlab Demonstration Experimental FEC http://www.youtube.com/watch? Demonstration v=XI9E7Fr5TNY. http://www.youtube.com/watch?v=h1yKDcGLLb0 Wednesday, November 7, 12