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COGNITIVE POWER MANAGEMENT from Mobilize 2012
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COGNITIVE POWER MANAGEMENT from Mobilize 2012

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Ahmed Eltawil, UC Irvine

Ahmed Eltawil, UC Irvine
#mobilizeconf
More at http://event.gigaom.com/mobilize/

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    COGNITIVE POWER MANAGEMENT from Mobilize 2012 COGNITIVE POWER MANAGEMENT from Mobilize 2012 Presentation Transcript

    • COGNITIVE POWER MANAGEMENT Ahmed Eltawil Professor UC IrvineWednesday, November 7, 12
    • Cognitive Power Management Ahmed Eltawil Fadi Kurdahi Muhammad S. Abdelghaffar Amr M. HussienWednesday, November 7, 12
    • The Power Challenge 3Wednesday, November 7, 12
    • The Power Challenge 3Wednesday, November 7, 12
    • The Power Challenge Logic vs memory power (ITRS) 3Wednesday, November 7, 12
    • The Power Challenge Power density limit of handheld Logic vs memory power (ITRS) 3Wednesday, November 7, 12
    • The Power Challenge Power density limit of handheld Logic vs memory power (ITRS) 3Wednesday, November 7, 12
    • The Power Challenge Power density limit of handheld 1. Power is the key Logic vs memory power 2. Embedded memories are (ITRS) dominant 3Wednesday, November 7, 12
    • Concept System Model Noisy Noisy Wireless Wireless Receiver Channel Noise is uncontrollable and is a function of the Errors are controllable! environment. Errors and power consumption are inversely related. Current Design Approach Specs Overdriven Vdd Nominal Vdd Low Vdd Memory typically consumes Aggressively approximately Low Vdd Memory Array 50% of the chip area and/or power x Management Cycle System Design: Circuit Design: Memory noise and power ü Observe the channel statistics and system state Assume worst case wireless conditions Minimize noise at consumption can be directly üTake the action and modulate the supply voltage expense of power controlled by the supply voltage ü Monitor performance metrics such as BER, PSNR andWednesday, November 7, 12
    • CPM Approach n Created a statistical model for both Channel+HW noise n Created a new class of FEC decoders for combined Channel and hardware noise q Viterbi, Turbo, LDPC q Negligible hardware overhead 0.013%-0.65% n Created a design exploration framework for designers to easily experiment with different power management schemes by propagating error statistics through the system. n Approach is not limited to data path memories but can be extended to control memories and logic with some modifications.Wednesday, November 7, 12
    • CPM Approach n Created a statistical model for both Channel+HW noise n Created a new class of FEC decoders for combined Channel and hardware noise q Viterbi, Turbo, LDPC q Negligible hardware overhead 0.013%-0.65% n Created a design exploration framework for designers to easily experiment with different power management schemes by propagating error statistics through the system. n Approach is not limited to data path memories but can be extended to control memories and logic with some modifications.Wednesday, November 7, 12
    • Technology Demonstration Matlab Demonstration Experimental FEC http://www.youtube.com/watch? Demonstration v=XI9E7Fr5TNY. http://www.youtube.com/watch?v=h1yKDcGLLb0Wednesday, November 7, 12
    • Wednesday, November 7, 12
    • Wednesday, November 7, 12