Converting a Single-Ended Signal with the AD7984 Differential PulSAR ADC

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Discussion of the reference design converting a single-ended input signal to a differential signal for use with the AD7984

Discussion of the reference design converting a single-ended input signal to a differential signal for use with the AD7984

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  • 1. Converting a Single-Ended Signal with the AD7984 Differential PulSAR ADC
    • Source: ANALOG DEVICES
  • 2. Introduction
    • Purpose
      • This training module discusses the reference design converting a single-ended input signal to a differential signal for use with the AD7984 18-bit, PULSAR® ADC, and selected the ADA4941 ADC driver and the ADR435 ultra-low noise voltage reference.
    • Outline
      • Comparison between single-ended and differential inputs
      • PulSAR conversion technique
      • Overview of AD7984 ADC
      • Discussion of the verified circuits
    • Content
      • 13 pages
  • 3. Single-Ended vs. Differential Inputs
    • In single-ended inputs, one wire is connected from each signal source to the data acquisition interface.
      • All inputs are referenced to a common ground.
      • Disadvantage: Single-ended inputs are sensitive to noise errors.
    • With differential inputs, two signal wires run from each signal source.
      • One goes to a + input and one to a - input.
      • Disadvantage: They need twice as many wires to single-ended inputs
  • 4. PulSAR ® Technique
    • In the acquisition phase, the switches are closed to be connected to the IN+ and IN- analog inputs, thus each capacitor is used as a sampling capacitor acquiring the analog signal at the input.
    • In the conversion phase, the analog inputs are disconnected from the internal capacitors and applied to the comparator inputs.
    • Switching each element of the array between REF and REFGND starting with the MSB, brings the comparator back into a balanced condition and thus generates the output code representing the analog input signal.
  • 5. Overview of the AD7984
    • 18-bit resolution with no missing codes
    • Throughput: 1.33 MSPS
    • Low power dissipation: 10.5 mW at 1.33 MSPS
    • INL: ±2.25 LSB maximum
    • True differential analog input range: ±V REF 0 V to V REF with V REF between 2.9 V to 5.0 V
    • Dynamic range: 99.7 dB typical
    • No pipeline delay
    • Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface
    • SPI-compatible serial interface
    • Ability to daisy-chain multiple ADCs and busy indicator
  • 6. Analog Inputs of the AD7984
    • The analog input structure allows the sampling of the true differential signal between IN+ and IN−.
    • D1 and D2 provide ESD protection for the IN+ and IN- analog inputs.
      • They can handle a forward-biased current of 130 mA maximum .
    • The analog input signal can not exceed the reference input voltage (REF) by more than 0.3V.
      • If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current.
    Equivalent Analog Input Circuit
  • 7. Driving the AD7984
    • The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7984.
      • The typical noise of the AD7984 is 36.24μV rms
      • The SNR degradation due to the amplifier is
    • For AC applications, the driver should have a THD performance commensurate with the AD7984.
    • For multi-channel multiplexed applications, the driver amplifier and the AD7984 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4ppm).
  • 8. ADA4941 Single-Ended to Differential Driver
    • The voltage applied to the REF pin appears as the output common-mode voltage.
    • The voltage applied to the REF pin does not affect the voltage at the OUT+ pin.
    • Differential offset can exist between the outputs, while the desired output common-mode voltage is present.
    A2 A1
  • 9. The ADA4941 Driving the AD7984
    • R1 and R2 set the attenuation ratio between the input range and the ADC range.
    • The ratio of R2 to R1 should be equal to the ratio of REF to the peak-to-peak input voltage.
    • R3 and R4 set the common mode on the IN− input.
    • R5 and R6 set the common mode on the IN+ input of the ADC.
    V IN
  • 10. Verified Circuit Verified Circuits are designed for ease of use and proven to work by ADI.
  • 11. Resistors Selections for the Verified Circuit
    • The ADC’s common mode, which is equal to the voltage present at Voffset1, should be close to VREF/2.
    • The voltage present at Voffset2 should roughly be set to the ratio of Voffset1 to 1+R2/R1.
    10.00K Ω 20.0K Ω 1.00K Ω 2.00K Ω 5.00, 0.00 0.00, 5.00 1.667 2.5 ±5.5 10.00K Ω 15.0K Ω 1.00K Ω 4.02K Ω 4.99, 0.01 0.01, 4.99 2.000 2.5 ±10 10.00K Ω 12.70K Ω 1.00K Ω 8.06K Ω 5.01, 0.04 -0.01, 4.96 2.203 2.5 ±20 R3=R5=R6 R4 R2 R1 OUTN OUTP V offset2 V offset1 V IN
  • 12. Power Supply for the AD7984
    • The digital input/output interface supply (VIO) allows direct interface with any logic between 1.8 V and 5.5 V.
    • To reduce the number of supplies needed, VIO and VDD can be tied together.
    • The AD7984 is independent of power supply sequencing between VIO and VDD.
    • To ensure optimum performance, VDD should be roughly half of REF, the voltage reference input.
      • If REF is 5.0 V, VDD should be set to 2.5 V (±5%).
  • 13. Additional Resource
    • For ordering the AD7984 and selected parts, please click the part list or
    • Call our sales hotline
    • For additional inquires contact our technical service hotline
    • For more product information go to