5. Basic Functions ( 계속 )

7. Basic Identities of Boolean Algebra The relationship between a single variable X, its complement X  , and the binary constants 0 and 1

26. Look at (A +B +C + D)’ = A’ • B’ • C’ • D’

30. Truth Table from Logic Circuit A(B+CD)=m11+m12+m13+m14+m15 =  (11,12,13,14,15) Output Input 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 A(B+CD) D C B A

42. Boolean Expression Truth Table Logic Diagram

45. Three- and Four-input Kanaugh maps Gray code

48. Gray code sequence generation

49. F(X,Y,Z)=  m(0,1,2,6) =(XY  +YZ)  =X’Y’ + YZ’

51. Example) F(X,Y,Z)=  m(0,2,4,6) = X  Z  +XZ  =Z  (X  +X)=Z 

55. F(W, X,Y,Z)=  m(0,2,7,8,9,10,11) = WX’ + X’Z’ + W’XYZ

65. Mapping Directly from a Truth Table

80. PAL Block Diagram

81. PAL Output Combinational Logic X  0=X X  1=X’

82. A Specific PAL Figure 4-50 Block diagram of the PAL16L8 .

84. Figure 4-52 GAL implementation of a sum-of-products expression.

88. GAL20V8 High Performance E2CMOS PLD Generic Array Logic™

90. -- Program X=(AC+(BC’)’+D)’+((BC)’)’=(A’+C’)(BC’)D’+BC -- =A’BC’D’+BC’D’+BC=(A’+1)BC’D’+BC = BC’D’+BC entity alogicft is port(B, C, D: in bit; X: out bit); end entity alogicft; architecture expaft of alogicft is begin X<= (B and not C and not D) or (B and C); end architecture expaft;

91. Levels of Abstraction for sequential logic circuits VHDL (1) Behavioral approach : state diagram or truth table (2) Data flow approach : Boolean expression or function (3) Structure approach : logic diagram or schematic describing logic function

92. Digital System Application : 7-Segment LED Driver Seven-Segment LED driver

94. Figure 4-59 Karnaugh map minimization of the segment- a logic expression.

95. Figure 4-60 The minimum logic implementation for segment a of the 7-segment display.

96. -- Program 7-segment driver entity sevensegdrv is port(A, B, C, D: in bit; a,b,c,d,e,f,g: out bit); end entity sevensegdrv; architecture segment of sevensegdrv is begin a<= B or D or (A and C) or (not A and not C); -- B +D+AC+A’C’ • • • • • • • • • g<= A or B and C’ or not B and C or C and not D; -- A+BC’+B’C+CD’ end architecture segment; VHDL for 7-Segment Driver

98. The relationship between a single variable X, its complement X  , and the binary constants 0 and 1

100. Boolean Expression Truth Table Logic Diagram VHDL (HDL)

101. End of Ch. 4