Efficient coding schemes for fault tolerant parallel filters Contact: IIS TECHNOOGIES ph:9952077540,landline:044 42637391

1. Efficient Coding Schemes for Fault Tolerant Parallel
Filters
Presented by
IIS TECHNOLOGIES
No: 40, C-Block,First Floor,HIET Campus,
North Parade Road,St.Thomas Mount,
Chennai, Tamil Nadu 600016.
Landline:044 4263 7391,mob:9952077540.
Email:info@iistechnologies.in,
Web:www.iistechnologies.in
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2. ABSTRACT
• As the complexity of communications and signal processing systems increases, so does the
number of blocks or elements that they have. In many cases, some of those elements
operate in parallel performing the same processing on different signals.
• A typical example of those elements are digital filters.
• The increase in complexity also poses reliability challenges and creates the need for fault
tolerant implementations.
• A scheme based on error correction coding has been recently proposed to protect parallel
filters.
• In that scheme, each filter is treated as a bit and redundant filters that act as parity check bits are
introduced to detect and correct errors.
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3. ABSTRACT
• In this paper, the idea of applying coding techniques to protect parallel filters is addressed in a
more general way.
• In particular, it is shown that the fact that filter inputs and outputs are not bits but
numbers enables a more efficient protection.
• This reduces the protection overhead and makes the number of redundant filters
independent of the number of parallel filters.
• The proposed scheme is first described and then illustrated with two case studies.
• Finally, both the effectiveness in protecting against errors and the cost are evaluated for an
FPGA implementation.
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4. FLOW CHART
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5. CIRCUIT DIAGRAM
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6. TOOLS AND SOFTWARE USED
Software
• Simulation: Modelsim.
• Synthesize: Xilinx ISE.
Hardware
• FPGA-Spartan3E.
Language
• HDL- Hardware Description Language.
Note : Output will been shown proposed module in kit.
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7. Advantages
• Smaller Size,
• High Speed,
• High Performance,
• Low Power.
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8. Future Enhancement
• In this project the some error correcting code can be designed and
can be expanded with newer lower bit or higher bit architecture and
concluded with FPGA parameters such as AREA ,delay and power can
be determined.
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9. OUTPUT
• HARDWARE
• SIMULATION
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10. Contact
IIS TECHNOLOGIES
No: 40, C-Block,First Floor,HIET Campus,
North Parade Road,St.Thomas Mount,
Chennai, Tamil Nadu 600016.
Landline:044 4263 7391,mob:9952077540.
Email:info@iistechnologies.in,
Web:www.iistechnologies.in
www.iistechnologies.in