9. Software Defined Networking (SDN)
API to the data plane
(e.g., OpenFlow)
Logically-centralized control
Smart,
slow
10. NetFPGA as OPENFLOW SWITCH
FGPA
Modules 1
SoftwareHardware
Linux user-level
processes
Verilog on
NetFPGA PCI board
Linux
Processes
FGPA
Modules 2
11. Example: An IP Router on NetFPGA
Switching
Engine
Forwarding
Engine
Routing
Table
Switching
Table
Management
& CLI & API
SoftwareHardware
Linux user-level
processes
Verilog on
NetFPGA PCI board
Exception
Processing
Forwarding
Table
12. FPGA
Memory
10GE
10GE
10GE
10GE
PLAN1
NetFPGA board on PC
PCIe
CPU Memory
PC with NetFPGA
Networking
Software
running on a
standard PC
A hardware
accelerator
built with a Field
Programmable
Gate Array
driving 10 Gigabit
network links
15. Link between
switches facilitates
coordination, fail-
over
Redundant switches
increase system
availability, eliminates
single point of failure
Nodes support
redundant links,
one to each switch
Number of routed
channelsTwo dedicated
system slots for
switching
resources
ATCA Backplane – Fabric topologies – Dual Star
16. Data throughput
capacity scales
with each added
node board,
large capacities
possible
Fabric links are
inherently
redundant,
highly available
All system slots are
identical. No dedicated
hub slots. All slots are
hub capable
Switching services
and managment are
distributed across all
system slots
ATCA Backplane – Fabric topologies – Mesh
17. 17
ATCA Blades
Promise of Mix-n-match
CPU Blade
NetFPGA Blades
Enables “one-blade”
applications
Core of the NETFPGA Router
architecture
Diagram courtesy PICMG
Editor's Notes
Maybe this is a better picture… though need some details of what happens in each plane… like in next slides… or, have both?
Maybe this is a better picture… though need some details of what happens in each plane… like in next slides… or, have both?