This document summarizes the results of simulating a two-stage 130nm RF CMOS power amplifier designed for 2.4GHz applications. The power amplifier was simulated with variations in supply voltage from 1V to 5V and size of the second stage transistor from 150um to 500um. Supply voltage significantly impacted output power, ranging from 10.684dBm to 25.08dBm at 1dB compression point. Transistor size also impacted output power but to a lesser degree, from 15.47dBm to 20.338dBm. Power added efficiency was maximized at intermediate supply voltages and transistor sizes, from 16.65% to 48.46% and 29.085% to 45.439% respectively

1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
A 10 dBm-25 dBm, 0.363 mm2 TWO STAGE
130 nm RF CMOS POWER AMPLIFIER
Shridhar R. Sahu1 and Dr. A. Y. Deshmukh2
1
Research Scholar, Department of Electronics Engineering, G. H. Raisoni College of
Engineering, Nagpur, India
2
Professor, Department of Electronics Engineering, G. H. Raisoni College of
Engineering, Nagpur, India
Abstract
This paper proposes a 2.4 GHz RF CMOS Power amplifier and variation in its main performance
parameters i.e, output power, S-parameters and power added efficiency with respect to change in supply
voltage and size of the power stage transistor. The supply voltage was varied form 1 V to 5 V and the range
of output power at 1dB compression point was found to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width of the power stage transistor was varied from 150 µm
to 500 µm to achieve output power of range 15.47 dBm to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the layout comes out to be 0.714 * 0.508 mm2.
Keywords
RF CMOS, PAE, Output Power, S-parameters, Matching Networks
1. INTRODUCTION
CMOS RFICs are Radio Frequency Integrated circuits in CMOS technology operated in radio
frequency range. RF Power Amplifiers are part of the transmitter front-end used to amplify the
input power to be transmitted [1][3].
The main performance parameters for the power amplifier are the level of output power it can
achieve, depending on the targeted application, linearity, and efficiency. The two basic definitions
for the efficiency of the power amplifier are drain efficiency (DE) which is the ratio between the
RF output power to the dc power dissipated, and the power added efficiency (PAE) which is the
ratio between the difference of the RF output power and the RF input power to the total dc power
of the circuit. The PAE is a more practical measure as it is responsible for the power gain of the
amplifier [1].
DOI : 10.5121/vlsic.2013.4509
107

2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
DE =
P
out ( RF )
P
dc
(2)
RFICs are fabricated using CMOS, GaAs Hetero-Junction Bipolar Transistor (HBT), SiGe
BiCMOS, , GaN High Electron Mobility Transistor (HEMT) technologies. Existing power
amplifiers mostly use GaAs (Gallium Arsenide) or GaN (Gallium Nitride) for high output power.
But it also leads to high power dissipation, large chip area and more cost. The GaAs technology
provides high output power at high frequency, but it is quite expensive and the uniformity of the
device structure may be affected due to process variations [6]. The GaN process also operates at
higher frequencies and deals with high power capacity but due to wide band gap materials used
more voltage supply is needed for operation which in turn leads to high power dissipation [7].
CMOS power amplifiers can also be operated at high frequencies and by using some techniques
output power can be increased. CMOS power amplifiers show more linearity as compared to
GaAs and GaN technologies. As CMOS can operate on low power supplies there is drastic
decrease in overall power dissipation of the circuit and hence better PAE can be expected. CMOS
power amplifiers are cost effective and use minimum chip area for fabrication.
The main objective behind this paper is to design a CMOS Power Amplifier for 2.4 GHz WLAN
application and observe change in its important parameters such as s-parameters, output power,
power added efficiency with change in supply voltage and size of the power stage transistor. The
tool used for designing this circuit is ADS (Advanced Design System) tool of Agilent Systems.
This circuit is designed in RFCMOS 130 nm technology. The layout of this paper is follows:
Initially this paper deals with the schematic of the CMOS power amplifier, then the simulation
results obtained by varying supply voltage and size of second stage transistor. Layout of the
designed circuit is drawn in Tanner Tool. Finally, conclusions are drawn out after observing the
simulation results.
2. SCHEMATIC
A schematic of the CMOS power amplifier is shown in the figure 1. Driver stage and Power stage
with the supply and bias network are main parts of the power amplifier. A cascode topology is
used in the driver stage and a basic power amplifier topology is used in the power stage. The
circuit is operated in 2.4 GHz ISM band.
vdd
L
L3
R
R2
T SMC_CM013RF_PMOS vdd
M4
V _DC
V1
V dc=2.5 V
L
L4
L
L6
C
C6
C
C3
C
C4
L
L5
C
C2
T SMC_CM013RF_NMOS_RF
M2
R
R3
V load
I_Probe
I_Probe1
T erm
T erm1
T SMC_CM013RF_NMOS_RF
M3
vdd
R
R1
T SMC_CM013RF_PMOS
M6
T SMC_CM013RF_NMOS
M7
T S MC_CM013RF_NMOS
M5
C
C1
C
C5
L
L1
P_1T one
PORT 1
Freq=2.4 GHz
T SMC_CM013RF_NMOS_RF
M1
L
L2
Fig. 1. Schematic of complete Two Stage CMOS Power Amplifier
108

3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
A cascode topology is implemented in the first stage. The transistor M1 is the main amplifying
device of this stage and transistor M2 is cascaded with M1. An inductor of a large value is
connected between the drain of M2 and VDD which opposes the change in current and the
cascaded transistor is to prevent large flow of drain current through M1. The transistor M2 is
biased in saturation. Transistor M1 is biased by a MOSFET only bias circuit whose output is 0.5
Volts to operate in triode region. The transistor was first analyzed with different biasing voltages
and found to be operating better at 0.5 V in similar conditions. An input matching network is
connected to the driver stage i.e., the input stage for input impedance matching. For this matching
purpose gate inductance Lg (L1) and source inductance Ls (L2) are used. The values of these
inductances and the size of the transistors are such selected that the operation of the circuit is
tuned to the resonance frequency of 2.4 GHz. The gate length of the transistors is fixed at 130nm
and the width of gate is varied. The output power of this topology is not as high as the power
stage but the isolation provided between output and input is very high. Also the dc power
consumed by this circuit is far less than the power stage circuit. The dc current through this stage
is 6.31 mA at 2.5 V.
The second stage is mainly responsible for power amplification considering the overall circuit.
The size of the transistor used in this stage is large as compared to the size the transistors used in
the driver stage. A big fat inductance is connected between the dc supply and the drain of the
transistor M3. The output of the driver stage is fed to the gate of the transistor M3 through the
capacitor C6. The dc current here is controlled by varying the size of the transistor. The
amplification of the signal also depends on the bias voltage supply. Bias voltage is 0.75 V. Output
matching network is connected at the output side for output impedance matching. Here, a LC tank
circuit is designed for matching purpose and to tune the circuit to its operating frequency, so that
the output return loss is better at resonance frequency. The total dc current of this stage comes out
to be 83.5 mA at 2.5 V.
3. SIMULATION RESULTS
S – Parameters are an important part of Power amplifiers. There are four s-parameters essential to
observe after designing a power amplifier. They are input return loss S(1,1), output return loss
S(2,2), gain S(2,1) and isolation loss S(1,2).
Power calculations are carried out at 1dB compression point of the gain of the circuit. As shown
in the figure 3, graph of gain in dB is plotted v/s input power in dBm. According to the figure
1dB compression point is obtained at -22.7 dBm of input power. Output power is observed at the
same input power which comes out to be 20.028 dBm. This output power is known as output
power at 1dB compression point. The maximum output power delivered by this circuit is 22.002
dBm. The unit used for power calculations of a power amplifier is dBm instead of watts. The
conversion of watts to dBm and dBm to watts is given as in equation (3). The equation for power
gain is given as in equation (5).
Power added efficiency; the factor by which the power amplifiers are analyzed is the deciding
parameter between different types of power amplifiers. This CMOS power amplifier operating at
2.4 GHz with a main supply of 2.5 V gives PAE of 44.669 % at 1dB compression point. The
maximum PAE achieved by the circuit is 70.196 %. These values can be observed in figure 8
where on left y axis pout is plotted and on right y axis PAE is plotted. The equations for the same
are given in equation 6, 7 and 8.
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4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
P(W )
)
1mW
P(dBm) = 10 × log(
(
P (W ) = 10
P ( dBm )
−3 )
10
(4)
P
P
P ( dB ) = 10 × log(
PAE
PAE
=
P
out (1dB )
P
out
(W )
(W )
in
)
(5)
(W ) − P in (1dB ) (W )
P
out (max)
dc
(W )
(6)
(W ) − Pin (W )
P
dc
(W )
(7)
= V dd × I dc
(8)
m1
freq= 2.400GHz
dB(S(1,1))=-11.132
m2
freq= 2.400GHz
dB(S(2,2))=-12.467
m4
m3
50
-60
40
-80
m3
freq= 2.400GHz
dB(S(2,1))=43.745
30
10
-120
m1
m2
-10
-140
dB (1 ))
(S ,2
-100
20
0
m4
freq= 2.400GHz
dB(S(1,2))=-61.889
-160
-20
0.0
0.5
1.0
1. 5
2. 0
2.5
3.0
3.5
4.0
4.5
5.0
f req, GHz
Fig. 2. S - Parameters
m5
45
m6
m5
pin= -45.800
gain=43.752
40
35
G in( B
a d)
dc
max
=
d (S ,1))
B (1
d (S ,1))
B (2
d (S ,2))
B (2
P
1dB
(3)
30
m6
pin= -22.700
gain=42.728
25
20
15
10
-50
-40
-30
-20
-10
0
10
Pin (dBm)
Fig. 3. Obtaining 1dB compression point
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5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
m8
pin= -3.900
pout=22.002
Max
m8
m7
pin= -22.700
pout=20.028
25
m7
100
20
m9
pin= -22.700
PAE=44.669
80
m10
60
10
m9
m10
pin= -3.900
PAE=70.196
Max
5
0
40
PAE (%
)
Pout (dBm)
15
20
-5
0
-10
-50
-40
-30
-20
-10
0
10
Pin (dBm)
Fig. 4. Output Power and Power Added Effciency
3.1 Variation in Output Power, S-Parameters and PAE with change in Supply
Voltage
The supply voltage was varied from 1 V to 5 V. The operating frequency was kept constant i.e,
2.4 GHz. The values of s-parameters, output power, PAE achieved are tabulated in table 1. The
range of output power at 1dB compression point observed is 10.684 dBm to 25.08 dBm. The
range of maximum output power is 14.286 dBm to 27.217 dBm. Power added efficiency at 1dB
compression point is calculated to be 16.65 % at 1 V to 48.46 % at 3.3 V. Maximum PAE is
38.12 % at 1 V to 77.407 % at 3.3 V. The overall DC current observed here is 70.23 mA at 1 V to
168 mA at 5 V. These results can also be observed in figures 5, 6, & 7.
3.2 Variation in Output Power, S- parameters and PAE with change in Size of
Power stage Transistor
Initially the width of the second stage transistor was 300 µm, i.e, 30 gate fingers with 10 µm
width of single gate finger. The number of gate fingers was varied to change the size of the
transistor. The gate fingers were varied from 15 to 50 numbers making the width effectively 150
µm to 500 µm. The results obtained are tabulated in table 2. The operating voltage and operating
frequency were kept constant at 2.5 V and 2.4 GHz respectively. The number of gate fingers here
is denoted as F. The range of output power at 1dB compression point observed is 15.47 dBm to
20.338 dBm. The range of maximum output power is 20.702 dBm to 22.354 dBm. Power added
efficiency at 1dB compression point is calculated to be 29.085 % at 150 µm gate width to 45.439
% at 25 um gate width. The overall DC current observed here is 48.4 mA at 15 gate fingers to
143.7 mA at 50 gate fingers. These results can also be observed in figures 8, 9, & 10.
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6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
m16
pin= -14.800
pout=14.286
Vdd=1.000000
Max
m7
pin= -29.800
pout=10.684
Vdd=1.000000
30
Pout (dBm)
20
m15
pin= -3.500
pout=22.098
Vdd=2.500000
Max
m18
m14
pin= -2.100
pout=27.217
Vdd=5.000000
Max
m14
Vdd=5.000
Vdd=3.300
Vdd=3.000
Vdd=2.500
Vdd=1.800
m15
m17
m16
Vdd=1.200
Vdd=1.000
m7
10
m17
pin= -22.700
pout=20.021
Vdd=2.500000
0
m18
pin= -18.700
pout=25.080
Vdd=5.000000
-10
-50
-40
-30
-20
-10
0
Pin (dBm)
Fig. 5. Output Power at different supply voltages
m26
indep(m26)= -44.400
plot_vs(Idc, pin)=-70.291
Vdd=1.000000
m26
0
Idc (mA)
-50
m24
indep(m24)= -16.000
plot_vs(Idc, pin)=-90.048
Vdd=2.500000
Vdd=1.000
Vdd=1.200
Vdd=1.800
Vdd=2.500
Vdd=3.000
Vdd=3.300
m24
-100
m25
indep(m25)= -12.400
plot_vs(Idc, pin)=-167.923
Vdd=5.000000
-150
m25
Vdd=5.000
-200
-50
-40
-30
-20
-10
0
Pin (dBm)
Fig. 6. Total DC Current at different Supply voltages
100
PAE (%
)
80
60
40
m20
pin= -14.800
PAE=38.120
Vdd=1.000000
Max
m21
pin= -29.800
PAE=16.651
Vdd=1.000000
m22
pin= -3.500
PAE=71.818
Vdd=2.500000
Max
m22
m19
m23
pin= -22.700
PAE=44.635
Vdd=2.500000
m23
m9 m20
Vdd=3.300
Vdd=3.000
Vdd=2.500
Vdd=5.000
Vdd=1.800
Vdd=1.200
Vdd=1.000
m9
pin= -18.700
PAE=38.361
Vdd=5.000000
m21
20
m19
pin= -2.200
PAE=62.680
Vdd=5.000000
Max
0
-50
-40
-30
-20
-10
0
Pin (dBm)
Fig. 7. Power Added Efficiency at different supply voltages
112

7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Table 1. Variation in Output Power, S- Parameters and PAE with change in Supply voltage
OperatingS – Parameters (dB)
Voltage
(V)
Vdd
S(1,1)
S(2,2)
1.0
-10.928
-12.048
1.2
-11.569
-12.804
1.8
-12.477
-13.467
2.5
-11.132
-12.467
3
-10.034
-11.368
3.3
-9.579
-10.738
5
-6.285
-8.32
S(2,1)
41.474
42.227
43.403
43.745
43.813
43.891
44.769
Total Dc
Current
(mA)
IDC
70.3
72.6
79.5
90.05
100
108
168
S(1,2)
-60.822
-60.992
-61.367
-61.889
-62.39
-62.755
-65.214
Output Power
(dBm)
Power Added
Efficiency (%)
Pout1dB
10.684
12.612
16.724
20.021
21.6
22.365
25.08
PAE1dB PAEmax
16.65 38.12
20.952 44.213
31.958 63.854
44.635 71.818
48.01 76.279
48.466 77.407
38.361 62.68
Poutmax
14.286
15.86
19.327
22.098
23.623
24.411
27.217
Operating Frequency: 2.4 GHz
P u (d m
ot B )
m12
pin=-5.000
pout=20.706
Fingers=15.000000
Max
25
m11
pin=-27.500
pout=15.470
20
Fingers=15.000000
m24
pin=-3.900
pout=22.002
Fingers=30.000000
Max
m25
m23
m22
pin= -8.100
pout=22.354
Fingers=50.000000
Max
m22 m24
Fingers=50.000
Fingers=45.000
m12
Fingers=40.000
Fingers=35.000
Fingers=30.000
Fingers=25.000
Fingers=20.000
Fingers=15.000
m11
m25
pin=-22.700
pout=20.028
Fingers=30.000000
m23
pin= -20.700
pout=20.018
Fingers=50.000000
15
10
5
0
-50
-40
-30
-20
-10
0
Pin (dBm)
Fig. 8. Output Power with change in size of power stage transistor
m19
indep(m19)= -38.100
plot_vs(Idc, pin)=-48.456
Fingers=15.000000
m20
indep(m20)= -3.000
plot_vs(Idc, pin)=-90.129
Fingers=30.000000
m19
-40
Fingers=15.000
-60
Fingers=20.000
Idc (m )
A
-80
Fingers=25.000
m20
Fingers=30.000
-100
-120
-140
Fingers=35.000
m21
indep(m21)= -7.700
plot_vs(Idc, pin)=-143.767
Fingers=50.000000
Fingers=40.000
Fingers=45.000
m21
Fingers=50.000
-160
-50
-40
-30
-20
-10
0
10
Pin (dbm)
Fig. 9. Total DC Current with change in size of power stage transistor
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8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
m18
pin= -5.000
PAE=96.851
Fingers=15.000000
Max
100
P E(%
A
)
80
60
40
20
m14
pin= -3.900
PAE=70.196
Fingers=30.000000
Max
m13
pin= -8.200
PAE=47.803
Fingers=50.000000
Max
m18
m17
pin= -27.500
PAE=29.085
Fingers=15.000000
Fingers=15.000
Fingers=20.000
m14
Fingers=25.000
Fingers=30.000
Fingers=35.000
Fingers=40.000
Fingers=45.000
Fingers=50.000
m15
m13
pin= -22.700
m15
PAE=44.669
Fingers=30.000000 m17
m16
m16
pin= -20.700
PAE=27.938
Fingers=50.000000
0
-50
-40
-30
-20
-10
0
Pin (dBm)
Fig. 10. Power Added Efficiency with change Size of Power stage transistor
Table 2. Variation in Output Power, S- Parameters and PAE with change in size of power stage transistor
Size of Power S – Parameters (dB)
Stage Transistor
(W/L) µm
(10*F)/0.13
S(1,1)
S(2,2)
15
-6.578
-9.295
20
-8.179
-15.293
25
-9.614
-16.637
30
-11.132
-12.467
35
-11.952
-9.504
40
-12.886
-7.772
45
-13.631
-6.493
50
-14.299
-5.638
S(2,1)
43.857
44.176
43.975
43.745
43.114
42.673
42.082
41.605
S(1,2)
-61.92
-61.557
-61.496
-61.889
-62.432
-62.860
-63.344
-63.767
Total DC Output Power
Current (dBm)
(mA)
IDC
Pout1dB Poutmax
48.4
15.47
20.702
62.4
17.995 21.381
76.3
19.378 21.761
90.1
20.028 22.002
104
20.317 22.139
117
20.338 22.239
131
20.263 22.291
143.7
20.018 22.354
Power Added
Efficiency (%)
PAE1dB
29.085
40.408
45.439
44.669
41.477
36.889
32.542
27.938
PAEmax
96.851
87.913
78.449
70.196
62.93
56.982
51.863
47.803
Operating Voltage: 2.5 V
Operating Frequency: 2.4 GHz
4. LAYOUT
The layout of the designed power amplifier drawn in Tanner tool is shown in figure 11.This
layout occupies total die area of 0.363 mm2. This layout is designed to be operating at 2.5 dc
supply and the width of power stage transistor is 300 µm. The total dc current flowing through
this circuit is 90.1 mA. Metal 4 is used for VDD and ground lines and as its current flowing
density is 1.6 mA per 1 µm, 120 µm metal 4 width is used.
114

9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Fig. 11. Layout of RF CMOS Power Amplifier
5. CONCLUSIONS
CMOS power amplifiers provide high output power with high efficiency. The values of VDD
supply and size of power transistor were varied to observe the changes in output power, sparameters and power added efficiency. As shown in the results wide range of output power was
achieved with relatively high efficiency. From the results it can be concluded that this power
amplifier shows best performance with VDD 2.5 V and width of power stage transistor to be 300
µm. This wide range of output power helps this circuit in application of Bluetooth to WLAN.
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