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From Superscalar OO to Multicore SST Checkpoint and Transactional memory support for SST © dave+stratusdesign@gmail.com st...
The OO Superscalar legacy <ul><ul><li>OO legacy technique of the superscalar era does it have a future in multicore? </li>...
Speculative execution evolution <ul><ul><li>Scout (Run-ahead) thread </li></ul></ul><ul><ul><ul><li>During a data-dependen...
Evolution to SST <ul><ul><li>Speculative Execution Depends on => </li></ul></ul><ul><ul><ul><li>Checkpointing </li></ul></...
Hazards <ul><ul><li>Common to OO and SST </li></ul></ul><ul><ul><li>Data </li></ul></ul><ul><ul><ul><li>RAW, WAR, WAW </li...
OO & SST Differences <ul><ul><li>Traditional OO </li></ul></ul><ul><ul><ul><li>Stalls instructions with any data dependenc...
Data hazards <ul><ul><li>RAW a=5; a=10; b=a+1; </li></ul></ul><ul><ul><li>b should be 11 not 6 </li></ul></ul><ul><ul><li>...
SST handling of Data Hazards <ul><ul><li>Ahead thread </li></ul></ul><ul><ul><ul><li>Avoids RAW by using NT bit and deferr...
SST handling of Control Hazards <ul><ul><li>Speculation fails if any of the following occur </li></ul></ul><ul><ul><ul><li...
SST Memory Consistency Protocol <ul><ul><li>Load Order protocol  </li></ul></ul><ul><ul><ul><li>Speculative loads set the ...
Checkpoints <ul><ul><li>For N=2  </li></ul></ul><ul><ul><li>At start of an SST episode 2 checkpoints are created </li></ul...
SST new circuit structures <ul><ul><li>To Handle N Checkpoints (assume N=2) </li></ul></ul><ul><ul><ul><li>2 Defer Queues ...
SST logic Wakeup Behind Thread DQ Full? DQ Empty for current & spec ckpt? L1 Miss Set  ‘ S ’  bit  in Cache Start Behind  ...
SST scheduling Program Order LDX addr1, %r1 ADD %r1, 0x04, %r2 STX %r2, addr2 SETHI 0x01, %r2 STX %r2, addr3 etc..  ;  Ahe...
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from OO to Multicore SST

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from OO to Multicore SST. An overview of SST describing Checkpoint and Transactional Memory Support for ROCK

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from OO to Multicore SST

  1. 1. From Superscalar OO to Multicore SST Checkpoint and Transactional memory support for SST © dave+stratusdesign@gmail.com stratusdesign.squarespace.com
  2. 2. The OO Superscalar legacy <ul><ul><li>OO legacy technique of the superscalar era does it have a future in multicore? </li></ul></ul><ul><ul><li>Used to utilise otherwise wasted cycles while waiting for memory </li></ul></ul><ul><ul><li>State of the art </li></ul></ul><ul><ul><li>Ultimately limited by </li></ul></ul><ul><ul><ul><li>Parallelism found in code </li></ul></ul></ul><ul><ul><ul><li>Logic for RRF/CDB cycle latencies </li></ul></ul></ul><ul><ul><ul><li>Hazard checking burden increases quadratically with size of issue queue/reservation station due to the CAM like structure used for these queues </li></ul></ul></ul><ul><ul><ul><li>Ability to scale as memory wall increases </li></ul></ul></ul>Year Inflight Instructions Clock Speed 1998 90 600Mhz 2008 200 3200Mhz
  3. 3. Speculative execution evolution <ul><ul><li>Scout (Run-ahead) thread </li></ul></ul><ul><ul><ul><li>During a data-dependent stall (eg L1 cache miss) enter run-ahead mode continuing execution in program order </li></ul></ul></ul><ul><ul><ul><ul><li>Helps to warm caches until dependency resolved and normal execution can be resumed </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Throws away lots of instructions that could have been executed between stall and resolution of the data-dependency </li></ul></ul></ul></ul><ul><ul><li>Evolution to SST </li></ul></ul><ul><ul><ul><li>During a data-dependent stall (eg L1 cache miss) enter execute-ahead mode doing speculative execution </li></ul></ul></ul><ul><ul><ul><li>(..contd) </li></ul></ul></ul>
  4. 4. Evolution to SST <ul><ul><li>Speculative Execution Depends on => </li></ul></ul><ul><ul><ul><li>Checkpointing </li></ul></ul></ul><ul><ul><ul><li>Transactional Memory </li></ul></ul></ul><ul><ul><li>Exploits => hardware threading </li></ul></ul><ul><ul><ul><li>Ahead thread executing instructions speculatively </li></ul></ul></ul><ul><ul><ul><li>Behind thread executing instructions with resolved data dependencies </li></ul></ul></ul><ul><ul><li>Advantages => </li></ul></ul><ul><ul><ul><li>[+] Single threaded software code is being executed simultaneously from 2 different locations using hardware threads </li></ul></ul></ul><ul><ul><ul><li>[+] Achieves MLP and ILP </li></ul></ul></ul><ul><ul><ul><li>[-] Program locality works toward ensuring cache misses are kept to a minimum or the prefetcher may be able to produce the result with a very low cycle latency </li></ul></ul></ul>
  5. 5. Hazards <ul><ul><li>Common to OO and SST </li></ul></ul><ul><ul><li>Data </li></ul></ul><ul><ul><ul><li>RAW, WAR, WAW </li></ul></ul></ul><ul><ul><li>Control </li></ul></ul><ul><ul><ul><li>Branching, Exceptions </li></ul></ul></ul><ul><ul><li>Memory Consistency Protocols </li></ul></ul><ul><ul><ul><li>Scheme must not break effect of Total Store Ordering (The Von-Neuman/Turing ordering of a code). In other words the results of the dynamic machine scheduling of code must not differ with the static program schedule) </li></ul></ul></ul>
  6. 6. OO & SST Differences <ul><ul><li>Traditional OO </li></ul></ul><ul><ul><ul><li>Stalls instructions with any data dependency, that is , there is no progression to the retirement unit. </li></ul></ul></ul><ul><ul><ul><li>Uses register renaming to continue OO ‘ execute ’ </li></ul></ul></ul><ul><ul><li>SST </li></ul></ul><ul><ul><ul><li>RAW => Defers instructions and any resolved operands in a deferred queue (DQ) </li></ul></ul></ul><ul><ul><ul><li>WAR, WAW => Speculatively retired </li></ul></ul></ul>
  7. 7. Data hazards <ul><ul><li>RAW a=5; a=10; b=a+1; </li></ul></ul><ul><ul><li>b should be 11 not 6 </li></ul></ul><ul><ul><li>WAR a=5 b=a+1 a=6 </li></ul></ul><ul><ul><li>b should be 5 not 6 </li></ul></ul><ul><ul><li>WAW a=5; b=50; </li></ul></ul><ul><ul><li>b should be 50 not 5 </li></ul></ul><ul><ul><li>Executing instructions out of order is problematical as potentially N versions of operands held in finite set of registers </li></ul></ul><ul><ul><li>When does the register have the correct value for the right instruction? </li></ul></ul>
  8. 8. SST handling of Data Hazards <ul><ul><li>Ahead thread </li></ul></ul><ul><ul><ul><li>Avoids RAW by using NT bit and deferring the instruction </li></ul></ul></ul><ul><ul><li>Behind thread </li></ul></ul><ul><ul><ul><li>Avoids WAR by saving resolved operands alongside relevant instruction in the DQ </li></ul></ul></ul><ul><ul><ul><li>Avoids WAW the NT bits determines if it can update the ARF (architectural register file) if not the WAW bit is set preventing this and the SRF register update may only be used to do data forwarding </li></ul></ul></ul><ul><ul><li>Discovering and propagating data dependencies </li></ul></ul><ul><ul><ul><li>Reg [dest] = Reg [operand_1] || Reg [operand_n] </li></ul></ul></ul>
  9. 9. SST handling of Control Hazards <ul><ul><li>Speculation fails if any of the following occur </li></ul></ul><ul><ul><ul><li>Branch Mis-Prediction </li></ul></ul></ul><ul><ul><ul><li>Transactional Memory Failure </li></ul></ul></ul><ul><ul><ul><ul><li>Memory order violation detected by ‘ S ’ bit in cache </li></ul></ul></ul></ul><ul><ul><ul><li>Exception </li></ul></ul></ul><ul><ul><li>Failed speculation causes </li></ul></ul><ul><ul><ul><li>speculative checkpoint to be discarded and, </li></ul></ul></ul><ul><ul><ul><li>architectural checkpoint restored </li></ul></ul></ul>
  10. 10. SST Memory Consistency Protocol <ul><ul><li>Load Order protocol </li></ul></ul><ul><ul><ul><li>Speculative loads set the cache line “ S ” speculatively read bit (transactional memory support) </li></ul></ul></ul><ul><ul><ul><li>If cache logic evicts or invalidates a line with the ‘ S ’ bit set then ahead thread speculation has failed for this episode </li></ul></ul></ul>
  11. 11. Checkpoints <ul><ul><li>For N=2 </li></ul></ul><ul><ul><li>At start of an SST episode 2 checkpoints are created </li></ul></ul><ul><ul><ul><li>Architectural Checkpoint </li></ul></ul></ul><ul><ul><ul><ul><li>Initially active </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Once active ahead-thread progresses with speculative execution </li></ul></ul></ul></ul><ul><ul><ul><li>Speculative Checkpoint (inactive) </li></ul></ul></ul><ul><ul><ul><ul><li>Behind thread wakes then makes it active ; clears W bit vector </li></ul></ul></ul></ul><ul><ul><ul><ul><li>NT bit vector copied to SNT bit vector to detect WAW hazards </li></ul></ul></ul></ul><ul><ul><ul><li>When deferred queue empty for speculative episode a “ merge ” operation is performed </li></ul></ul></ul><ul><ul><ul><ul><li>Merge is Ahead-thread results + Behind-thread results => Architectural Checkpoint </li></ul></ul></ul></ul><ul><ul><ul><ul><li>NT = SNT && W ; SNT and W bit vectors cleared ; Architectural Checkpoint is discarded ; Speculative Checkpoint is made active aka it becomes the new Architectural Checkpoint </li></ul></ul></ul></ul><ul><ul><ul><li>When deferred queue empty for all speculative episodes a “ join ” operation is performed </li></ul></ul></ul><ul><ul><ul><ul><li>Join similar to Merge except nothing remains in the Deferred Queue and the speculative episode is ended returning the Ahead-thread to Normal mode </li></ul></ul></ul></ul>
  12. 12. SST new circuit structures <ul><ul><li>To Handle N Checkpoints (assume N=2) </li></ul></ul><ul><ul><ul><li>2 Defer Queues </li></ul></ul></ul><ul><ul><ul><ul><li>Hold instructions & resolved operands used by behind thread </li></ul></ul></ul></ul><ul><ul><ul><li>1 Architectural register file (aka Normal RF) </li></ul></ul></ul><ul><ul><ul><ul><li>Initially read by Ahead-thread </li></ul></ul></ul></ul><ul><ul><ul><li>2 Working register files (aka speculative RF) </li></ul></ul></ul><ul><ul><ul><ul><li>Ahead-thread initially reads ARF updates SRF1 until, </li></ul></ul></ul></ul><ul><ul><ul><ul><li>speculative checkpoint when it updates SRF2 the behind-thread wakes and uses SRF1 </li></ul></ul></ul></ul><ul><ul><ul><li>Status bits NT, SNT, W, WAW </li></ul></ul></ul><ul><ul><ul><ul><li>Not There, Speculatively Not There, Written, WAW </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Behind thread uses W bit like Ahead thread uses NT bit </li></ul></ul></ul></ul><ul><ul><ul><ul><li>SNT bit is used to capture register state of Ahead thread when Behind thread initiates </li></ul></ul></ul></ul><ul><ul><ul><ul><li>NT =/= SNT => WAW when checked during SST episode </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Any Register with WAW set value gets dropped at end of SST episode </li></ul></ul></ul></ul><ul><ul><ul><li>S bit in Cache line </li></ul></ul></ul><ul><ul><ul><ul><li>Cache Slot is waiting for a ‘ S ’ peculative Load </li></ul></ul></ul></ul>
  13. 13. SST logic Wakeup Behind Thread DQ Full? DQ Empty for current & spec ckpt? L1 Miss Set ‘ S ’ bit in Cache Start Behind thread in wait mode to handle Defers Start Executing Main thread Speculatively ahead Behind Thread Runs Thru DQ for Active Checkpoint Done Ahead Thread • Normal Mode Behind Thread • Pause L1 Resolved Ahead Thread • Scout Mode Behind Thread • Pause High Level SW initiates a Memory Transaction Restore Checkpoint Tx Fail ‘ S ’ bit Detect Mem Order Violation Br Mispredict Exception WAIT Begin SST Episode Arch Checkpoint Active • Architectural Inactive • Speculative Instr has Data Dependencies? Execute Instr and Retire OO Enqueue DQ with Instr & All Resolved Opr Instr has no Data Dependencies? WAIT more data expected Speculation Successful Program Execution resumes were speculation finished
  14. 14. SST scheduling Program Order LDX addr1, %r1 ADD %r1, 0x04, %r2 STX %r2, addr2 SETHI 0x01, %r2 STX %r2, addr3 etc.. ; Ahead-Thread 1 LDX addr1, %r1 ; Load Miss on addr1, Defer and set R1 [ NT ]) To Defer Q ; Checkpoint Start Ahead-Thread, Behind-Thread Waits for data read 2 ADD %r1, 0x04, %r2 ; Source Operand has NT bit set Defer and set R2 [NT] To Defer Q 3 STX %r2, addr2 ; Source Operand has NT bit set Defer) To Defer Q 4 SETHI 0x01, %r2 ; Ahead Thread Executes Independently) 5 STX %r2, addr3 ; Ahead Thread Executes Independently & continues speculative execution of more program instructions ; Load Miss resolves start Behind-Thread 6 ADD %r1, 0x04, %r2 [NT=0,SNT=1] ; NT was reset at 4, set waw bit 7 STX %r2, addr3 SST Order LDX addr1, %r1 ADD %r1, 0x04, %r2 STX %r2, addr2 SETHI 0x01, %r2 STX %r2, addr3 etc.. Deferring data-dependent instructions prevents RAW – here %r2 was read at 3 but written before at 2 Saving operands in DQ prevents WAR as any valid data in register at that time is captured and saved for Behind-Thread to use later regardless of future writes by Ahead-Thread Registers with WAW bit not committed to Architectural state – here %r2 was written at 4 & 6 ;Deferred Queue LDX addr1, %r1 [ NT ] ADD %r1 [ NT ], 0x04, %r2 [ NT ] STX %r2 [ NT ] , addr2 WAW WAR RAW

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