This document outlines the course objectives and topics for several electronics engineering courses, including CMOS VLSI Design, VLSI Systems and Architecture, Embedded System Design, Linear Algebra, and VLSI Technology. The CMOS VLSI Design course covers MOS transistor theory, CMOS process technology, digital and analog CMOS design. The VLSI Systems and Architecture course covers dedicated and programmable architectures, CISC, RISC, and DSP architectures. The Embedded System Design course covers embedded processors and memory, device networks, embedded programming, and real-time systems. Linear Algebra covers linear equations, vector spaces, linear transformations, and inner product spaces. The VLSI Technology elective covers clean rooms, impurity incorporation
This document outlines a course on semiconductor device modeling. The course aims to help students understand the operation of semiconductor devices and verify BJT modeling and simulation techniques. It covers topics like electrons and holes in silicon, p-n junctions, MOS capacitors, MOSFET devices, BJT modeling, temperature effects, advanced bipolar models, threshold voltage modeling, and noise modeling. Students will learn analytical and numerical modeling of BJT and MOS transistors. Upon completing the course, students should have a clear understanding of utilizing MOS and semiconductor microwave devices and be able to design advanced electronic devices.
This document contains the course scheme and syllabus details for the 8th semester of Electronics and Communication Engineering at University Visvesvaraya College of Engineering. It outlines 7 subjects to be covered in the semester, along with the course code, number of hours per week, internal and external assessment marks allocation for theory and practical components. For each subject, the document provides the detailed syllabus to be covered, divided into parts and topics, along with reference books. Laboratory experiments and protocols to be covered for the Embedded Systems Lab subject are also listed.
EC(UVCE) 8th sem syllabus copy form lohith kumar 11guee6018UVCE
This document contains the course scheme and syllabus details for the 8th semester of Electronics and Communication Engineering at University Visvesvaraya College of Engineering. It outlines 7 subjects to be covered in the semester, along with the course code, number of hours per week, internal and external marks allocation for theory and practical components. For each subject, the document provides the detailed syllabus to be covered, divided into parts and topics, along with reference books. Laboratory experiments and protocols to be covered for the Embedded Systems Lab subject are also listed.
This document outlines the course structure and content for several Masters of Technology courses in Electronics and VLSI design. It includes 5 units for each course, along with the relevant textbooks. Some of the key courses covered include VLSI Subsystem Design, Embedded Systems & Controllers, Advanced Digital Signal Processing, Physics of Materials, Real-Time Operating Systems, MEMS, Solid State Devices, Switching Theory & Automata, and Reconfigurable Computing.
This document contains the course details for Semester I and Semester II of an electronics engineering program. Semester I includes courses on graph theory, digital design principles, device modeling, digital IC design, and designing with FPGAs. Semester II includes courses on low power VLSI design, analog VLSI circuits, testing and testability. Each course lists the topics to be covered, number of lecture hours, references, and course outcomes. Laboratory courses are also included to provide hands-on learning experiences.
Gang Fang (3481652) PhD Student (advisor: Dr. Vipin Kumar).docbutest
This document contains Gang Fang's petition for course transfers and substitutions from his MS degree at SUNY-Buffalo to his PhD program at the University of Minnesota. It lists the courses he took at SUNY-Buffalo, including Pattern Recognition, Algorithms Analysis and Design, and Introduction to Operating Systems, and petitions for them to fulfill various requirements. It also lists two courses taken at UMN, and petitions for them to fulfill breadth requirements.
This document outlines the teaching scheme and units for the course "Digital Signal Processing". The course is divided into 6 units that cover key topics in digital signal processing including characterization of linear time-invariant discrete-time systems, Fourier analysis of discrete-time systems, analysis using the z-transform, digital filter design, multirate sampling, and digital signal processing hardware platforms. Students will learn both theoretical concepts and practical applications through lectures, assignments, and laboratory experiments using software tools.
The Phase Field Methods Workshop was held at Northwestern University on January 9, 2015. The workshop brought together researchers from national laboratories, universities, and industry to discuss phase field modeling tools and methods. The agenda included sessions on current phase field codes and capabilities, large-scale computing approaches, potential focus areas for research, and how to structure a community code. Attendees discussed formulating standard benchmark problems and organizing a community repository to enable further collaboration on phase field modeling code development.
This document outlines a course on semiconductor device modeling. The course aims to help students understand the operation of semiconductor devices and verify BJT modeling and simulation techniques. It covers topics like electrons and holes in silicon, p-n junctions, MOS capacitors, MOSFET devices, BJT modeling, temperature effects, advanced bipolar models, threshold voltage modeling, and noise modeling. Students will learn analytical and numerical modeling of BJT and MOS transistors. Upon completing the course, students should have a clear understanding of utilizing MOS and semiconductor microwave devices and be able to design advanced electronic devices.
This document contains the course scheme and syllabus details for the 8th semester of Electronics and Communication Engineering at University Visvesvaraya College of Engineering. It outlines 7 subjects to be covered in the semester, along with the course code, number of hours per week, internal and external assessment marks allocation for theory and practical components. For each subject, the document provides the detailed syllabus to be covered, divided into parts and topics, along with reference books. Laboratory experiments and protocols to be covered for the Embedded Systems Lab subject are also listed.
EC(UVCE) 8th sem syllabus copy form lohith kumar 11guee6018UVCE
This document contains the course scheme and syllabus details for the 8th semester of Electronics and Communication Engineering at University Visvesvaraya College of Engineering. It outlines 7 subjects to be covered in the semester, along with the course code, number of hours per week, internal and external marks allocation for theory and practical components. For each subject, the document provides the detailed syllabus to be covered, divided into parts and topics, along with reference books. Laboratory experiments and protocols to be covered for the Embedded Systems Lab subject are also listed.
This document outlines the course structure and content for several Masters of Technology courses in Electronics and VLSI design. It includes 5 units for each course, along with the relevant textbooks. Some of the key courses covered include VLSI Subsystem Design, Embedded Systems & Controllers, Advanced Digital Signal Processing, Physics of Materials, Real-Time Operating Systems, MEMS, Solid State Devices, Switching Theory & Automata, and Reconfigurable Computing.
This document contains the course details for Semester I and Semester II of an electronics engineering program. Semester I includes courses on graph theory, digital design principles, device modeling, digital IC design, and designing with FPGAs. Semester II includes courses on low power VLSI design, analog VLSI circuits, testing and testability. Each course lists the topics to be covered, number of lecture hours, references, and course outcomes. Laboratory courses are also included to provide hands-on learning experiences.
Gang Fang (3481652) PhD Student (advisor: Dr. Vipin Kumar).docbutest
This document contains Gang Fang's petition for course transfers and substitutions from his MS degree at SUNY-Buffalo to his PhD program at the University of Minnesota. It lists the courses he took at SUNY-Buffalo, including Pattern Recognition, Algorithms Analysis and Design, and Introduction to Operating Systems, and petitions for them to fulfill various requirements. It also lists two courses taken at UMN, and petitions for them to fulfill breadth requirements.
This document outlines the teaching scheme and units for the course "Digital Signal Processing". The course is divided into 6 units that cover key topics in digital signal processing including characterization of linear time-invariant discrete-time systems, Fourier analysis of discrete-time systems, analysis using the z-transform, digital filter design, multirate sampling, and digital signal processing hardware platforms. Students will learn both theoretical concepts and practical applications through lectures, assignments, and laboratory experiments using software tools.
The Phase Field Methods Workshop was held at Northwestern University on January 9, 2015. The workshop brought together researchers from national laboratories, universities, and industry to discuss phase field modeling tools and methods. The agenda included sessions on current phase field codes and capabilities, large-scale computing approaches, potential focus areas for research, and how to structure a community code. Attendees discussed formulating standard benchmark problems and organizing a community repository to enable further collaboration on phase field modeling code development.
This document provides course information for the M.E. VLSI Design program at Anna University in Chennai, India. It outlines the curriculum, courses, credits, and syllabus for semesters I through IV. Semester I includes courses in applied mathematics, VLSI signal processing, VLSI design techniques, solid state device modeling and simulation, and electives. Semester II continues with additional core and elective courses. Semesters III and IV involve project work to complete the 68 total credits required for the degree. Elective courses cover topics in analog and digital circuits, computer architecture, FPGA design, and more.
This document outlines the course details for the subject "Fundamentals of CMOS VLSI". The course is divided into 8 units that cover topics such as basic MOS transistor theory, CMOS logic structures, circuit design processes, memory elements, and testability. The course includes 52 total lecture hours over 8 units. Students will be assessed through exams worth 125 total marks. Two textbooks are listed as required reading along with 3 additional reference books.
This document outlines the course details for the subject "Fundamentals of CMOS VLSI". The course is divided into 8 units that cover topics such as basic MOS transistor theory, CMOS logic structures, circuit design processes, memory elements, and testability. The course includes both lecture and exam hours totaling 52 hours over 8 units. Students will be graded based on in-semester assessments worth 25 marks and an end-semester exam worth 100 marks. Suggested textbooks and references are also provided.
This course covers computer networks and networking concepts. It discusses 3 main topics: networking techniques and the internet, networking protocol layers and models, and specific protocols like TCP, IP, and DNS. The goal is to introduce fundamental computer networking concepts and the layered networking model. Students will learn about networking principles, protocols, and applications through lectures and hands-on labs.
This document provides information on a course titled "Computer Networks". The course is 3 credit hours and includes both theory and lab components. It introduces concepts of computer networking and discusses the different layers of the networking model. The course content covers topics such as types of networking techniques, the Internet, IP addressing, routing, transport layer protocols, and local area networks. The goal is to provide students an understanding of computer networking fundamentals.
This document outlines the course units and topics for CS9221 Database Technology. It covers 5 units: Distributed Databases, Object Oriented Databases, Emerging Systems, Database Design Issues, and Current Issues. Some key topics included are distributed and conventional database architectures, query processing, transaction processing, concurrency control, recovery, object oriented data modeling and design, and temporal, spatial, multimedia, and text databases. The document also lists 8 references for the course.
This document outlines the details of a VLSI Technology course offered at Indian Institute of Technology Roorkee. The course provides knowledge of various semiconductor fabrication processes and techniques. Over 10 weeks, it covers topics like crystal growth, epitaxial growth, oxidation, etching, lithography, diffusion, ion implantation, metallization, VLSI process integration, assembly techniques, packaging, yield and reliability. The course aims to give students an understanding of the fundamental science and engineering principles underlying VLSI fabrication.
This document provides information about the Semester VII curriculum including course details, teaching schemes, and examination schemes. Key points:
- The semester includes courses like Compiler Construction and Design, Computer Forensics and Cyber Laws, Software Testing, and an elective.
- Courses involve lectures, tutorials, and practical sessions. Examinations include internal assessments, unit tests, term work assignments, and end semester exams.
- Detailed course objectives, prerequisites, outcomes are provided for Compiler Construction and Design along with unit-wise syllabus and assignment lists.
- Similarly, course details like objectives, prerequisites, outcomes are given for Computer Forensics and Cyber Laws along with its unit-wise syllabus
B.Tech 2nd Year CSE & CSIT AICTE Model Curriculum 2019-20.pdfAnita Pal
This document outlines the evaluation scheme, syllabus, and course details for the second year of the B.Tech Computer Science and Engineering program at DR. A.P.J. Abdul Kalam Technical University in Lucknow, India. It includes information on subjects, credit hours, evaluation criteria, and course codes for semesters 3 and 4. Semester 3 covers subjects like Data Structures, Computer Organization and Architecture, Discrete Structures and Logic, along with their corresponding labs. Semester 4 covers subjects like Operating Systems, Theory of Automata, Microprocessors, along with their labs. For each subject, the document provides the course outcomes, topics to be covered, textbooks, and other details.
UVCE ELECTRONICS AND COMMUNICATION 7th SEM SYLLABUS BY LOHITH KUMAR R 11GUEE...UVCE
This document contains information about the 7th semester courses for Electronics and Communication Engineering at University Visvesvaraya College of Engineering. It lists the courses offered, number of hours per week, internal and external assessment details. It provides the syllabus breakdown and reference materials for some of the courses including Wireless Communication, Multimedia Systems, Computer Communication Networks, Satellite Communication and Remote Sensing, Digital Communication Lab, and Simulation and HDL Lab.
This document provides an overview of an introductory software engineering course. It discusses the goals of introducing formal processes, individual and team development, and life-cycle issues. Key topics that will be introduced include requirements engineering, software modeling, and assurance. The course aims to facilitate problem understanding and communication skills. It also provides a historical perspective on software engineering and discusses the software engineering life-cycle which includes definition, development, maintenance, and umbrella activities.
This document provides information about a book titled "Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices". The book is a collection of recent works from leading research groups working on dedicated hybrid (CMOS + nanodevice) hardware for neuromorphic computing. It contains chapters on implementing artificial neurons and synapses using emerging nanoscale devices. The chapters cover topics like hardware spiking neurons, synaptic plasticity with memristive devices, neuromemristive circuit design, memristor-based neural networks, and exploiting resistive memory variability for cognitive systems. The book aims to advance the field of neuromorphic computing through efficient hybrid CMOS-nanodevice architectures.
The document contains information about various courses offered at Kakatiya University for B.Sc Computer Science students in their final year, 5th semester.
It includes details of 5 courses - Programming in Java, Public Health and Hygiene (generic elective), Verbal Reasoning for Aptitude Test (skill enhancement), Computer Networks (elective 1) and Python (elective 1). For each course, it lists the course credits, units of study, textbooks and references. It also provides the syllabus and lab programs for the Programming in Java and Computer Networks courses.
A Guide to Wireless Communication, Addison Wesley, 1995.
3. J.F.Kurose and K.W.Ross: Computer Networking: A Top Down Approach Featuring
the Internet, Addison Wesley, 2002.
4. C.Siva Ram Murthy and B.S.Manoj: Adhoc Wireless Networks: Architectures and
Protocols, Prentice Hall, 2004.
5. William Stallings: Wireless Communications and Networks, Prentice Hall, 2002.
Image Processing
Introduction to Digital Image Processing, Image acquisition and digitization, Image
enhancement, Image restoration, Image compression, Image segmentation, Image
representation and description, Object recognition
EC(UVCE) 7th sem syllabus copy form lohith kumar 11guee6018UVCE
This document contains the scheme of study and examination for the 7th semester of the B.E. (EC) program under the 2k6 scheme at University Visvesvaraya College of Engineering.
It lists the various subjects to be covered in the 7th semester, including Wireless Communication, Multimedia Systems, Computer Communication Networks, an elective subject, and several labs.
For each subject, it provides details such as the number of hours per week, internal and external marks allotted, topics to be covered, and references. It also includes the syllabus for some of the subjects, outlining the topics and their allocation of lecture hours.
The document provides a comprehensive overview of the curriculum, assessment
This document outlines the course structure and content for a Data Science course. The 5 modules cover: 1) introductions to data science concepts and statistical inference using R; 2) exploratory data analysis and machine learning algorithms; 3) feature generation/selection and additional machine learning algorithms; 4) recommendation systems and dimensionality reduction; 5) mining social network graphs and data visualization. The course aims to teach students to define data science fundamentals, demonstrate the data science process, explain necessary machine learning algorithms, illustrate data analysis techniques, and follow ethics in data visualization.
This course teaches technical writing skills needed for a career in technology. It covers writing processes, styles, and formats for various technical documents. Key topics include organizing information, writing for different audiences, using graphics and visual elements, writing instructions, descriptions, reports, and other common technical document types. Students learn grammar and mechanics rules specific to technical writing. The goal is for students to gain proficiency in written communication skills required in technical fields.
The document provides the syllabus for the 3rd year 1st semester courses for the Computer Science and Engineering department at Jawaharlal Nehru Technological University Kakinada, including courses on Data Warehousing and Data Mining, Computer Networks, Compiler Design, Artificial Intelligence, and Professional Electives, along with information on class schedules, course objectives, and reading materials.
The document provides details of the revised syllabus for 7th and 8th semesters of the B.E. Computer Science & Engineering program at Shivaji University, Kolhapur.
It lists the subjects to be taught in each semester along with their course codes, number of lecture hours, tutorials, practical sessions and marks distribution. Elective subjects are also specified for semesters 7 and 8. Guidelines for term work, project work, assignments and assessments are outlined. The syllabus for individual subjects like Advanced Computer Architecture, Distributed Systems and Advanced Database Systems are briefly described in terms of topics to be covered.
This document provides course information for the M.E. VLSI Design program at Anna University in Chennai, India. It outlines the curriculum, courses, credits, and syllabus for semesters I through IV. Semester I includes courses in applied mathematics, VLSI signal processing, VLSI design techniques, solid state device modeling and simulation, and electives. Semester II continues with additional core and elective courses. Semesters III and IV involve project work to complete the 68 total credits required for the degree. Elective courses cover topics in analog and digital circuits, computer architecture, FPGA design, and more.
This document outlines the course details for the subject "Fundamentals of CMOS VLSI". The course is divided into 8 units that cover topics such as basic MOS transistor theory, CMOS logic structures, circuit design processes, memory elements, and testability. The course includes 52 total lecture hours over 8 units. Students will be assessed through exams worth 125 total marks. Two textbooks are listed as required reading along with 3 additional reference books.
This document outlines the course details for the subject "Fundamentals of CMOS VLSI". The course is divided into 8 units that cover topics such as basic MOS transistor theory, CMOS logic structures, circuit design processes, memory elements, and testability. The course includes both lecture and exam hours totaling 52 hours over 8 units. Students will be graded based on in-semester assessments worth 25 marks and an end-semester exam worth 100 marks. Suggested textbooks and references are also provided.
This course covers computer networks and networking concepts. It discusses 3 main topics: networking techniques and the internet, networking protocol layers and models, and specific protocols like TCP, IP, and DNS. The goal is to introduce fundamental computer networking concepts and the layered networking model. Students will learn about networking principles, protocols, and applications through lectures and hands-on labs.
This document provides information on a course titled "Computer Networks". The course is 3 credit hours and includes both theory and lab components. It introduces concepts of computer networking and discusses the different layers of the networking model. The course content covers topics such as types of networking techniques, the Internet, IP addressing, routing, transport layer protocols, and local area networks. The goal is to provide students an understanding of computer networking fundamentals.
This document outlines the course units and topics for CS9221 Database Technology. It covers 5 units: Distributed Databases, Object Oriented Databases, Emerging Systems, Database Design Issues, and Current Issues. Some key topics included are distributed and conventional database architectures, query processing, transaction processing, concurrency control, recovery, object oriented data modeling and design, and temporal, spatial, multimedia, and text databases. The document also lists 8 references for the course.
This document outlines the details of a VLSI Technology course offered at Indian Institute of Technology Roorkee. The course provides knowledge of various semiconductor fabrication processes and techniques. Over 10 weeks, it covers topics like crystal growth, epitaxial growth, oxidation, etching, lithography, diffusion, ion implantation, metallization, VLSI process integration, assembly techniques, packaging, yield and reliability. The course aims to give students an understanding of the fundamental science and engineering principles underlying VLSI fabrication.
This document provides information about the Semester VII curriculum including course details, teaching schemes, and examination schemes. Key points:
- The semester includes courses like Compiler Construction and Design, Computer Forensics and Cyber Laws, Software Testing, and an elective.
- Courses involve lectures, tutorials, and practical sessions. Examinations include internal assessments, unit tests, term work assignments, and end semester exams.
- Detailed course objectives, prerequisites, outcomes are provided for Compiler Construction and Design along with unit-wise syllabus and assignment lists.
- Similarly, course details like objectives, prerequisites, outcomes are given for Computer Forensics and Cyber Laws along with its unit-wise syllabus
B.Tech 2nd Year CSE & CSIT AICTE Model Curriculum 2019-20.pdfAnita Pal
This document outlines the evaluation scheme, syllabus, and course details for the second year of the B.Tech Computer Science and Engineering program at DR. A.P.J. Abdul Kalam Technical University in Lucknow, India. It includes information on subjects, credit hours, evaluation criteria, and course codes for semesters 3 and 4. Semester 3 covers subjects like Data Structures, Computer Organization and Architecture, Discrete Structures and Logic, along with their corresponding labs. Semester 4 covers subjects like Operating Systems, Theory of Automata, Microprocessors, along with their labs. For each subject, the document provides the course outcomes, topics to be covered, textbooks, and other details.
UVCE ELECTRONICS AND COMMUNICATION 7th SEM SYLLABUS BY LOHITH KUMAR R 11GUEE...UVCE
This document contains information about the 7th semester courses for Electronics and Communication Engineering at University Visvesvaraya College of Engineering. It lists the courses offered, number of hours per week, internal and external assessment details. It provides the syllabus breakdown and reference materials for some of the courses including Wireless Communication, Multimedia Systems, Computer Communication Networks, Satellite Communication and Remote Sensing, Digital Communication Lab, and Simulation and HDL Lab.
This document provides an overview of an introductory software engineering course. It discusses the goals of introducing formal processes, individual and team development, and life-cycle issues. Key topics that will be introduced include requirements engineering, software modeling, and assurance. The course aims to facilitate problem understanding and communication skills. It also provides a historical perspective on software engineering and discusses the software engineering life-cycle which includes definition, development, maintenance, and umbrella activities.
This document provides information about a book titled "Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices". The book is a collection of recent works from leading research groups working on dedicated hybrid (CMOS + nanodevice) hardware for neuromorphic computing. It contains chapters on implementing artificial neurons and synapses using emerging nanoscale devices. The chapters cover topics like hardware spiking neurons, synaptic plasticity with memristive devices, neuromemristive circuit design, memristor-based neural networks, and exploiting resistive memory variability for cognitive systems. The book aims to advance the field of neuromorphic computing through efficient hybrid CMOS-nanodevice architectures.
The document contains information about various courses offered at Kakatiya University for B.Sc Computer Science students in their final year, 5th semester.
It includes details of 5 courses - Programming in Java, Public Health and Hygiene (generic elective), Verbal Reasoning for Aptitude Test (skill enhancement), Computer Networks (elective 1) and Python (elective 1). For each course, it lists the course credits, units of study, textbooks and references. It also provides the syllabus and lab programs for the Programming in Java and Computer Networks courses.
A Guide to Wireless Communication, Addison Wesley, 1995.
3. J.F.Kurose and K.W.Ross: Computer Networking: A Top Down Approach Featuring
the Internet, Addison Wesley, 2002.
4. C.Siva Ram Murthy and B.S.Manoj: Adhoc Wireless Networks: Architectures and
Protocols, Prentice Hall, 2004.
5. William Stallings: Wireless Communications and Networks, Prentice Hall, 2002.
Image Processing
Introduction to Digital Image Processing, Image acquisition and digitization, Image
enhancement, Image restoration, Image compression, Image segmentation, Image
representation and description, Object recognition
EC(UVCE) 7th sem syllabus copy form lohith kumar 11guee6018UVCE
This document contains the scheme of study and examination for the 7th semester of the B.E. (EC) program under the 2k6 scheme at University Visvesvaraya College of Engineering.
It lists the various subjects to be covered in the 7th semester, including Wireless Communication, Multimedia Systems, Computer Communication Networks, an elective subject, and several labs.
For each subject, it provides details such as the number of hours per week, internal and external marks allotted, topics to be covered, and references. It also includes the syllabus for some of the subjects, outlining the topics and their allocation of lecture hours.
The document provides a comprehensive overview of the curriculum, assessment
This document outlines the course structure and content for a Data Science course. The 5 modules cover: 1) introductions to data science concepts and statistical inference using R; 2) exploratory data analysis and machine learning algorithms; 3) feature generation/selection and additional machine learning algorithms; 4) recommendation systems and dimensionality reduction; 5) mining social network graphs and data visualization. The course aims to teach students to define data science fundamentals, demonstrate the data science process, explain necessary machine learning algorithms, illustrate data analysis techniques, and follow ethics in data visualization.
This course teaches technical writing skills needed for a career in technology. It covers writing processes, styles, and formats for various technical documents. Key topics include organizing information, writing for different audiences, using graphics and visual elements, writing instructions, descriptions, reports, and other common technical document types. Students learn grammar and mechanics rules specific to technical writing. The goal is for students to gain proficiency in written communication skills required in technical fields.
The document provides the syllabus for the 3rd year 1st semester courses for the Computer Science and Engineering department at Jawaharlal Nehru Technological University Kakinada, including courses on Data Warehousing and Data Mining, Computer Networks, Compiler Design, Artificial Intelligence, and Professional Electives, along with information on class schedules, course objectives, and reading materials.
The document provides details of the revised syllabus for 7th and 8th semesters of the B.E. Computer Science & Engineering program at Shivaji University, Kolhapur.
It lists the subjects to be taught in each semester along with their course codes, number of lecture hours, tutorials, practical sessions and marks distribution. Elective subjects are also specified for semesters 7 and 8. Guidelines for term work, project work, assignments and assessments are outlined. The syllabus for individual subjects like Advanced Computer Architecture, Distributed Systems and Advanced Database Systems are briefly described in terms of topics to be covered.
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
simplified modulation technique paves the way for more straightforward and
efficient control of multilevel inverters, enabling their widespread adoption and
integration into modern power electronic systems. Through the amalgamation of
sinusoidal pulse width modulation (SPWM) with a high-frequency square wave
pulse, this controlling technique attains energy equilibrium across the coupling
capacitor. The modulation scheme incorporates a simplified switching pattern
and a decreased count of voltage references, thereby simplifying the control
algorithm.
Design and optimization of ion propulsion dronebjmsejournal
Electric propulsion technology is widely used in many kinds of vehicles in recent years, and aircrafts are no exception. Technically, UAVs are electrically propelled but tend to produce a significant amount of noise and vibrations. Ion propulsion technology for drones is a potential solution to this problem. Ion propulsion technology is proven to be feasible in the earth’s atmosphere. The study presented in this article shows the design of EHD thrusters and power supply for ion propulsion drones along with performance optimization of high-voltage power supply for endurance in earth’s atmosphere.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Software Engineering and Project Management - Introduction, Modeling Concepts...Prakhyath Rai
Introduction, Modeling Concepts and Class Modeling: What is Object orientation? What is OO development? OO Themes; Evidence for usefulness of OO development; OO modeling history. Modeling
as Design technique: Modeling, abstraction, The Three models. Class Modeling: Object and Class Concept, Link and associations concepts, Generalization and Inheritance, A sample class model, Navigation of class models, and UML diagrams
Building the Analysis Models: Requirement Analysis, Analysis Model Approaches, Data modeling Concepts, Object Oriented Analysis, Scenario-Based Modeling, Flow-Oriented Modeling, class Based Modeling, Creating a Behavioral Model.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
1. 5
I – SEMESTER
CMOS VLSI DESIGN
Subject Code : 08EC021 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage
equation, body effect, MOS device design equation, sub threshold region,
Channel length modulation. mobility variation, Tunneling, punch through,
hot electron effect MOS models, small signal AC Characteristics, CMOS
inverter, βn / βp ratio, noise margin, static load MOS inverters, differential
inverter, transmission gate, tristate inverter, BiCMOS inverter.
CMOS Process Technology: Lambda Based Design rules, scaling factor,
semiconductor Technology overview, basic CMOS technology, p well / n
well / twin well process. Current CMOS enhancement (oxide isolation, LDD.
refractory gate, multilayer inter connect) , Circuit elements, resistor ,
capacitor, interconnects, sheet resistance & standard unit capacitance
concepts delay unit time, inverter delays , driving capacitive loads, propagate
delays, MOS mask layer, stick diagram, design rules and layout, symbolic
diagram, mask feints, scaling of MOS circuits.
Basics of Digital CMOS Design: Combinational MOS Logic circuits-
Introduction, CMOS logic circuits with a MOS load, CMOS logic circuits,
complex logic circuits, Transmission Gate. Sequential MOS logic Circuits -
Introduction, Behavior of hi stable elements, SR latch Circuit, clocked latch
and Flip Flop Circuits, CMOS D latch and triggered Flip Flop. Dynamic
Logic Circuits - Introduction, principles of pass transistor circuits, Voltage
boot strapping synchronous dynamic circuits techniques, Dynamic CMOS
circuit techniques
CMOS Analog Design: Introduction, Single Amplifier. Differential
Amplifier, Current mirrors, Band gap references, basis of cross operational
amplifier.
Dynamic CMOS and clocking: Introduction, advantages of CMOS over
NMOS, CMOSSOS technology, CMOSbulk technology, latch up in bulk
CMOS., static CMOS design, Domino CMOS structure and design, Charge
sharing, Clocking- clock generation, clock distribution, clocked storage
elements.
6
REFERENCE BOOKS:
1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design:
A System Perspective,” 2nd edition, Pearson Education (Asia) Pte.
Ltd., 2000.
2. Wayne, Wolf, “Modern VLSI design: System on Silicon”
Pearson Education”, Second Edition
3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design”
PHI 3rd
Edition (original Edition – 1994)
4. Sung Mo Kang & Yosuf Lederabic Law, “CMOS Digital
Integrated Circuits: Analysis and Design”, McGraw-Hill (Third
Edition)
VLSI SYSTEM AND ARCHITECTURE
Subject Code : 08EC082 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Behavior and Architecture: Dedicated and Programmable VLSI
architectures, Instruction sets and through enhancement techniques
(Parallelism. pipelining. cache, etc.)
CISC Architecture Concepts: Typical CISC instruction set and its VLSI
implementation, RT-level optimization through hardware flow charting,
Design of the execution unit, Design of the control part (micro programmed
and hardwired), handling exceptions: Instruction boundary interrupts,
immediate interrupts and traps.
RISC Architecture Concepts: Typical RISC instruction set and its VLSI
implementation, Execution pipeline, Benefits and problems of pipelined
execution, Hazards of various types of pipeline stalling, concepts of
scheduling (Static and dynamic) and forwarding to reduce / minimize
pipeline stalls Exceptions in pipelined processors
2. 7
DSP Architecture Concepts: Typical DSP instruction set and its VLSI
implementation
Dedicated Hardware Architecture Concepts: Example and Case studies.
Dedicated DSP architecture Concepts: Synthesis, Scheduling and Resource
allocation, Conventional Residue number, distributed arithmetic architecture
REFERENCE BOOKS:
1. D A Patterson and I L Hennessy, “Computer Architecture: A
Quantitative approach”, Second edition, Margon Kaufmann, 1996
2. Lars Wanhammar, “DSP Integrated Circuits”, Academic
Press 1999.
3. D A Patterson and J L Hennessy, “Computer organization and
Design: Hardware/Software interface” Second Edition, Margan
Kaufmann, 1998
4. Avtar Sing and Srinivas S, “DSP: Architecture,
Programming and Applications”, Thomson Learning, 2004.
5. B. Venkataramani and M. Baskar, “DSP: Architecture,
Programming and Applications”, TMH, 2002.
EMBEDDED SYSTEM DESIGN
Subject Code : 08EC037 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction to Embedded System: An embedded system, processor,
hardware unit, soft ware embedded into a system, Example of an embedded
system, OS services, I/O, N/W, O/S, Real time and embedded OS.
8
Processor and Memory Organization: Structural unit in as processor,
processor selection for an embedded systems. Memory devices, memory
selection for an embedded system, allocation of memory to program
statements and blocks and memory map of a system. Direct memory
accesses.
Devices And Buses for Device Networks: I/O devices, serial
communication using FC, CAN devices, device drivers, parallel port device
driver in a system, serial port device driver in a system, device driver for
internal programmable timing devices, interrupt servicing mechanism, V
context and periods for switching networked I/O devices using ISA, PCI
deadline and interrupt latency and advanced buses.
Programming Concepts and Embedded Programming in C: Microchip
PlC microcontroller/Motorola MC68HC1I: Introduction, CPU architecture
registers instruction sets, addressing modes, timers. Interrupts, ITC bus
operation, serial EEPROM, ADC, UART, serial programming /parallel slave
port
Program Modeling Concepts In Single and Multiprocessor Systems:
software development process, modeling process for software analysis before
software implementation, programming model for the event controlled or
response time constrained real time programs, modeling of multiprocessor
system.
Intel-Process Communication and Synchronization of Processors Tasks:
and threads; multiple process in an application, problems of sharing data by
multiple tasks and routines, inter process communications. RTOS task
scheduling models interrupt literacy and response times, performance metric
in scheduling models, standardization of RTOS, list of basic functions,
fifteen point strategy for synchronization.
REFERENCE BOOKS:
1. Raj Kamal, “Embedded systems Architecture, Programming and
Design”, TMH.
2. J. W. Valvano, “Embedded Microcomputer system – Real time
Interfacing”, Thomson Learning Publishing
3. Jane W. S., Liu, “Real Time Systems”, Pearson Education Asia Pub
3. 9
LINEAR ALGEBRA
Subject Code : 08EC046 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Linear Equations: Fields; system of linear equations, and its solution sets;
elementary row operations and echelon forms; matrix operations; invertible
matrices, LU-factorization.
Vector Spaces: Vector spaces; subspaces; bases and dimension; coordinates;
summary of row-equivalence; computations concerning subspaces.
Linear Transformations: Linear transformations; algebra of linear
transformations; isomorphism; representation of transformations by matrices;
linear functionals; transpose of a linear transformation.
Canonical Forms: Characteristic values; annihilating polynomials; invariant
subspaces; direct-sum decompositions; invariant direct sums; primary
decomposition theorem; cyclic bases; Jordan canonical form. Iterative
estimates of characteristic values.
Inner Product Spaces: Inner products; inner product spaces; orthogonal sets
and projections; Gram-Schmidt process; QR-factorization; least-squares
problems; unitary operators.
Symmetric Matrices and Quadratic Forms: Digitalization; quadratic
forms; constrained optimization; singular value decomposition.
REFERENCE BOOKS:
1. David. C. Lay, “Linear Algebra and its Applications,” 3rd
edition,
Pearson Education (Asia) Pte. Ltd, 2005.
2. Kenneth Hoffman and Ray Kunze, "Linear Algebra," 2nd
edition,
Pearson Education (Asia) Pte. Ltd/ Prentice Hall of India, 2004. .
3. Bernard Kolman and David R. Hill, "Introductory Linear Algebra
with Applications," Pearson Education (Asia) Pte. Ltd, 7th
edition,
2003.
4. Gilbert Strang, "Linear Algebra and its Applications," 3rd
edition,
Thomson Learning Asia, 2003.
10
ELECTIVE – I
VLSI TECHNOLOGY
Subject Code : 08EC083 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Environment for VLSI Technology: Clean room and safety requirements.
Wafer cleaning processes and wet chemical etching techniques.
Impurity Incorporation: Solid State diffusion modeling and technology;
Ion Implantation modeling, technology and damage annealing;
characterization of Impurity profiles.
Oxidation: Kinetics of Silicon dioxide growth both for thick, thin and ultra
thin films. Oxidation technologies in VLSI and ULSI; Characterization of
oxide films; High k and low k dielectrics for ULSI.
Lithography: Photolithography, E-beam lithography and newer lithography
techniques for VLSI/ULSI; Mask generation.
Chemical Vapour Deposition Techniques: CVD techniques for deposition
of polysilicon, silicon dioxide, silicon nitride and metal films; Epitaxial
growth of silicon; modeling and technology.
Metal Film Deposition: Evaporation and sputtering techniques. Failure
mechanisms in metal interconnects; Multi-level metallization schemes.
Plasma and Rapid Thermal Processing: PECVD, Plasma etching and RIE
techniques; RTP techniques for annealing, growth and deposition of various
films for use in ULSI.
Process integration for NMOS, CMOS and Bipolar circuits; Advanced MOS
technologies
REFERENCE BOOKS:
1. C.Y. Chang and S.M.Sze (Ed), “ULSI Technology”, McGraw Hill
Companies Inc, 1996.
2. Stephena, Campbell, “The Science and Engineering of
Microelectronic Fabrication”, Second Edition, Oxford University
Press, 2005.
3. Yuan Taur, Tak. H. Ning, “Fundamentals of Modern VLSI
Devices”, Cambridge University Press, 2003
4. 11
4. S.K. Gandhi, “VLSI Fabrication Principles”, John Wiley Inc.,
New York, 1983.
ASIC DESIGN
Subject Code : 08EC012 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Note All Designs Will Be Based On VHDL
Introduction: Full Custom with ASIC, Semi custom ASICS, Standard Cell
based ASIC, Gate array based ASIC, Channeled gate array, Channel less gate
array, structured get array, Programmable logic device, FPGA design flow,
ASIC cell libraries
Data Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic
Operator, I/O cell, Cell Compilers
ASIC Library Design: Logical effort: practicing delay, logical area and
logical efficiency logical paths, multi stage cells, optimum delay, optimum
no. of stages, library cell design.
Low-Level Design Entry: Schematic Entry: Hierarchical design. The cell
library, Names, Schematic, Icons & Symbols, Nets, schematic entry for
ASIC’S, connections, vectored instances and buses, Edit in place attributes,
Netlist, screener, Back annotation
Programmable ASIC: programmable ASIC logic cell, ASIC I/O cell
A Brief Introduction to Low Level Design Language: an introduction to
EDIF, PLA Tools, an introduction to CFI designs representation. Half gate
ASIC. Introduction to Synthesis and Simulation;
ASIC Construction Floor Planning and Placement And Routing:
Physical Design, CAD Tools, System Partitioning, Estimating ASIC size,
partitioning methods. Floor planning tools, I/O and power planning, clock
planning, placement algorithms, iterative placement improvement, Time
driven placement methods. Physical Design flow global Routing, Local
Routing, Detail Routing, Special Routing, Circuit Extraction and DRC.
12
REFERENCE BOOKS:
1. M.J.S .Smith, - “Application - Specific Integrated Circuits” –
Pearson Education, 2003.
2. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI
Circuits for Telecommunication and signal processing”, Prentice
Hall, 1994.
3. Malcolm R.Haskard; Lan. C. May, “Analog VLSI Design - NMOS
and CMOS”, Prentice Hall, 1998.
4. Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and
Information Processing”, McGraw Hill, 1994.
DIGITAL SYSTEM DESIGN USING VHDL
Subject Code : 08EC032 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Specification of combinational systems using VHDL, Introduction to VHDL,
Basic language element of VHDL, Behavioral Modeling, Data flow
modeling, Structural modeling, Subprograms and overloading, VHDL
description of gates.
Description and design of sequential circuits using VHDL, Standard
combinational modules, Design of a Serial Adder with Accumulator, State
Graph for Control Network, design of a Binary Multiplier, Multiplication of a
Signed Binary Number, Design of a Binary Divider.
Register- transfer level systems, Execution Graph, Organization of System,
Implementation of RTL Systems, Analysis of RTL Systems, and Design of
RTL Systems.
Data Subsystems, Storage Modules, Functional Modules, Data paths, Control
Subsystems, Micro programmed Controller, Structure of a micro
programmed controller, Micro instruction Format, Micro instruction
sequencing, Micro instruction Timing, Basic component of a micro system,
memory subsystem.
5. 13
I/O Subsystem, Processors, Operation of the computer and cycle time, Binary
Decoder, Binary Encoder, Multiplexers and Demultiplexers, Floating Point
Arithmetic-Representation of Floating Point Number, Floating Point
Multiplication
REFERENCE BOOKS:
1. C. H. Roth, “Digital System Design using VHDL”, Thomson
Learning”, 2001
2. M. Ercegovac, T. Lang and L.J. Moreno, “Introduction to Digital
Systems”, Wiley,2000.
3. J. Bhaskar, “A VHDL Primer”, Addison Wesley, 1999.
4. John.F.Wakerly, “Digital Design-Principles and Practices”, PHI,
3rd
Edition updated, 2005
5. Navabi, “VHDL-Analysis and Modeling of Digital Systems”,
MGH
II – SEMESTER
DESIGN OF ANALOG & MIXED MODE VLSI CIRCUITS
Subject Code : 08EC025 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction to CMOS Analog Circuits : MOS transistor DC and AC small
signal parameters from large signal model,
Common Source Amplifier : with resistive load, diode load and current
source load, Source follower, Common gate amplifier, Cascode amplifier,
Folded Cascode, Frequency response of amplifiers, Current
source/sink/mirror, Matching, Wilson current source and Regulated Cascode
current source, Band gap reference,
Differential Amplifier, Gilbert cell, Op-Amp, Design of 2 stage Op-Amp,
DC and AC response, Frequency compensation, slew rate, Offset effects,
PSRR, Noise, Comparator,
14
Sense Amplifier, Sample and Hold, Sampled data circuits, Switched
capacitor filters, DAC, ADC, RF amplifier, Oscillator, PLL, Mixer.
REFERENCE BOOKS:
1. Razavi B., “Design of Analog CMOS Integrated Circuits”,
McGraw Hill, 2001
2. R. Jacob Baker,”CMOS: Mixed-Signal Circuit Dedsign”,
John Wiley, 2008
3. Baker, Li, Boyce, “CMOS: Circuit Design, Layout and
Simulation”, Prentice Hall of India, 2000
4. E. Allen, Douglas R. Holberg, “CMOS Analog circuit
Design”
REAL TIME EMBEDDED SYSTEMS
Subject Code : 08EC070 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction: Real Time System, Types, Real Time Computing, Design
Issue, Sample Systems, Hardware Requirements- Processor in a system,
System Memories, System I/O.
Hardware Requirements for Real-Time Applications: Processors,
Interfaces, (A/D, D/A, USART, Watchdog Timers, Interrupt Controllers).
Embedded Systems: Introduction, Various System Architecture for
Embedded System, High Performance Processors - Strong ARM processors,
Programming, Interrupt Structure, I/O architecture.
Real Time Operating System: Fundamental Requirements of RTOS, Real
Time Kernel Types, Schedulers, Various Scheduling modules with examples,
Latency (Interrupt Latency, Scheduling Latency and Context Switching
Latency), Tasks Management, State Transition Diagram, Task Control Block.
Mutual Exclusion, Inter-task communication and synchronization of tasks.
Memory and File management: Pipelining and Cache Memories, Paging
and Segmentation, Fragmentation, Address Translation.
6. 15
Case Study: Introduction to VX Works/Mucos/pSOS; Example systems.
Design of Real Time Systems: Introduction, Development Methodologies,
Real Time applications; Considerations such as double buffing, Design
Analysis.
REFERENCE BOOKS:
1. Stuart Bennett, “Real-Time Computer Control: An Introduction”,
2nd
Edn. Pearson Education, 2005
2. Philip. A. Laplante, “Real-Time Systems Design and Analysis- an
Engineer’s Handbook”- Second Edition, PHI Publications.
3. Jane W.S. Liu, “Real-Time Systems”, Pearson Education Inc.,
2000.
4. Dr. K.V.K K Prasad, “Embedded Real Time Systems: Concepts
Design and Programming”, Dreamtech Press New Delhi, 2003.
5. David A. Evesham, “Developing Real Time Systems – A Practical
Introduction”, Galgotia Publications, 1990.
LOW POWER VLSI DESIGN
Subject Code : 08EC047 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction : Need for low power VLSI chips, Sources of power dissipation
on Digital Integrated circuits. Emerging Low power approaches, Physics of
power dissipation in CMOS devices.
Device & Technology Impact on Low Power: Dynamic dissipation in
CMOS, Transistor sizing & gate oxide thickness, Impact of technology
Scaling, Technology & Device innovation
Power estimation, Simulation Power analysis: SPICE circuit simulators,
gate level logic simulation, capacitive power estimation, static state power,
gate level capacitance estimation, architecture level analysis, data correlation
analysis in DSP systems, Monte Carlo simulation.
16
Probabilistic power analysis: Random logic signals, probability &
frequency, probabilistic power analysis techniques, signal entropy.
Low Power Design Circuit level: Power consumption in circuits. Flip Flops
& Latches design, high capacitance nodes, low power digital cells library
Logic level: Gate reorganization, signal gating, logic encoding, state machine
encoding, pre-computation logic
Low power Architecture & Systems: Power & performance management,
switching activity reduction, parallel architecture with voltage reduction,
flow graph transformation, low power arithmetic components, low power
memory design.
Low power Clock Distribution: Power dissipation in clock distribution,
single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip &
package co design of clock network
Algorithm & Architectural Level Methodologies: Introduction, design
flow, Algorithmic level analysis & optimization, Architectural level
estimation & synthesis.
REFERENCE BOOKS:
1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit
Design” Wiley, 2000
2. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP,
2002
3. Rabaey, Pedram, “Low Power Design Methodologies” Kluwer
Academic, 1997
TESTING AND VERIFICATION OF VLSI CIRCUITS
Subject Code : 08EC078 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction: Scope of testing and verification in VLSI design process;
Issues in test and verification of complex chips; embedded cores and SOCs
Fundamentals of VLSI testing, Fault models. Automatic test pattern
generation, Design for testability, Scan design,
7. 17
Test interface and boundary scan.
System Testing and test for SOCs, Iddq testing, Delay fault testing, BIST for
testing of logic and memories, Test automation.
Design Verification Techniques based on simulation, analytical and formal
approaches, Functional verification, Timing verification, Formal verification,
Basics of equivalence checking and model checking,
REFERENCE BOOKS :
1. M. Abramovici, M. A. Breuer, A. D. Friedman, “Digital Systems
Testing and Testable Design” Piscataway, New Jersey: IEEE
Press, 1994
2. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing
for Digital, Memory and Mixed-Signal VLSI Circuits", Kluwer
Academic Publishers, 2000
3. T.Kropf, "Introduction to Formal Hardware Verification",
Springer Verlag, 2000.
4. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip
Verification-Methodology and Techniques", Kluwer Academic
Publishers, 2001.
5. Samiha Mourad and Yervant Zorian, “Principles of Testing
Electronic Systems”, Wiley (2000).
ELECTIVE -II
DESIGN OF VLSI SYSTEMS
Subject Code : 08EC027 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
VLSI System Design Methodology: Structure Design, Strategy, Hierarchy,
Regularity, Modularity, and Locality. System on Chip Design options:
Programmable logic and structures, Programmable interconnect,
18
programmable gate arrays, Sea of gate and gate array design, standard cell
design, full custom mask design.
Chip Design Methods: Behavioral synthesis, RTL synthesis, Logic
optimization and structural tools layout synthesis, layout synthesis, EDA
Tools for System
Design Capture Tools: HDL Design, Schematic Design, Layout Design,
Floor planning and Chip Composition. Design Verification Tools: Simulation
Timing Verifiers, Net List Comparison Layout Extraction, Design Rule
Verification.
Data Path Sub System Design: Introduction, Addition, Subtraction,
Comparators, Counters, Boolean logical operations, coding, shifters,
Multiplication, Parallel Prefix computations
Array Subsystem Design: SRAM, Special purpose RAMs, DRAM, Read
only memory, Content Addressable memory, Programmable logic arrays.
Control Unit Design: Finite State Machine (FSM) Design, Control Logic
Implementation: PLA control implementation, ROM control implementation.
Special Purpose Subsystems: Packaging, power distribution, I/O, Clock,
Transconductance amplifier, follower integrated circuits, etc
Design Economics: Nonrecurring and recurring engineering Costs, Fixed
Costs, Schedule, Person power, example
VLSI System Testing & Verification: Introduction, A walk through the
Test Process, Reliability, Logic Verification Principles, Silicon Debug
Principles, Manufacturing Test Principles, Design for Testability, Boundary
Scan
VLSI Applications: Case Study: RISC microcontroller, ATM Switch,
etc.
REFERENCE BOOKS:
1. Neil H.E. Weste, Davir Harris, “CMOS VLSI Design: A Circuits
and System Perspectives” Addison Wesley - Pearson Education,
3rd
Edition, 2004.
2. Wayne, Wolf, “Modern VLSI Design: System on Silicon”
Prentice Hall PTR/Pearson Education, Second Edition, 1998
8. 19
3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design”
PHI 3rd
Edition (original Edition – 1994)
ALGORITHMS FOR VLSI DESIGN AUTOMATION
Subject Code : 08EC010 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Logic Synthesis & Verification: Introduction to combinational logic
synthesis, Binary Decision Diagram, Hardware models for High-level
synthesis.
VLSI Automation Algorithms:
Partitioning: problem formulation, classification of partitioning algorithms,
Group migration algorithms, simulated annealing & evolution, other
partitioning algorithms
Placement, Floor Planning & Pin Assignment: problem formulation,
simulation base placement algorithms, other placement algorithms, constraint
based floor planning, floor planning algorithms for mixed block & cell
design. General & channel pin assignment
Global Routing: Problem formulation, classification of global routing
algorithms, Maze routing algorithm, line probe algorithm, Steiner Tree based
algorithms, ILP based approaches
Detailed Routing: problem formulation, classification of routing algorithms,
single layer routing algorithms, two layer channel routing algorithms, three
layer channel routing algorithms, and switchbox routing algorithms
Over The Cell Routing & Via Minimization: two layers over the cell
routers, constrained & unconstrained via minimization
Compaction: problem formulation, one-dimensional compaction, two
dimension based compaction, hierarchical compaction
REFERENCE BOOKS:
1. Naveed Shervani, “Algorithms for VLSI physical design
Automation”, Kluwer Academic Publisher, Second edition.
20
2. Christophn Meinel & Thorsten Theobold, “Algorithm and Data
Structures for VLSI Design”, KAP, 2002.
3. Rolf Drechsheler : “Evolutionary Algorithm for VLSI”, Second
edition
4. Trimburger, “Introduction to CAD for VLSI”, Kluwer Academic
publisher, 2002
ADVANCED EMBEDDED SYSTEM DESIGN
Subject Code : 08EC007 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction - The concept of embedded systems design, embedded
microcontroller cores, embedded memories, Examples of embedded systems.
Technological Aspects of Embedded Systems: interfacing between analog
and digital blocks, signal conditioning, Digital signal processing.
Sub-System Interfacing: interfacing with external systems, user interfacing.
Design trade offs due to process compatibility, thermal considerations, etc.
Software aspects of embedded systems: real time programming languages
and operating systems for embedded systems.
REFERENCE BOOKS:
1. J.W. Valvano, "Embedded Microcomputer System: Real Time
Interfacing", Brooks/Cole, 2000.
2. Jack Ganssle, "The Art of Designing Embedded Systems",
Newnes, 1999.
3. David Simon, "An Embedded Software Primer", Addison Wesley,
2000
9. 21
III – SEMESTER
CMOS RF CIRCUIT DESIGN
Subject Code : 08EC020 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction to RF Design and Wireless Technology: Design and
Applications, Complexity and Choice of Technology. Basic concepts in RF
design: Nonlinearly and Time Variance, Intersymbol interference, random
processes and noise. Sensitivity and dynamic range, conversion of gains and
distortion
RF Modulation: Analog and digital modulation of RF circuits, Comparison
of various techniques for power efficiency, Coherent and non-coherent
detection, Mobile RF communication and basics of Multiple Access
techniques. Receiver and Transmitter architectures, Direct conversion and
two-step transmitters
RF Testing: RF testing for heterodyne, Homodyne, Image reject, Direct IF
and sub sampled receivers.
BJT and MOSFET Behavior at RF Frequencies: BJT and MOSFET
behavior at RF frequencies, modeling of the transistors and SPICE model,
Noise performance and limitations of devices, integrated parasitic elements at
high frequencies and their monolithic implementation
RF Circuits Design: Overview of RF Filter design, Active RF components
& modeling, Matching and Biasing Networks. Basic blocks in RF systems
and their VLSI implementation, Low noise Amplifier design in various
technologies, Design of Mixers at GHz frequency range, Various mixers-
working and implementation. Oscillators- Basic topologies VCO and
definition of phase noise, Noise power and trade off. Resonator VCO
designs, Quadrature and single sideband generators. Radio frequency
Synthesizers- PLLS, Various RF synthesizer architectures and frequency
dividers, Power Amplifier design, Liberalization techniques, Design issues in
integrated RF filters.
REFERENCE BOOKS:
1. B. Razavi, “RF Microelectronics” PHI 1998
2. R. Jacob Baker, H.W. Li, D.E. Boyce “CMOS Circuit Design,
layout and Simulation”, PHI 1998.
22
3. Thomas H. Lee “Design of CMOS RF Integrated Circuits”
Cambridge University press 1998.
4. Y.P. Tsividis, “Mixed Analog and Digital Devices and
Technology”, TMH 1996
ELECTIVE - III
HARDWARE - SOFTWARE CO-DESIGN
Subject Code : 08EC041 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction: Motivation hardware & software co-design, system design
consideration, research scope & overviews
Hardware Software back ground: Embedded systems, models of design
representation, the virtual machine hierarchy, the performance3 modeling,
Hardware Software development,
Hardware Software Co-Design Research: An informal view of co-design,
Hardware Software tradeoffs, crosses fertilization, typical co-design process,
co-design environments, limitation of existing approaches, ADEPT modeling
environment.
Co-design Concepts: Functions, functional decomposition, virtual machines,
Hardware Software partitioning, Hardware Software partitions, Hardware
Software alterations, Hardware Software trade offs, co-design.
Methodology for Co-Design: Amount of unification, general consideration
& basic philosophies, a framework for co-design
Unified Representation for Hardware & Software: Benefits of unified
representation, modeling concepts
An Abstract Hardware & Software Model: Requirement & applications of
the models, models of Hardware Software system, an abstract Hardware
Software models, generality of the model
Performance Evaluation: Application of t he abstract Hardware & Software
model, examples of performance evaluation
10. 23
Object Oriented Techniques in Hardware Design: Motivation for object
oriented technique, data types, modeling hardware components as classes,
designing specialized components, data decomposition, Processor example.
REFERENCE BOOKS:
1. Sanjaya Kumar, James H. Ayler “The Co-design of Embedded
Systems: A Unified Hardware Software Representation”,
Kluwer Academic Publisher, 2002 .
2. H. Kopetz, “Real-Time Systems”, Kluwer, 1997.
3. R. Gupta, “Co-synthesis of Hardware and Software for
Embedded Systems”, Kluwer 1995.
4. S. Allworth, “Introduction to Real-time Software Design”,
Springer-Verlag, 1984.
5. C. M. Krishna, K. Shin, “Real-time Systems”, Mc-Graw Hill, 1997
6. Peter Marwedel, G. Goosens, “Code Generation for Embedded
Processors”, Kluwer Academic Publishers, 1995.
SYNTHESIS AND OPTIMIZATION OF
DIGITAL CIRCUITS
Subject Code : 08EC077 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction: Microelectronics, semiconductor technologies and circuit
taxonomy, Microelectronic design styles, computer aided synthesis and
optimization.
Graphs: Notation, undirected graphs, directed graphs, combinatorial
optimization, Algorithms, tractable and intractable problems, algorithms for
linear and integer programs, graph optimization problems and algorithms,
Boolean algebra and Applications.
24
Hardware Modeling: Hardware Modeling Languages, distinctive features,
structural hardware language, Behavioral hardware language, HDLs used in
synthesis, abstract models, structures logic networks, state diagrams, data
flow and sequencing graphs, compilation and optimization techniques.
Two Level Combinational Logic Optimization: Logic optimization,
principles, operation on two level logic covers, algorithms for logic
minimization, symbolic minimization and encoding property, minimization
of Boolean relations.
Multiple Level Combinational Optimizations: Models and transformations
for combinational networks, algebraic model, Synthesis of testable network,
algorithm for delay evaluation and optimization, rule based system for logic
optimization.
Sequential Circuit Optimization: Sequential circuit optimization using state
based models, sequential circuit optimization using network models.
Schedule Algorithms: A model for scheduling problems, Scheduling with
resource and without resource constraints, Scheduling algorithms for
extended sequencing models, Scheduling Pipe lined circuits.
Cell Library Binding: Problem formulation and analysis, algorithms for
library binding, specific problems and algorithms for library binding (lookup
table F.P.G.As and Antifuse based F.P.G.As), rule based library binding.
Testing: Simulation, Types of simulators, basic components of a simulator,
fault simulation Techniques, Automatic test pattern generation methods
(ATPG), design for Testability (DFT) Techniques.
REFERENCE BOOKS:
1. Giovanni De Micheli, “Synthesis and Optimization of Digital
Circuits”, Tata McGraw-Hill, 2003.
2. Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, “Logic
Synthesis”, McGraw-Hill, USA, 1994.
3. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design:
A System Perspective,” 2nd
edition, Pearson Education (Asia)
Pte. Ltd., 2000.
4. Kevin Skahill, “VHDL for Programmable Logic,” Pearson
Education (Asia) Pte. Ltd., 2000.
11. 25
CAD TOOLS FOR VLSI DESIGN
Subject Code : 08EC019 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction to VLSI Methodologies - VLSI Physical Design Automation -
Design and Fabrication of VLSI Devices - Fabrication process and its impact
on Physical Design.
A Quick Tour of VLSI Design Automation Tools: Data structures and
Basic Algorithms, Algorithmic Graph theory and computational complexity,
Tractable and Intractable problems.
General Purpose Methods for Combinational Optimization: partitioning,
floor planning and pin assignment, placement, routing.
Simulation-Logic Synthesis: Verification-High level synthesis -
Compaction. Physical Design Automation of FPGAs, MCMS-VHDL-
Verilog-Implementation of Simple circuits using VHDL and Verilog.
REFERENCE BOOKS:
1. N.A. Shervani, “Algorithms for VLSI Physical Design
Automation”, 1999.
2. S.H.Gerez, “Algorithms for VLSI Design Automation”, 1998.
ELECTIVE-IV
ADVANCES IN VLSI DESIGN
Subject Code : 08EC009 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Review of MOS Circuits: MOS and CMOS static plots, switches,
comparison between CMOS and BI - CMOS.
MESFETS: MESFET and MODFET operations, quantitative description of
MESFETS.
26
MIS Structures and MOSFETS: MIS systems in equilibrium, under bias,
small signal operation of MESFETS and MOSFETS.
Short Channel Effects and Challenges to CMOS: Short channel effects,
scaling theory, processing challenges to further CMOS miniaturization
Beyond CMOS: Evolutionary advances beyond CMOS, carbon Nano tubes,
conventional vs. tactile computing, computing, molecular and biological
computing Mole electronics-molecular Diode and diode- diode logic .Defect
tolerant computing,
Super Buffers, Bi-CMOS and Steering Logic: Introduction, RC delay
lines, super buffers- An NMOS super buffer, tri state super buffer and pad
drivers, CMOS super buffers, Dynamic ratio less inverters, large capacitive
loads, pass logic, designing of transistor logic, General functional blocks -
NMOS and CMOS functional blocks.
Special Circuit Layouts and Technology Mapping: Introduction, Talley
circuits, NAND-NAND, NOR- NOR, and AOI Logic, NMOS, CMOS
Multiplexers, Barrel shifter, Wire routing and module lay out.
System Design: CMOS design methods, structured design methods,
Strategies encompassing hierarchy, regularity, modularity & locality, CMOS
Chip design Options, programmable logic, Programmable inter connect,
programmable structure, Gate arrays standard cell approach, Full custom
Design.
REFERENCE BOOKS:
1. Kevin F Brrnnan “Introduction to Semi Conductor Device”,
Cambridge publications
2. Eugene D Fabricius “Introduction to VLSI Design”, McGraw-Hill
International publications
3. D.A Pucknell “Basic VLSI Design”, PHI Publication
4. Wayne Wolf, “Modern VLSI Design” Pearson Education, Second
Edition , 2002
12. 27
RF AND MICROWAVE CIRCUIT DESIGN
Subject Code : 08EC071 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Wave Propagation in Networks: Introduction to RF/Microwave Concepts
and applications; RF Electronics Concepts; Fundamental Concepts in Wave
Propagation; Circuit Representations of two port RF/MW networks
Passive Circuit Design: The Smith Chart, Application of the Smith Chart in
Distributed and lumped element circuit applications, Design of Matching
networks.
Basic Considerations in Active Networks: Stability Consideration in Active
networks, Gain Considerations in Amplifiers, Noise Considerations in Active
Networks.
Active Networks: Linear and Nonlinear Design: RF/MW Amplifiers Small
Signal Design, Large Signal Design, RF/MW Oscillator Design, RF/MW
Frequency Conversion Rectifier and Detector Design, Mixer Design, RF/MW
Control Circuit Design, RF/MW Integrated circuit design.
REFERENCE BOOKS:
1. Matthew M. Radmanesh, “Radio Frequency and Microwave
Electronics Illustrated," Pearson Education (Asia) Pte. Ltd., 2004.
2. Reinhold Ludwig and Pavel Bretchko, “RF Circuit Design: Theory
and Applications,” Pearson Education (Asia) Pte. Ltd., 2004.
VLSI SUB-SYSTEM DESIGN
Subject Code : 08EC081 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Review of Transistor, Inverter Analysis, CMOS Process and Masking
Sequence, Layer Properties and Parasitic Estimation;
VLSI Design Flow, Design Methodologies, Abstraction Levels;
28
Design of Data Processing Elements: Adder Architectures, Multiplier
Architectures, Counter Architectures, ALU Architectures,
Design of Storage Elements: Latches, Flip-Flops, Registers, Register Files;
Design of Control Part: Moore & Mealy Machines, PLA Based
Implementation, Random Logic Implementation, Micro-programmed
Implementation;
Structuring of Logic Design: PLA Design, PLA Architectures, Gates Array
Cell Design, Concept of Standard Cell Based Design, Cell Library Design;
Memory Design: SRAM cell, Various DRAM cells, RAM Architectures,
Address Decoding, Read/Write Circuitry, Sense Amplifier and their Design,
ROM Design;
Clocking Strategies, Clock Skew, Clock Distribution and Routing, Clock
Buffering, Clock Domains, Gated Clock, Clock Tree; Synchronization
Failure and Meta-stability.
REFERENCE BOOKS:
1. Neil H. E. Weste and Kamran Eshraghian, “Principles of CMOS
VLSI Design – A Systems Perspective”, Addison Wesley.
2. Wayne Wolf, “Modern VLSI Design”, Prentice Hall.
3. C. Mead and L. Conway, “Introduction to VLSI Systems”,
Addison Wesley.
4. J. P. Uyemura, “Circuit Design for CMOS VLSI”, Kluwer
Academic.