The document details the VHDL code for the ADC0804, a 4-bit magnitude comparator, and a parity generator, including features, pin descriptions, interface schematics, and simulation results. The ADC0804 is an 8-bit parallel analog-to-digital converter ideal for applications requiring moderate accuracy, with a conversion time of up to 100 μs. Additionally, it discusses the functionality of the parity generator for error detection in binary transmissions and the operation of the comparator for multi-bit binary number comparisons.

1. VHDL CODE FOR ADC0804, 4-BIT
MAGNITUDE COMPARATOR AND
PARITY GENERATOR
Presented by:- APARNA
Department of Electronics Engineering
(VLSI & ES)

2. TOPICS
 ADC0804
 ADC
 FEATURES
 PIN DIAGRAM & DISCRIPTION
 ADC0804 INTERFACE SCHEMATIC & TIMING DIAGRAM
 VHDL CODE & SIMULATION RESULT
 PARITY GENERATOR
 INTRODUCTION
 VHDL CODE & SIMULATION RESULT
 4-BIT MAGNITUDE COMPARATOR
 INTRODUCTION
 VHDL CODE & SIMULATION RESULT

3. ADC
 Analog-to-digital converter (ADC) is a device which can
convert analogue voltage to digital numbers so that
microcontrollers and microprocessors can handle and process
the data.
 ADC are the most widely used devices for data acquisition.
 ADC has n-bit resolution, where n can be 8, 12, 16 or even 24
bits.

4.  The higher-resolution ADC provides a smaller step size.
 Step size is the smallest change that can be recognized by ADC
 Vcc is the reference voltage of ADC with n-bit resolution.
 Table : Resolution versus Step Size for ADC (if Vcc = 5V)
1
2 
 n
cc
V
Size
Step

5. ADC0804 IC

6. ADC0804
Features
 Single channel ,8-bit parallel ADC module
 Easy to interface with all
Microprocessors or works
Stand alone.
 Differential analog voltage inputs. 0V to 5V analog input
voltage range with single 5V supply.
 On chip Clock available.

7.  Digital output various from 0 to 255.
 When Vref = 5V, for every 19.60mV of analog value there will
be rise of one bit on digital side (Step size)
 Available in 20-pin PDIP, SOIC packages.
 A common, low-cost ADC, compatible with a wide range of
microprocessors. There are many faster ADCs available with
more resolution, this device is ideal for applications that do
not require a high degree of accuracy.
 ADC0804 requires up to 100 µs to convert an analog input
voltage into a digital output code.

8. ADC0804 PIN DIAGRAM

9. PIN DESCRIPTION
Pin No Function Name
1
Activates ADC; Active low ; used if more than 1 ADC module is used.
By default grounded
Chip select
2
Input pin; High to low pulse brings the data from internal registers to
the output pins after conversion
Read
3 Input pin; Low to high pulse is given to start the conversion Write
4 Clock Input pin; to give external clock. Clock IN
5 Output pin; Goes low when conversion is complete Interrupt
6 Analog non-inverting input Vin(+)
7 Analog inverting Input; normally ground Vin(-)
8 Ground(0V) Analog Ground
9 Input pin; sets the reference voltage for analog input Vref/2
10 Ground(0V) Digital Ground
11
8 bit digital output pins
D7
12 D6
13 D5
14 D4
15 D3
16 D2
17 D1
18 D0
19 Used with Clock IN pin when internal clock source is used Clock R
20 Supply voltage; 5V Vcc

10. TIMING DIAGRAM FOR ADC0804

11. ADC0804 INTERFACE
INTR/EOC
ADC 8-BIT OUTPUT
ADC0804 FPGA
RD/OE
WR/SC
Analog
input
ADC OUTPUT
(LED)
CLK

12. VHDL CODE FOR ADC0804

14. SIMULATION RESULT

16. PARITY GENERATOR
 A Parity Generator is a Combinational Logic Circuit that
Generates the Parity bit in the Transmitter.
 A Parity bit is used for the Purpose of Detecting Errors during
Transmissions of binary Information.
 It is an Extra bit Included with a binary Message to Make the
Number of 1’s either Odd or Even.

17. Two Types of Parity
 In Even Parity, the added Parity bit will Make the Total
Number of 1’s an Even Amount.
 In Odd Parity, the added Parity bit will Make the Total
Number of 1’s an Odd Amount.

18. PARITY GENERATOR TRUTH TABLE

19. VHDL CODE FOR ODD PARITY

20. SIMULATION RESULT

21. 4-BIT MAGNITUDE COMPARATOR
 Compare two multi-bit binary numbers
 The comparison of two numbers
outputs: A>B, A=B, A<B

22. LOGIC USED IN VHDL CODE
in_1=_ _ _ _
in_2=_ _ _ _
‘0’ -> unsigned bit vector
Comp_type
‘1’-> signed bit vector
in_1= 0 _ _ _ in_1= 1 _ _ _
in_2= 0 _ _ _ in_2= 1 _ _ _
in_1= 1 _ _ _ in_1= 0 _ _ _
in_2= 0 _ _ _ in_2= 1 _ _ _

23. VHDL CODE FOR COMPARATOR

25. SIMULATION RESULT

26. THANK YOU