System Verilog training prepares the individuals for industries to take verification tasks. Participants will learn the basic and advanced test bench skills required to drive the desired output. The curriculum is designed to deliver different approaches and techniques used in industry to solve the problems

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Verilog, SV and UVM
Course Content
www.multisoftsystems.com B-125, Sector 2 Noida

2. info@multisoftsystems.com 98103 06956
Verilog, SV and UVM
Course Content
Pre-requisites:-
1. https://www.edaplayground.com/ EDA Playground Registration to access Simulation
Tools.
2. Basic knowledge of Digital Design Concepts.
3. Fundamentals of any Programming Language preferably Verilog.
Goal:-
 Understanding of SV and UVM Environment, Test bench and Verification
Challenges.
 Should be able to writing System Verilog and UVM TB model for simple to
complex Digital Logic circuits.

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I. HDL – Verilog
4. Introduction
5. Language Basics
6. Behavioral Verilog
7. Modeling Techniques
8. Miscellaneous Topics
9. Synthesis Perspective
10.Gate Level Modeling, Timing specification capture
11.Verification Perspective
12.Introduction to PLI(Program Language Interface)
13.Verilog-2001 enhancements
1. Assessment: - FAQ Discussion & DIY (Do It Yourself) of Digital Block Design & Test bench

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Phase -2
II. SV-Design and Verification (HDL & HVL)
 Introduction.
 Enhanced, New data types
 Structs, Unions
 Procedural Constructs
 Arrays
 Packages
 Port Connections
 Interface, Modport Clocking block.
 Classes: Object Oriented Programming
 Arrays, Data Types, Literals, Operators
 Scheduling Semantics, Inter process Synchronization
 Processes, Threads, Tasks and Functions
 Randomization, Constraints
 Interface, Clocking blocks, Program Block
 Functional Coverage
 System Tasks & Functions
 Compiler Directives

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2. Assessment: - FAQ Discussion & DIY (Do It Yourself) of Test Bench
14.Introduction on Verification technologies
15.Verification using SV Test bench
III. UVM (UNIVERSAL VERIFICATION METHODOLOGY)
UVM Overview
 UVM Evolution
 UVM Structural Pieces and Classes
 Phases, Reporting, Factory and Config_db
 Writing a Simple UVM Testbench
 UVM Classes and Field Macros
 UVM Environment Architecture
 TB Top, Test, Environment, Agent
 Sequencer, Driver, Monitor, Scoreboard
 Sequence and Sequence Item
 Factory Overriding
 Functional Coverage Integration
 Signal level Functional Coverage
 Transaction level Functional Coverage
 Integrating Functional Coverage into UVM Testbench

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3. Assessment: - FAQ Discussion & DIY (Do It Yourself) of Test Bench
 Introduction on Verification technologies
 Verification using UVM Test bench