SPICE MODEL of uPC4250C in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.

1. Device Modeling Report
COMPONENTS: OPERATIONAL AMPLIFIER
PART NUMBER: uPC4250C
MANUFACTURER: NEC ELECTRONICS
REMARK TYPE: (OPAMP)
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

2. Spice Model
U6
1 8
OFFSET NULL Iset
2 7
II V+
3 6
IN OUT
4 5
V- OFFSET NULL
UPC4250
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

3. Output Voltage Swing, +Vout and –Vout
Evaluation circuit
V+
U6
1 8 15Vdc
OFFSET NULL Iset
2 7 0
II V+
Vi
VOFF = 0 3 6 Vout
VAMPL = 0 IN OUT Vout
FREQ = 0 4 5 0Vdc Rload
AC = 0 V- OFFSET NULL
DC = 0 V- 10k
Vin UPC4250
0 VOFF = 0
VAMPL = 0
FREQ = 0 -15Vdc
AC = 0 0
DC = 0 0
0
The output voltage change of Opamp(open loop) when input DC voltage
(Vin -Vi) is changed with the evaluation circuit is simulated
Simulation result
These simulation results are compared with +Vout
Output Voltage Swing Data sheet Simulation %Error
+Vout(V) 12 11.983 0.141666
-Vout(V) 12 -11.983 0.141666
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

4. Input Offset Voltage
Evaluation circuit
V+
U6
1 8 15Vdc
OFFSET NULL Iset
2 7 0
II V+
Vi
VOFF = 0 3 6
VAMPL = 0 IN OUT Vout
FREQ = 0 4 5 Rload
AC = 0 V- OFFSET NULL
DC = 0 V- 1n
Vin UPC4250
0 VOFF = 0
VAMPL = 0
FREQ = 0 -15Vdc
AC = 0 0
DC = 0 0
0
Simulation result
Measurement Simulation Error
Vos
6 mV 6.3127 mV 5.2346 %
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

5. Slew Rate, +SR, -SR
Evaluation circuit
V+
U6
1 8 15Vdc
OFFSET NULL Iset
2 7 0
II V+
3 6
IN OUT Vout
V1 = 0 V1 4 5 Rload
V2 = 12 V- OFFSET NULL
TD = 0 V- 10k
UPC4250
TR = 10n
0 TF = 10n
PW = 5u -15Vdc
PER = 500u 0
V2 0
-6.3127m
0
The output voltage change versus time (slope) of op-amp when input electric
step voltage.
Simulation result
Output voltage change 0.2V in 1 us (If no good can change C2 of Spice
Model Editor)
Data sheet Simulation %Error
Slew Rate(v/us)
0.2 0.19999 0.005
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

6. Input current Ib, Ibos
Evaluation circuit
V+
U6
1 8 15Vdc
OFFSET NULL Iset
2 7 0
II V+
3 6
IN OUT Vout
Vin
Vi VOFF = -6.3127m 4 5 Rload
VOFF = -6.3127m VAMPL = 0 V- OFFSET NULL
VAMPL = 0 FREQ = 0 V- 10k
UPC4250
FREQ = 0 AC = 0
AC = 0 DC = 0
DC = 0 0 -15Vdc
0 0 0
The input offset current when supply voltage to op-amp
Simulation result
I(Vin) =84.573mA, I(Vi) =64.970mA :Ib =( I(Vin)+ I(Vi))/2=,Ibos =19.603m
Data sheet Simulation %Error
Ib(mA) 75 74.7715 0.304666667
Ibos(mA) 20 19.603 1.985
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

7. Open Loop Voltage Gain vs. Frequency, Av-dc, f-0dB
Evaluation circuit
V+
U6
1 8 15Vdc
OFFSET NULL Iset
2 7 0
II V+
3 6
IN OUT Vout
Vi Vin
VOFF = 0 VOFF = 0 4 5 Rload
VAMPL = 0 VAMPL = 0 V- OFFSET NULL
FREQ = 0 FREQ = 0 V- 10k
UPC4250
AC = 0 AC = 1m
DC = 0 DC = -6.3127m
0 0 -15Vdc
0 0
The open loop voltage gain of op-amp when supply AC input voltage 0.35MHz
frequecy
Simulation result
Data sheet Simulation %Error
f-0dB(MHz) 0.35 0.37 5.7
Av-dc 60000(min) 55526 7.4566
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

8. Output Short Circuit Current - Ios
Evaluation circuit
V+
U6
1 8 15Vdc
OFFSET NULL Iset
2 7 0
II V+ V6
3 6
IN OUT Vout
Vin
Vi VOFF = -6.3127m 4 5 0 Rload
VOFF = 0 VAMPL = 0 V- OFFSET NULL
VAMPL = 0 FREQ = 0 V- 1n
UPC4250
FREQ = 0 AC = 0
AC = 0 DC = 0
DC = 0 0 -15Vdc
0 0 0
Simulation result
Short Circuit current
Short Circuit Data sheet Simulation %Error
Current 11mA 11.43mA 3.9
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004

9. Common-Mode Rejection Voltage gain
Evaluation circuit
V+
U6
1 8 15Vdc
Vi OFFSET NULL Iset
2 7 0
-6.3127m II V+
Vof f 0Vdc 3 6
IN OUT Vout
4 5
Vin V- OFFSET NULL
V-
UPC4250
V1 0Vdc
VOFF = 0
VAMPL = 0.59 -15Vdc
FREQ = 1
AC = 0 0
DC = 0
0
Simulation result
Common mode gain=17.066/1
Common Mode Reject Ratio=55526/17.066=3253.6
Data sheet Simulation %Error
CMRR
3162.3 3253.6 2.887
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004