The document provides an overview of the NVIDIA Tegra K1 mobile processor. It details the modules that interface with external devices or control fundamental chip operations, including an interrupt controller, semaphores, clock and reset controller, timers, pin multiplexing, power management controller, real-time clock, and host subsystem. The document is intended to provide information for programming and interfacing with the covered modules.
PocketPORT is the world’s smallest 3G/4G Cellular Modem to Ethernet Bridge. The PocketPORT instantly connects virtually any cellular (3G/4G) USB modem to any Ethernet device simply by plugging both devices into the PocketPORT. Any device that can be connected to a cable, DSL or satellite modem, Ethernet switch or hub can use the PocketPORT to get Internet service via an inexpensive USB modem from cellular service providers. The PocketPORT is the highly portable, simple and low-cost alternative to large, complex and expensive cellular Ethernet modems.
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PocketPORT is the world’s smallest 3G/4G Cellular Modem to Ethernet Bridge. The PocketPORT instantly connects virtually any cellular (3G/4G) USB modem to any Ethernet device simply by plugging both devices into the PocketPORT. Any device that can be connected to a cable, DSL or satellite modem, Ethernet switch or hub can use the PocketPORT to get Internet service via an inexpensive USB modem from cellular service providers. The PocketPORT is the highly portable, simple and low-cost alternative to large, complex and expensive cellular Ethernet modems.
Use a PocketPORT wherever wired Internet service is unavailable, difficult, costly or time-consuming to install. Plug a PocketPORT into the Ethernet port of devices such as IP cameras (web cams) for security applications, programmable logic controllers (PLC) for industrial processes, digital & network video recorders (DVR/NVR) or any other equipment that needs Internet service for remote access. Have field service technicians keep a PocketPORT in their “pocket” for instant Internet access for remote equipment when they are on site visits.
DFM Industrial is designed for accurate flow rate measurement of fuel and other liquids used in sea and river vessels, fuel delivery from truck tankers, in high-power diesel generator sets and boilers, in petrochemical, utilities and other industrial applications (IIoT).
Model line of DFM Industrial flowmeters includes autonomous counters with electronic display only (LCD) and flow meters with LCD and output interface cable for sending data to recording devices, displays, tracking units, telematics units.
DFM Industrial flowmeter is mainly used as a part of ship monitoring and machinery operation tracking systems, and as part of Industrial Internet of Things (IIoT) systems, also as autonomous solution for fuel/ liquid consumption.
Yokogawa Model GX10/GX20/GP10/GP20 Paperless Recorder First Step GuidePower Specialties, Inc.
The GP series is an industry-first multi-point touch panel, to improve intuitive and smart operator control. Users can scroll, pan, zoom historical data, and even write freehand messages on its dust-proof and water-proof display. It delivers industry leading reliability and measurement accuracy. The GP series is ideally suited for monitoring or troubleshooting long term physical or electrical trends.
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Yokogawa Model GX10/GX20/GP10/GP20 Paperless Recorder First Step Guide
Tegra k1 trm_dp06905001_v02p
1. TECHNICAL REFERENCE MANUAL
NVIDIA Tegra K1 Mobile Processor
Abstract
The Technical Reference Manual focuses on the logical organization and control of Tegra K1 mobile processors. It
provides information for those modules that interface to external devices, or those that control fundamental chip
operations. The modules detailed in this document provide an overview, any necessary programming guidelines, and
a register listing for that module. Internal functional units such as video and graphics hardware acceleration are
controlled by NVIDIA provided software and not documented here.
Revision History
Version Date Description
v01p MAR 20, 2014 Public release to support Open Source Development. This document is a work in progress. There will be follow-up
releases as new information is made available.
v02p JUL 15, 2014 • Revised DSI and eDP maximum resolution to 3200x2000.
• I2C Controller: Revised encoding for BC_TERMINATE field.
• USB Complex: Revised maximum packet size supported on any endpoint to 1024 bytes. Clarified encoding
of MEM_ALIGNMENT_MUX_EN fields.
TEGRA K1 | TRM | DP-06905-001_v02p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com
2. Tegra K1 Technical Reference Manual
Table of Contents
TEGRA K1 | TRM | DP-06905-001_v02p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 2
Table of Contents
1.0 Introduction....................................................................................................................................................... 11
1.1 The Role of the Technical Reference Manual.............................................................................................. 11
1.2 Block Diagram .............................................................................................................................................. 12
1.3 Memory Controller and Internal Bus Architecture ........................................................................................ 13
1.4 Reading Register Tables.............................................................................................................................. 14
1.5 Glossary........................................................................................................................................................ 15
2.0 Address Map..................................................................................................................................................... 19
2.1 System Address Map ................................................................................................................................... 19
2.2 Available DRAM Address Ranges................................................................................................................ 25
3.0 Interrupt Controller............................................................................................................................................ 29
3.1 References ................................................................................................................................................... 29
3.2 Interrupt Mapping.......................................................................................................................................... 29
3.3 Hierarchical Groups...................................................................................................................................... 34
3.4 Functional Description .................................................................................................................................. 34
3.5 Interrupt Registers ........................................................................................................................................ 43
4.0 Semaphores ..................................................................................................................................................... 49
4.1 Arbitration Semaphores................................................................................................................................ 49
4.2 Semaphore Registers................................................................................................................................... 50
5.0 Clock and Reset Controller............................................................................................................................... 53
5.1 Hardware Features....................................................................................................................................... 53
5.2 Clocking Architecture.................................................................................................................................... 54
5.3 PLLs.............................................................................................................................................................. 70
5.4 Reset Architecture ........................................................................................................................................ 73
5.5 Power Gating and Ungating ......................................................................................................................... 73
5.6 Software Features and Programming Model................................................................................................ 75
5.7 Clock and Reset Controller Registers .......................................................................................................... 90
6.0 CL-DVFS ........................................................................................................................................................ 245
6.1 CL-DVFS Registers .................................................................................................................................... 245
7.0 Timers............................................................................................................................................................. 251
7.1 ARM CPU Generic Timers (GITs) .............................................................................................................. 251
7.2 Generic Timer System Counter (TSC) ....................................................................................................... 251
7.3 NVIDIA Timers (TMR) ................................................................................................................................ 252
7.4 Watchdog Timers (WDTs).......................................................................................................................... 253
7.5 Secure TMRs and Secure WDTs ............................................................................................................... 253
7.6 Legacy Watchdog Timer............................................................................................................................. 254
7.7 Watchdog Timer Programming Guide........................................................................................................ 255
9. Tegra K1 Technical Reference Manual
Table of Contents
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37.2 Features.................................................................................................................................................. 2331
37.3 Address Space ....................................................................................................................................... 2332
37.4 Reference Block Decomposition ............................................................................................................ 2332
37.5 Memory Management Unit ..................................................................................................................... 2334
37.6 Access to Memory.................................................................................................................................. 2335
37.7 Cache Maintenance................................................................................................................................ 2336
37.8 AVP Cache Controller Registers ............................................................................................................ 2336
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Table of Contents
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11. Tegra K1 Technical Reference Manual
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1.0 INTRODUCTION
The NVIDIA
®
Tegra
®
K1 mobile processor is a complete applications and digital media system built around several powerful
hardware elements:
Graphics: NVIDIA
®
GeForce
®
Kepler Graphics Processing Unit (GPU). The GPU fully supports DX11, Shader Model
4, and OpenGL4.3 as well as OpenGL ES 3.0. It supports Unified shaders and is GPU compute capable with 192
CUDA cores. The GPU supports all the same features as discrete NVIDIA GPUs, including PhysX, CUDA, OpenCL,
and DX compute. It is highly power optimized for best performance in mobile use cases.
CPU Complex: Quad Cortex
®
-A15 Symmetric Multi-Processing ARM
®
Cores in a 4-PLUS-1™ configuration with a
quad-core fast CPU complex and a fifth Battery Saver Core. The Cortex-A15 core features triple instruction issue and
both out-of-order and speculative execution. It has full cache coherency support for the quad symmetric processors.
All processors have 32 KB Instruction and 32 KB Data Level 1 caches; and there is a 2 MB shared Level 2 cache for
the quad-core complex and a 512 KB Level 2 cache for the fifth core. The NVIDIA 4-PLUS-1 architecture uses the
fifth Battery Saver Core, which operates exclusively with the main CPU complex, for very low-power, low-leakage
operation at the light CPU loads common to multimedia and lightly loaded use situations.
Memory Controller: 64-bit DRAM interface providing high bandwidth. LP-DDR3 and DDR3L DRAM types are
supported.
Audio/Video Decoder: the Audio-Video Processor (AVP) subsystem includes dedicated audio and video decode
hardware acceleration, an ARM7 processor, and embedded RAM. This subsystem provides full motion playback of
up to 1440P high-definition video and supports H.264 BP/MP/HP/MVC, VC-1, VP8, MPEG-2 and MPEG-4 video
standards and multiple audio standards with dedicated hardware.
Video Encoder: A high performance H.264 capable hardware video encoder. This processor supports H.264
BP/MP/HP/MVC and VP8 encoding.
Imaging: A high-quality hardware accelerated still-image and video capture path, with dual next-generation ISP3s.
Display: Dual display controllers with MIPI-DSI output, along with LVDS or eDP support for LCD panels and HDMI
output for external display devices. Multiple line pixel storage allows more memory-efficient scaling operations and
pixel fetching. Hardware display surface rotation is also provided for bandwidth reduction.
In addition to these major elements, Tegra K1 mobile processors have a broad range of peripheral interfaces to enable
communication with wireless baseband, other communications peripherals, audio codecs, power management, and mass
storage. When combined with baseband and PMIC chips, the Tegra K1 mobile processor provides the functionality needed to
build a range of low-power devices. Dedicated high-performance mass storage controllers, with their own DMA engines, free
the CPU Complex from routine data management tasks.
1.1 The Role of the Technical Reference Manual
This document is intended to provide guidance to programmers writing code for Tegra K1 devices. It describes the register
interfaces and hardware functionality, with the goal to aid anyone in understanding and potentially modifying the NVIDIA
provided code.
It may also describe hardware functions not currently supported by NVIDIA drivers; thus the description of a capability in this
document does not necessarily imply software support for that function.
12. Tegra K1 Technical Reference Manual
Introduction
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1.2 Block Diagram
This diagram provides an overview of a Tegra K1 mobile processor.
Figure 1: Tegra K1 Processor Block Diagram
FM Receiver
Front
TEGRA
PMU
Camera
(Stereo Optional)
External Display
(3D Optional)
Memory
Card
Microphone
Headset
Stereo Speaker
Battery
PC / USB
Peripherals
CPU Complex
4-PLUS-1™ Quad-Core Processor
ARM®
Cortex®
-A15 MPCore
Camera
Display
Controller
1 & 2
SDMMC
PCIe
JTAG
SATA
I2CI2SPWR I2C
SDMMC
I2S
I2C
I2S
BB I/F
Platform Security Engine
Boot/Secure ROM
Timers, Interrupt Controller
CSI x 1
YUV / RAW / CSI x 4
SPI, I2C
DSI x 4
DSI x 4
2nd
LCD
Main LCD
(3D Optional)
HDMI
SD
HSIC
PCM
I2C PCM
HS USB 2.0
Bluetooth
L
PCM (BT)
I2C (NFC)
I2S
PCM (FM)
DDR3L / LP-DDR3 / LP-DDR2
eMMC
ULP Audio
Kepler Mobile GPU
HD Video Decoder HD Video Encoder
Touch
Screen
UART
CTL
Audio DAC
Charging
LDOs
DC/DCs
R
VBUS (5V)
SDMMC
GPS
WLAN
FM Radio
SDIO (WF)
UART (BT)
2 x
USB 3.0
3 x
USB 2.0
Security Coprocessor
(TSEC)
Antennas:
- WiFi + BT
- GPS
- NFC
USB 3.0
Debug
YUV / RAW / CSI x 4
SPI (Smart Panel)
I2C
Advanced Imaging
Audio-Video Processor
(AVP)
UART
NFC
UART (GPS)
64-bit
L
R
Base-
band
BB I/F
Audio
RF
Memory
Controller
Flash
Controller
NOR
I2C
eDP x 4 or
Single Channel LVDS
DTV
SSD
13. Tegra K1 Technical Reference Manual
Introduction
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1.3 Memory Controller and Internal Bus Architecture
The Tegra K1 mobile processor has a highly optimized 64-bit memory controller, supporting low latency access for the CPU,
optimized high bandwidth access for the graphics and video devices, and controlled latency for real time devices such as
display.
There is a three-level hierarchy of memory clients:
1. Memory controller clients: The memory controller directly arbitrates between these using a complex algorithm
optimizing DRAM efficiency. The highest bandwidth clients all fall into this class, and they communicate directly with
the memory controller using a proprietary high-speed bus.
2. AHB devices: These generally have a built-in DMA engine, and share a single memory client using the AHB bus
protocol.
3. APB devices: All APB devices are slaves, and are serviced by a shared multi-channel APB DMA controller which is
also an APB device.
Special provisions are made for the CPU to bypass parts of the memory controller arbitration to help achieve a lower latency.
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Introduction
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1.4 Reading Register Tables
Every register table has an address line followed by a table containing the bit descriptions for that register. The address line
contains:
Offset: the address of the register within the specific module. Refer to the system memory map for the start address
of the module, and apply the offset at the top of the table to get the register address.
Read/Write: the register access type. When a register table contains the R/W column, individual bits within the
register will have different R/W properties. When there is no R/W column, all bits in that register have the same R/W
property.
Reset: gives the power-on reset value in 32-bit binary. A value of x implies that the register bit has an undefined
value at reset. A hexadecimal value is listed for convenience, where appropriate.
Default: only displayed if the default setting is different from the Reset value.
Unspecified bits may not appear in tables (see example below). Unspecified bits should be written with their Reset values,
while reads return an unknown value.
Address within the
module
Unspecified bits in this example
register: 31:26, 23:20, 15:10, 7:4
In the Reset field above the table,
most unspecified bits are shown as
‘x’ in binary format. In hex format,
unspecified bits within nibbles are
shown as 0 in the Reset field above
the table.
At power-on reset, write only the
provided reset value to unspecified
bits for proper operation. For
example, in the Reset field above
the table, bits [31:30], which are not
specified in the table, must be
written as 0s.
Register access type
Offset: 0x010 | Read/Write: R/W | Reset: 0x00040002(0b00xxxx00xxxx0100xxxxxx00xxxx0010) | Default: 0x00000000
Bit R/W Reset Description
25:24 RW N1 EMEM_NUMDEV
0 = N1
1 = N2
19:16 RO D64MB EMEM_DEVSIZE
0 = D4 MB
1 = D8 MB
2 = D16 MB
3 = D32 MB
4 = D64 MB
5 = D128 MB
6 = D256 MB
7 = D512 MB
9:8 RW W2 EMEM_BANKWIDTH
1 = W1
2 = W2
3 = W3
3:0 RO W9 EMEM_COLWIDTH
0 = W7
1 = W8
2 = W9
3 = W10
4 = W11
Default provided if different
from Reset
32-bit Power-on reset
value
15. Tegra K1 Technical Reference Manual
Introduction
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1.5 Glossary
This glossary is intended to cover the Tegra specific acronyms used in this document; along with some others related to the
ARM SOC world. Many acronyms in this document are in broad engineering use and are not documented here; we assume
you already know what USB and CPU are, for example.
Term Definition
ADX Audio Demultiplexer Block, part of the Audio Hub used to demultiplex multiple
audio streams.
AHB AMBA High-Speed Bus, a multi-master high-speed (relative to APB) bus
supporting arbitration and split transactions, defined as part of AMBA 2.
AHBSLVMEM The AHB slave used for the main memory interface. Acts as an AHB slave and
provides a path from there to main memory. Refer to the AHB section.
AMBA Advanced Microcontroller Bus Architecture, a set of standard buses defined by
ARM.
AMX Audio Multiplexer Block, part of the Audio Hub used to multiplex multiple audio
streams together.
APB AMBA Peripheral Bus, a simple 32-bit single master bus for peripheral devices.
APBDMA A multi-channel DMA controller for devices on the APB bus, performing DMA
between APB and AHB.
ARM Advanced RISC Machines, a company that licenses CPU IP to Tegra. Also:
Architecture Reference Manual, so the ARM defines the CPU architecture.
AVP Audio-Video Processor, the term used both to describe the ARM7 processor in
Tegra devices, and to describe the broader audio and video decode acceleration
hardware and RAM associated with the ARM7. Note that the AVP is sometimes
known as COP in legacy documentation and registers.
AXI AMBA Advanced eXtensible Interface, a more advanced bus than AHB defined as
part of AMBA 3.
BSEA Bit Stream Engine for Audio applications
CAR Clock and Reset module allows controlling clocks and resets to all the modules
and subsystems in the Tegra processor.
CEC Consumer Electronics Control, a part of the HDMI interface specification used for
sending device control commands, often from a remote control.
COP CO-Processor, an obsolete name for the AVP still present in legacy
documentation and registers.
CSI MIPI Camera Serial Interface, a standard high-speed serial interface for
connecting cameras to the Tegra processor.
DAM Digital Audio sample-rate conversion and Mixing block, a block within the Audio
Hub that performs audio mixing and sample rate conversion
DSI MIPI Display Serial Interface, a standard high-speed serial interface for
connecting displays to the Tegra processor.
DTV Digital TV input block, used to stream a serial TV transport stream of compressed
data into Tegra, using an SPI like protocol.
DVC Dynamic Voltage Controller module
eDP Embedded Display Port
EMC External Memory Controller, a module that interfaces with external DDR/LPDDR
devices.
GART Graphic Address Relocation Table, a now obsolete mechanism for mapping from
virtual to physical addresses for devices. Remains in Tegra only as an aperture to
memory that may be mapped though the SMMU, the replacement for the GART.
GPIO General Purpose Input/Output, an I/O signal uncommitted to a specific role and
controlled by software.
HDMI High-Definition Multimedia Interface, a digital connection carrying uncompressed
video and audio at high speed over a single connector.
HSI MIPI High-Speed Synchronous Interface, a standard high-speed serial interface
for bi-directional communications with baseband processors and other devices.
16. Tegra K1 Technical Reference Manual
Introduction
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Term Definition
IDE Integrated Drive Electronics (or Integrated Device Electronics)
ISP Image Signal Processor, a hardware engine that is part of the camera processing
pipeline.
KBC Keyboard Controller module allows the Tegra processor to be connected to
keyboard matrices of sizes up to 11x8.
LVDS Low Voltage Differential Signaling
MC Memory Controller module handles requests from internal clients and arbitrates
among them to allocate memory bandwidth.
MCCIF or
MC-CIF
Memory Controller Client InterFace, the standard interface block between the
memory controller sub-system fabric and the client device. Note that some
modules may have multiple client interfaces.
MIPI The Mobile Industry Processor Interface and industry alliance promoting a number
of standard interfaces for mobile devices.
MPCORE Multi-processor CPU core, a generic term for a CPU capable of operating as part
of an SMP group.
MPE An older name for the Video Encoder in the Tegra processor capable of encoding
raw video stream into MPEG. Now referred to as MSENC.
MSENC Multi-Standard video Encoder engine.
NAND A type of flash memory supporting high densities, and commonly used for non-
volatile mass storage in portable devices. Accessed in sequential blocks to be
generally treated as a file system.
NOR A type of flash memory, with a direct bus interface that allows random access so
code can be executed in place. Generally more costly and less dense than NAND
flash memory.
OGL Open Graphics Library, also known as OpenGL. An API supported on Tegra
devices and accelerated in hardware by dedicated 3D and 2D engines.
PCIe Peripheral Component Interconnect Express, a high-speed interface for external
devices connected to the Tegra SOC.
PMC Power Management Controller module controls the various power management
features in the system.
PPSB PortalPlayer System Bus, a proprietary register bus used for some blocks. Similar
to APB. PortalPlayer is a company that was acquired by NVIDIA, and from where
parts of Tegra are derived including this bus.
PWFM Pulse Width Frequency Modulation module generates programmed pulse widths
typically used to control backlight in display panels.
PVT Process, Voltage, & Temperature
RISC Reduced Instruction Set Computer, the CPU architecture used by ARM CPUs.
SATA Serial Advanced Technology Attachment (ATA)
SDMMC SD and MMC controller. An I/O controller supporting
SLINK Serial Link, a legacy and now obsolete name for the SPI controller
SMMU System Memory Management Unit, a block within the memory controller used to
map from a virtual address space to physical addresses for device DMA.
SMP Symmetric Multi-Processing
SOC System On a Chip, an integrated circuit containing a CPU, memory controller and
the peripheral devices needed for a computing system.
SOR Serial Output Resource. SOR is GPU IP for driving HDMI/DP/LVDS. It converts
the output of the display to a more modern high-speed serial protocol. DSI is not
included since it’s not GPU IP based
S/PDIF Sony/Philips Digital Interconnect Format
SPI Serial Peripheral Interface Bus, a synchronous serial data link, that operates in full
duplex mode.
TSEC Tegra Security co-processor, an embedded security processor used mainly to
manage the HDCP encryption and keys on the HDMI link.
TZ Trust Zone, a secure operating environment of the ARM CPU and the related
secure parts of the SOC backbone and devices
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Introduction
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Term Definition
TZRAM Trust Zone secured RAM on the SOC.
UCQ Unified Command Queue – a sub module within Video Decoder Engine
VCP2 Vector Co-Processor version 2, a hardware acceleration block for the signal
processing parts of audio decode and filtering. Use to offload the ARM7 AVP
during audio playback.
VDE Video Decode Engine, a Tegra hardware acceleration block dedicated to
decoding compressed video in various formats.
VI2 Video Input 2 block, the acronym used to describe the Tegra K1 block used for
camera and related input functions.
VIC Video Image Compositer, a Tegra K1 block that implements video post-
processing functions needed by a video playback application to produce the final
image for the player window.
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Introduction
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25. Tegra K1 Technical Reference Manual
Address Map
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2.2 Available DRAM Address Ranges
Table 2 describes the various address regions that are available as DRAM in Tegra
®
K1 devices.
The address map available varies by master, because MMIO is not available to any direct MC client except the processors.
These other direct MC clients are therefore able to access all DRAMs on 4GB systems, with the spaces reserved for MMIO on
the processors available to them as DRAM. This may be used as a carve-out or for similar purposes.
Note: MMIO in Table 2 below refers to the MMIO target, register, or non-DRAM region. Not all of
the MMIO regions actually have an MMIO target.
Physical/Virtual Address Range is available for Host1X clients for all apertures.
Table 2: DRAM Address Ranges
Aperture Range
Size
(MB)
H/W Config
Option
Physical DRAM Range
IOVA Range
Available for:
2 GB 3GB 4 GB >4 GB
COP/
AVP?
AHB
Clients?
DRAM 8000_0000 - FFFF_FFFF 2048 Always DRAM DRAM DRAM DRAM DRAM Yes Yes
DRAM2 1_0000_0000 - 2_7FFF_FFFF 6144 Always DRAM N/A N/A N/A DRAM No No
AHB_A2_rsvd 7E00_0000 - 7FFF_FFFF 32 Selectable DRAM+
DRAM+
DRAM DRAM+
Yes Yes
AHB_A2 7C00_0000 - 7DFF_FFFF 32 Always MMIO MMIO MMIO MMIO MMIO No No
AHB_A1_rsvd 7900_0000 - 7BFF_FFFF 48 Selectable DRAM
+
DRAM
+
DRAM DRAM
+
Yes Yes
AHB_A1 7800_0000 - 78FF_FFFF 16 Selectable MMIO MMIO MMIO MMIO No No
APB_rsvd 7100_0000 - 77FF_FFFF 112 Selectable DRAM
+
DRAM
+
DRAM DRAM
+
Yes Yes
APB 7000_0000 - 70FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
ExtIO_rsvd 6900_0000 - 6FFF_FFFF 112 Selectable DRAM+
DRAM+
DRAM DRAM+
Yes Yes
ExtIO 6800_0000 - 68FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
PPSB_rsvd 6100_0000 - 67FF_FFFF 112 Selectable DRAM
+
DRAM
+
DRAM DRAM
+
Yes Yes
PPSB 6000_0000 - 60FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
GART/GPU_GART 5700_0000 - 5FFF_FFFF 144 Always MMIO MMIO MMIO MMIO MMIO Yes Yes
Graphics Host rsvd
(HOST1X_DR_RSVD)
5500_0000 - 56FF_FFFF 32 Selectable DRAM
+
DRAM
+
DRAM DRAM
+
Yes Yes
Graphics Host
(HOST1X_DR)
5400_0000 - 54FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
Verif Aper + Rsvd 5100_0000 - 53FF_FFFF 48 Selectable DRAM
+
DRAM
+
DRAM DRAM
+
Yes Yes
Host1x+PERIPH
1
5000_0000 - 50FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO
Host1X+
PERIPH
Host1x 5000_0000 – 5002_7FFF 160KB Always MMIO MMIO MMIO MMIO MMIO No No
PERIPHBASE 5004_0000 - 5005_FFFF 128KB Always MMIO MMIO MMIO MMIO MMIO No Yes
MSELECT 5006_0000 - 5006_0FFF 4KB Always MMIO MMIO MMIO MMIO MMIO No Yes
NOR_A3 4B00_0000 - 4FFF_FFFF 80 Selectable
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
Yes if no
NOR.
Yes if no
NOR.
NOR_A2 4900_0000 - 4AFF_FFFF 32 Selectable
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
Yes if no
NOR.
Yes if no
NOR.
NOR_A1 4800_0000 - 48FF_FFFF 16 Selectable
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
Yes if no
NOR.
Yes if no
NOR.
IRAM_rsvd 4100_0000 - 47FF_FFFF 112 Selectable DRAM+ DRAM
+
DRAM DRAM
+
Yes Yes
1
The Host1X+PERIPH is split into multiple apertures.
26. Tegra K1 Technical Reference Manual
Address Map
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Aperture Range
Size
(MB)
H/W Config
Option
Physical DRAM Range
IOVA Range
Available for:
2 GB 3GB 4 GB >4 GB
COP/
AVP?
AHB
Clients?
IRAM 4000_0000 - 40FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
PCIE_A3 1000_0000 - 3FFF_FFFF 768 Selectable
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
Yes Yes
PCIE_A2 0200_0000 - 0FFF_FFFF 224 Selectable
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
Yes Yes
PCIE_A1 0100_0000 - 01FF_FFFF 16 Selectable
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
DRAM/
MMIO
Yes Yes
IROM_LOVEC 0000_0000 - 00FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
Notes:
The IOVA Range column is available for AVP or AHB clients that have SMMU translation enabled or PA address for
AHB clients that have SMMU translation disabled.
“DRAM” really means “Memory Controller”. In particular:
The GART range (5700_0000 – 5FFF_FFFF) has been used as an SMMU bounce range, which through the
SMMU points to DRAM.
If the system configuration includes a PCIe device, then the PCIE_A* regions need to be configured as MMIO
(appropriately as required by address space requirement). If the system does not include any PCIe devices, then
these regions should be configured as DRAM.
All configurable regions that do not have a real MMIO target (labeled as DRAM+) in the above table should be
configured as DRAM to provide the largest and uniform IOVA view (in 2GB or 4GB system) for the AVP and
other clients that generate virtual addresses to access DRAM.
Requests from all clients (except the main CPU) are allowed to use SMMU translation. Any request address range
that can reach the MC can be translated by the SMMU.
SMMU is a sub-unit in the memory controller. Address ranges marked as "No" in the table will not reach the memory
controller.
All Host1x clients can see the full 4GB physical or IOVA range.
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Address Map
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Clients/Controllers are logically (static) grouped in different SWNAME/SWID. SMMU translation can be enabled/disabled for
individual SWNAME. The following table gives the Client to SW Name mapping details.
Table 3: Client to SW Name Mapping
SW Group Client Description
AFI AFI PCIe reads
AVPC AVP Cache ARM7 Audio-Video Processor (AVP)
DC Display Display reads, window A, window C, window D, window T, cursor
DCB Displayb Display reads, window B, window C, cursor
GPU GPU Kepler GPU, 3D engine
HC Host1x Host interface
HDA HDA High-definition Audio engine
ISP2 ISP2 Image Signal Processor, instance a
ISP2B ISP2B Image Signal Processor, instance b
MPCORE AXICIF Cortex-A15 CPU cores, writes
MPCORELP AXICIF_LP Cortex-A15 Shadow CPU core, writes
MSENC MSENC Multi Standard Video Encoder
PPCS AHBDMA, AHBSLV Clients in the AHB cluster (ppcs2mc_swid=1'b0)
PPCS1 AHBDMA, AHBSLV Same as PPCS, ppcs2mc_swid=1'b0)
PPCS2 AHBDMA, AHBSLV Same as PPCS, ppcs2mc_swid=1'b0)
PTC MC (SMMU) Misses from SMMU PTC
SATA SATA Serial ATA
SDMMC1a SDMMCA SDMMC1
SDMMC2a SDMMCAA SDMMC2
SDMMC3a SDMMC SDMMC3
SDMMC4a SDMMCAB SDMMC4
TSEC TSEC Tegra Security coprocessor
VDE VDE Video Decode Engine
VI VI2 Video Input engine for CSI
VIC VIC Video Image Compositer
XUSB_HOST USB3 Host
Although the same driver is expected to control both units, each has its own SWNAME
XUSB_DEV USB3 Device
Note: Requests from all clients (except main CPU) are allowed to use SMMU translation. Any
request address range that can reach the MC can be translated by the SMMU.
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Address Map
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The clients behind AHBSLV in the above table are:
VCP
CSITE
ARC
AHBDMA
USB
APBDMA
SNOR
BSEV
SE
DDS
BSEA
USB2
MIPIHSI
Each client in the above list has a SWID register field which controls whether the client maps to PPCS or PPCS1 SWNAME.
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3.0 INTERRUPT CONTROLLER
This section provides the mapping and hierarchical groups of the Tegra
®
K1 family processor interrupts. It also describes the
architecture for routing and handling of these interrupts. It describes semaphores, which provide a mechanism for the
processors to arbitrate for the use of various resources.
From the perspective of interrupts: devices (GPU, Memory Controller, Video encode/decode engines, and various I/O devices)
are the sources of interrupts; and processors are the target of interrupts. From sources, interrupts go to interrupt controllers
which, based on configuration, prioritize and route them to the appropriate target processor. There are two different types of
interrupt controllers used in Tegra K1 devices: The ARM
®
vGIC and the Legacy Interrupt Controller (LIC).
Glossary and Acronyms
Acronym Description
COP Refers to ARM7™ AVP
CPU Unless specified otherwise, refers to CPU complex
FIQ Fast Interrupt Request
GIC Also known as vGIC, see below
IPI Inter Processor Interrupt
IRQ Interrupt Request
LIC Legacy Interrupt Controller (used for the ARM7 AVP)
MSI Message Signaled Interrupt
PPI Private Peripheral Interrupts
SGI Software Generated Interrupt
SMP Symmetric MultiProcessors
SPI Shared Peripheral Interrupts
vGIC Virtual GIC (also known as GICv2, part of the CPU complex)
WFE Wait For Event (an ARM instruction)
WFI Wait For Interrupt (an ARM instruction)
3.1 References
Some ARM documentation is required to fully understand the Tegra interrupt architecture. Refer to ARM’s website for further
details and to access these.
Document Description
vGIC Architecture ARM Virtual Generic Interrupt Controller (also known as GIC v2) Architectural Specification
Timers Architecture ARM Generic Timer Architectural Specification
Cortex-A15 TRM Cortex-A15 Technical Reference Manual for Cortex-A15 implementation specific information
(Tegra K1 32-bit).
ARM Technical Reference
Manual v8
For implementation specific information (Tegra K1 64-bit)
3.2 Interrupt Mapping
The following five tables show the mapping of the interrupts from system devices to the bit fields in the Tegra K1 interrupt
controllers.
Interrupts to the CPU’s embedded interrupt controller (vGIC) are in this same order, but start at offset 32 because the first 32
are reserved for the CPU’s internal interrupts.
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Table 4: Primary Interrupt Controller (PRI_ICTRL) Mapping
Global
Interrupt
Number
Interrupt
Target
LIC
Interrupt
Number Interrupt Name
Source
Block Interrupt Description
Interrupt
Order
31 31 SDMMC4 SDMMC SDMMC4 Controller 0
30 30 OWR OWR OWR Interrupt 0
29 CPU 29 ARB_SEM_GNT_CPU Semaphore GNT.0 Arbitration Grant Status of CPU 0
28 COP 28 ARB_SEM_GNT_COP Semaphore GNT.1 Arbitration Grant Status of COP 0
27 CPU 27 AHB_DMA_CPU AHB_DMA AHB DMA Controller (CPU) 0
26 CPU 26 APB_DMA_CPU APB_DMA APB Bridge DMA Controller (CPU) 0
25 25 VCP VCP VCP 0
24 24 Unmapped Unassigned 0
23 23 SATA_CTL SATA SATA Controller Interrupt 0
22 22 Unmapped Unassigned 0
21 21 USB2 USB USB Device 0
20 20 USB USB USB Device 0
19 19 SDMMC3 SDMMC SDMMC3 Controller 0
18 18 AVP_UCQ AVP_UCQ AVP UCQ Interrupt 0
17 17 VDE VDE VDE Interrupt 0
16 16 Unmapped Unassigned 0
15 15 SDMMC2 SDMMC SDMMC2 Controller 0
14 14 SDMMC1 SDMMC SDMMC1 Controller 0
13 13 SATA_RX_STAT SATA SATA RX Wake Up Interrupt 1
12 12 VDE_SXE VDE VDE SXE Interrupt 3
11 11 VDE_BSEA VDE AVP BSEA Interrupt 0
10 10 VDE_BSEV VDE VDE BSE-V Interrupt 1
9 9 VDE_SYNC_TOKEN VDE VDE Sync Token Interrupt 0
8 8 VDE_UCQ VDE VDE UCQ Error Interrupt 4
7 CPU 7
SHR_SEM_OUTBOX_
EMPTY Semaphore CPU Outbox Empty Interrupt 3
6 COP 6 SHR_SEM_OUTBOX_FULL Semaphore COP Outbox Full Interrupt 2
5 COP 5 SHR_SEM_INBOX_EMPTY Semaphore COP Inbox Empty Interrupt 1
4 CPU 4 SHR_SEM_INBOX_FULL Semaphore CPU Inbox Full Interrupt 0
3 3 CEC CEC CEC General Interrupt 0
2 2 RTC RTC RTC Interrupt 0
1 1 TMR2 Timer TMR2 Interrupt 0
0 0 TMR1 Timer TMR1 Interrupt 0
Table 5: Secondary Interrupt Controller (SEC_ICTLR) Mapping
Global
Interrupt
Number
Interrupt
Target
LIC
Interrupt
Number Interrupt Name Source Block Interrupt Description
Interrupt
Order
63 31 I2C6 I2C I2C6 Interrupt 0
62 30 CLDVFS CL-DVFS Close Loop DVFS control logic 0
61 COP 29 AHB_DMA_COP AHB_DMA AHB-DMA Interrupt (COP) 1
60 COP 28 APB_DMA_COP APB_DMA APB-DMA Interrupt (COP) 1
59 27 SPI1 SPI SPI Controller (SBC1) 0
58 26 SE SE SE and TZRAM General Interrupt 0
57 25 USB3_DEV_PME USB3 USB3_DEV_PME 0
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Global
Interrupt
Number
Interrupt
Target
LIC
Interrupt
Number Interrupt Name
Source
Block Interrupt Description
Interrupt
Order
138 10 APB_DMA_CH26 APB_DMA APB-DMA Channel 26 0
137 9 APB_DMA_CH25 APB_DMA APB-DMA Channel 25 0
136 8 APB_DMA_CH24 APB_DMA APB-DMA Channel 24 0
135 7 APB_DMA_CH23 APB_DMA APB-DMA Channel 23 0
134 6 APB_DMA_CH22 APB_DMA APB-DMA Channel 22 0
133 5 APB_DMA_CH21 APB_DMA APB-DMA Channel 21 0
132 4 APB_DMA_CH20 APB_DMA APB-DMA Channel 20 0
131 3 APB_DMA_CH19 APB_DMA APB-DMA Channel 19 0
130 2 APB_DMA_CH18 APB_DMA APB-DMA Channel 18 0
129 1 APB_DMA_CH17 APB_DMA APB-DMA Channel 17 0
128 0 APB_DMA_CH16 APB_DMA APB-DMA Channel 16 0
3.3 Hierarchical Groups
The following table is a hierarchical interrupt grouping which generates interrupts for the first level of interrupt controllers.
Table 9: Hierarchical Interrupt Grouping
Hierarchical Interrupt
Controller Name
Interrupt
Number Interrupt Name Source Block Interrupt Description
HIER_GROUP1 31 - 16 Currently Unmapped Currently Unassigned
HIER_GROUP1 15 MselectError Unassigned
HIER_GROUP1 14 MPCORE_CTIIRQ3 CPU3 CTI interrupt
HIER_GROUP1 13 MPCORE_CTIIRQ2 CPU2 CTI interrupt
HIER_GROUP1 12 MPCORE_CTIIRQ1 CPU1 CTI interrupt
HIER_GROUP1 11 MPCORE_CTIIRQ0 CPU0 CTI interrupt
HIER_GROUP1 10 TMR_SHARED Timer TMR_SHARED interrupt
HIER_GROUP1 9 FLOW_RSM_COP FlowCtlr FLOW - RSM1 Resume for COP or COP1
HIER_GROUP1 8 FLOW_RSM_CPU FlowCtlr FLOW - RSM0 Resume for CPU
HIER_GROUP1 7 Currently Unmapped Currently Unassigned
HIER_GROUP1 6 Currently Unmapped Currently Unassigned
HIER_GROUP1 5 EVENT_GPIO_D GPIO (External) Event Detector GPIO Port D
HIER_GROUP1 4 EVENT_GPIO_C GPIO (External) Event Detector GPIO Port C
HIER_GROUP1 3 EVENT_GPIO_B GPIO (External) Event Detector GPIO Port B
HIER_GROUP1 2 EVENT_GPIO_A GPIO (External) Event Detector GPIO Port A
HIER_GROUP1 1 MPCORE_INTERRIRQ CCPLEX CPU INTERRIRQ
HIER_GROUP1 0 MPCORE_AXIERRIRQ CCPLEX CPU AXIERRIRQ
3.4 Functional Description
3.4.1 Interrupt Handling Mechanism
The two different types of interrupt controllers (vGIC, and LIC) receive interrupts from devices (i.e., hardware interrupts also
known as SPIs) or processors (i.e., software interrupts including IPI), arbitrate them, and send them to the appropriate target
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processor(s). From an interrupt perspective, there are two different types of processors: CPUs (Cortex-A15) and COP (ARM7
AVP). The vGIC is the interrupt controller for the CPUs, and the LIC is the interrupt controller for the ARM7 AVP. Any
processor can initiate a software interrupt, targeted to any one or more processors (including itself). However, IPIs can only be
initiated by a Cortex-A15 CPU to any one or more Cortex-A15 CPUs (including itself).
There are 160 hardware interrupts in Tegra K1 devices. Interrupt sources are allocated one or more interrupts as required.
The 160 interrupts are grouped into slices of 32, where each slice can be configured independently.
3.4.1.1 ARM Processors’ IRQ and FIQ
ARM processors (Cortex-A15, and ARM7) each have two input pins to receive two different types of interrupts. These
interrupts are called IRQ (Interrupt Request) and FIQ (Fast Interrupt Request). The interrupts are implemented as active-low
pins on the ARM processor input; thus the processor pins are named nIRQ and nFIQ.
The ARM processor goes into the IRQ mode or the FIQ mode depending up on which interrupt is activated. Generally,
interrupts that require low latency or are time critical are configured as FIQ. All other interrupts are configured as IRQ. Non-
secure interrupts can only be IRQ.
3.4.1.2 Interrupt Controllers
The interrupt controller receives interrupts from a large number of sources. The interrupt sources can be assigned a target
processor, a type (IRQ versus FIQ), priority levels, etc., by configuring interrupt-controller registers. The interrupt controller
arbitrates among different incoming interrupts and sends the interrupt to the nIRQ or nFIQ pin of the targeted processor.
In general, any incoming hardware interrupt can be routed to either nIRQ or nFIQ pin of any of the processors.
The Legacy Interrupt Controller (LIC) is primarily used for COP (ARM7). But it is also used for generating interrupts as wake
events for CPUs. All of the device hardware interrupt signals are sent to the LIC first, which routes them to the ARM7 AVP as
well as forwards them to other interrupt controller. The LIC also provides a software set/clear mechanism for all of the
interrupts.
The interrupt controller used for CPUs (Cortex-A15 CPUs) is called vGIC (virtual generic interrupt controller). The vGIC is an
SMP interrupt controller. It receives interrupts targeted to any one or more of the CPUs in the SMP complex. There is one
vGIC per CPU cluster.
3.4.1.3 vGIC Interrupt Sources
The vGIC supports 256 interrupts. All interrupts are identified by a unique ID. There are three types of interrupt sources for the
vGIC: SGIs, PPIs, and SPIs.
Software Generated Interrupts (SGIs)
SGIs are software interrupts which are generated by writing to a vGIC register. Software can generate a maximum of 16 SGIs,
with ID0-15. The SGIs are also referred to as IPIs (Inter Processor Interrupts).
Private Peripheral Interrupts (PPIs)
PPIs are interrupts generated by a peripheral that is specific to a single processor.
There are seven PPIs for each CPU: virtual maintenance interrupt (ID25), hypervisor timer interrupt (ID26), virtual timer
interrupt (ID27), legacy nFIQ (ID28), secure physical timer interrupt (ID29), non-secure physical timer interrupt (ID30), and
legacy nIRQ (ID31).
Tegra K1 devices use all PPIs except for the legacy nFIQ and legacy nIRQ.