The Statistical Package provides applications that utilize a systematic True Corner-based design methodology to account for process variation effects. It can analyze designs to identify failures and determine a set of True Corners. It also analyzes mismatch effects and allows running Monte Carlo simulations or verifying high-sigma designs. This provides accurate analysis of process variations to help designers identify and address problems.

1. Statistical Package
Product Benefits:
• Accurate and fast Analyze,
Identify and Fix flow to solve
process variation issues
The applications in the Statistical Package utilize a systematic and consistent True • Design-specific True Corners
Corner-based design methodology. The applications in this package extend the account for global, local, and
familiar digital corner-based design methodology to account for process variation environmental variation
effects. True Corners account for global, local (mismatch) and environmental
variations for a specific design, and accurately represent
the manufacturing and operating variance that a design
is subjected to. Inability to account for design-specific True
Corners can lead to over or under-design. 0.20
Under
Design
Variation Designer and the Statistical applications provides 0.15
an efficient way for chip designers to analyze, identify and fix
Gain Factor (dB)
the effects of process variations on their designs. It provides ss
0.10
automatic capabilities to analyze and identify process variation-
related failure mechanisms, but cedes control to designers to
ff
use the information in combination with their experience and 0.05
Over
knowledge to fix those problems in an interactive manner. Design
0.00
150 200 250 300 350 400 450 500
Bandwidth (MHz)
Monte Carlo Digital Corners Nominal
Applications Description and Benefit Over or Under Design
• Analyzes the design to find failures and a
Discover True set of True Corners
Accuracy
51
Corners • Enables an accurate, efficient, corner- 50
based design flow 49
Variation Designer
SFDR
48
• Analyzes mismatch effects of specific
Statistical Package
47
Analyze devices on design performance 46 Monte Carlo
Mismatch • Quickly and accurately identifies design 45
74 75 76 77 78 79 80 81
loss due to device mismatch Phase Margin
• Generates Monte Carlo or Latin 51
Run Monte Hypercube results with rich visualizations 50
Carlo • Provides detailed information about 49
sf
design loss caused by statistical variation 48
ss tt
SFDR
47
fs ff
• Efficiently calculates the yield of high- 46
Digital Corners
Verify High- sigma designs 45
74 75 76 77 78 79 80 81
Sigma Design • Typically 10-1000x faster than Monte Phase Margin
Carlo for designs with yield > 99.9%
Speed
Monte Carlo accuracy in Digital Corner time
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