Nios II Architecture

1. Embedded Systems
using reconfigurable architecture

2. References
 Book:
1. Introduction to Embedded Systems
 Shibu K V
2. Introduction to Embedded System Design using FPGAs
 Rahul Dubey
3. Hardware/software codesign for Data Flow Dominated
Embedded Systems
 Ralf Niemann
 Thesis:
1. A Bayesian Belief Network Approach to Codesign
 Amelia Wong Azman
 Website:
1. Nios ii Handbook
 Altera

3. Nios II Processor
 The Nios II architecture describes an instruction set
architecture (ISA). The ISA in turn necessitates a set of
functional units that implement the instructions.
 A Nios II processor core is a hardware design that
implements the Nios II instruction set and supports the
functional units described in this document.
 The processor core does not include peripherals or the
connection logic to the outside world.

4. Nios II Architecture
 The Nios II architecture defines the following functional
units:
• Register file
• Arithmetic logic unit (ALU)
• Interface to custom instruction logic
• Exception controller
• Internal or external interrupt controller
• Instruction bus
• Data bus
• Memory management unit (MMU)
• Memory protection unit (MPU)
• Instruction and data cache memories
• Tightly-coupled memory interfaces for instructions and data
• JTAG debug module

6. Register File
 thirty-two 32-bit general-purpose integer registers, and
up to thirty-two 32-bit control registers

7. ALU
 operates on data stored in general-purpose registers
 ALU operations take one or two inputs from registers,
and store a result back in a register

8. Qsys Output Files
 Qsys Design File (.qsys)—Contains the hardware
contents of the Qsys system.
 SOPC Information File (.sopcinfo)—Contains a
description of the contents of the .qsys file in
Extensible Markup Language File (.xml) format. The
Nios II EDS uses the .sopcinfo file to create software for
the target hardware.
 Hardware description language (HDL) files—Are the
hardware design files that describe the Qsys system.
The Quartus II software uses the HDL files to compile
the overall FPGA design into an SRAM Object File (.sof).

9. Hello world on Nios II