Anand Goyal has over 10 years of experience in RTL design and verification. He received his B.Tech in Electronics Engineering from Banaras Hindu University, where he graduated first in his class. He is currently a Senior Member of Technical Staff at Mentor Graphics, where he guides trainees and works on RTL modeling, verification, and issue fixing. Previously he held internships at Wipro Technologies and Mentor Graphics, where he developed simulation and modeling tools.

1. ANAND GOYAL
Senior Member Technical Staff Phone : +91-9971365995
RTL Compiler Group, Mail : anand.goyal88@gmail.com
Mentor Graphics, Noida
Academic Record:
Class Year of Institute/ School DGPA/ Rank
Passing Percentage
B.Tech (Electronics 2010 Institute of Technology, Banaras Hindu 9.20 1st
Engineering) University
Intermediate(C.B.S.E.) 2006 Rajkamal Saraswati Vidya Mandir, 91 % 1st
High School(C.B.S.E.) 2004 Dhanbad 91 % 1st
*DGPA : Department Grade Point Average (on absolute scale)
Professional Experience:
1.) Senior Member Technical Staff, RTL Compiler Group June ,10-Current
Mentor Graphics India Pvt. Ltd., Noida
RTL Compiler Group (Mentor Emulation Division) is working for the front end compiler for
emulation flow. Key responsibilities include:
 Design Ware modeling: Writing optimized synthesizable model (Verilog/VHDL) using RTL
Simulation models and also guiding trainees in this area.
 Miscellaneous development and enhancement (in C/C++), verification
(simulation/formal) and issue fixings related to RTL Compiler.
Awards and activities:
 Promoted to Senior Member Technical Staff within one year of service.
 Awarded Spot Bonus for guiding trainees for optimal Design Ware modelling.
 Conducted HDL Code Contest during Induction Training Program–2011 of Mentor Graphics.
 Attended Intensive Core C++ training by David Smallberg, Tenured Lecturer, UCLA.
2.) Technical Intern, RTL Compiler Group May-June, 09
Mentor Graphics India Pvt. Ltd., Noida
 Design Ware modeling: Worked on many (more than 30) Design Ware components to have
there optimized synthesizable model.
 Setting up of many designs (more than 50) in formal verification environment for RTL
Compiler’s Regression to ensure complete coverage.
 Expert validation in RTL compiler in the area of constant propagation and defparam
construct of Verilog.

2. 3.) Technical Intern, Telecom Equipment Group May-June, 08
Wipro Technologies, Bangalore
 Development of a Java based Simulator Platform in which different Routing Algorithms can
be simulated. This program provides a GUI developed in Java to define the network topology
and capable of determining the shortest path spanning tree and multicast tree (in accordance
with routing algorithm).
 Simulation of Dijkstra Algorithm and Distance Vector Algorithm.
 Development and Simulation of algorithm for Provider Link State Bridging (PLSB).
Software Skills:-
Programming Languages C, C++, Java (basics)
Hardware Description Languages Verilog, System Verilog, VHDL
EDA Tools RTL Compiler, QuestaSim, FormalPro
Scripting Linux Shell Scripting
Operating System MS Windows, Linux, Unix
Academic Project Works :
 Developed “Internet Controlled Robot ” as my B.Tech Project.This Robot is a multi functional
mobile device which can be controlled remotely in real time through the Internet by pressing
appropriate buttons on its webpage. A unidirectional video and audio link aid the user in its
navigation.
 Developed a “Simulation program in C++ for implementing Boolean expression using 4:1
Multiplexer”. This program provides a GUI for user interface and was able to generate equivalent
multiplexer circuit for any four variable mean term Boolean expressions.
Scholastic Achievements:
 Institute topper in B.Tech.
 Awarded BHU Alumni Association, Mumbai Scholarship, 2009-10.
 Awarded Scholarship for two consecutive years under Student Welfare Fund Scheme by
BHU for securing 1st Rank in Institute in B.Tech Part III and B.Tech Part II Examination
respectively.
 Awarded Merit Certificate and BHU Merit Scholarship for two consecutive years for securing
1st Rank in Department in B.Tech Part III and B.Tech Part II Examination respectively.
 Awarded Ruxmaniben Gardi Scholarship, 2008-09 by BHU Alumni, Mumbai.
 Awarded Prof. G.N Tripathi Scholarship, 2006-07 by BHU.
 Awarded Branch change from Mechanical Engineering to Electronics Engineering.
 Cleared IIT-JEE 2006 in first attempt and secured All India rank of 3126.
 Cleared JCECE (Jharkhand Combined Entrance Competitive Examination) 2006 in first
attempt and secured All India Rank 12.
 Awarded by Chief Minister of Jharkhand for securing 1st position in AISSCE-2006, CBSE
among all the students of VIDHYA BHARTI in JHARKHAND.

3.  Awarded Certificate of Merit for being placed in national top 1% in National Standard
Examination in Physics 2005-06 (NSEP 05-06), conducted by Indian Association of
Physics Teachers and Homi Bhabha Center for Science Education.
 Mathematics contest winner in Ranchi, Jharkhand Mathematics contest-2004, conducted
by Chottanagpur Mathematical society (CMS).
 School topper in Intermediate and High School.
 Obtained 95% and 98% marks in PCM in 12th and 10th respectively and was also eligible for
CBSE merit scholarship – 2006.
 Awarded Merit Certificate in science and technology, by CBSE for AISSE-2004.
Co-curricular Activities and Achievements:-
 Won 1st Prize in „Hardware Written Contest - 2009’ and „Hardware Written Contest - 2008’
organized by Department of Electronics Engineering, IT BHU.
 Won 1st Prize in „Electronics Quiz’, an event of Magnum Opus 2009, the Techno-
Management fest of IT BHU.
 Member of the Winning team in KHO-KHO in Mentor Mahayudh-2010, organised by Mentor
Graphics India Pvt. Ltd.
 Member of the Runner-up team in Matka Painting organised by Mentor Graphics India Pvt.
Ltd.
 Presented a paper on “Carrier Ethernet” at Papyrus, the paper presentation competition of
Technex-08.
 Was Event Co-ordinator for two different events in Magnum Opus 2009.
 Was Member of Hospitality team in SPARDHA-09.
 Was Member of Technical Wing, Electronics Engineering Society, IT BHU.
 Was Member of Mechanical Engineering Society of IT BHU.
 Was Member of The Institution of Engineers (India), Varanasi, IT-BHU, Students Chapter.
 Attended VLSI Conference – 2012, Hyderabad.