1. IF signal processing and Spectrum Analyzer on Sage UCTT
Renshou Dai
July 25, 2003
1 Introduction
This document describes the IF (Intermediate-Frequency) signal management and processing pro-
cedures implemented on Sage’s RF-DSP board. This RF-DSP board is one of the key building
blocks of the UCTT (Universal- Cellular (PCS)-Test-Tool) product.
The spectrum analyzer feature is included here to serve as an example in demonstrating how an
application module is interfaced with the IF data stream.
Unlike the DS1-DSP board [1], where two continuous DS1 data streams are processed in real-time,
the IF data stream here is processed in a capture-and-analyze manner. The capturing and analysis
steps are pipelined so that the application module has better real-time response to external test
signal. But no matter how fast the response appears to be, this RF-DSP board was not designed
to handle continuous IF stream in real-time fashion. To a large extent, the complexities associated
with the McBSP, EDMA and circular buffering on the DS1-DSP board are gone. The complexities
here come from the fact that, first, different applications require different sampling rates, hence
an efficient poly-phase-based sampling rate adaptor is needed for almost all DSP applications,
secondly, some applications (such as wide-band spectrum analyzer and fault location) require the
IF data capturing to be synchronized with the RF-front-end tuning, thirdly, frequency-dependent
(and even time-dependent) equalizations are required to face the analog RF hardware realities.
2 Overview
From signal processing point of view, this RF-DSP board consists of the following key devices:
1. High-speed (60MHz) 14-bit ADC for digitizing the incoming IF signal from the RF board,
and a high-speed (60 MHz) 14-bit DAC for transmitting the digitally generated IF signal to
the RF board. The 60 MHz clock comes from the RF front-end board. The incoming IF
signal is “centered” at 10 MHz with a bandwidth of 5 MHz. The outgoing IF signal is also
centered at 10 MHz with 5 MHz bandwidth.
2. Xilinx’s FPGA (named PLD in Figure 1) that handles the the data stream from ADC and
the data stream to DAC. A portion of the PLD is also clocked by the 60 MHz sampling clock
from the RF front-end board.
3. Sampling SRAM used by PLD to temporarily store the captured data stream from ADC
1

2. PLD
ADC
DAC
Tx IF centered at 10 MHzTo RF board
60 MHz sampling clock from RF board
Rx IF centered at 10 MHz
In from RF board
Upper RAM for Rx
Lower RAM for Tx and Rx
QDMA
McBSP/SPI
DSP-CPU
SPI control interface to RF board
PLD control
RAM data access
SDRAM
Interrupt
Figure 1: A simplified block diagram of the RF-DSP board. More detailed circuit
diagrams are available from Dave Morris and Mike Groh.
(upper and lower SRAM). The lower SRAM is also used by DSP to hold the transmitted
signal. More details are available in document [2].
4. TI’s C6711/C6713 DSP processor that controls the PLD and executes the signal processing
algorithms.
5. SDRAM is the DSP’s main external memory for both data and programs. The data movement
between SRAM and SDRAM is handled by the QDMA (Quick-DMA) of the DSP processor.
6. SPI (Serial-Protocol-Interface) that controls the RF front-end board. The SPI is derived from
the McBSP (Multi-channel-Buffered-Serial-Port) of the DSP processor. Details on the SPI
interface at the RF board side can be found in document [3].
The C-programs for managing the above devices are contained in the “RFIO.C” file.
2.1 Capturing the IF signal
In Figure 1, the ADC is continuously digitizing the incoming IF signal as long as the 60 MHz
sampling clock is available. But when to start collecting the samples is controlled by the DSP
through the PLD.
When the DSP needs N number of data samples, it calculates an SRAM address offset (or starting
address in SRAM) based on N and programs the starting address into the PLD. Then it writes a
1-bit to the “START ADC SAMP” bit-field of the PLD control register, and the PLD will start
capturing the data with fixed delay as described in [2]. The captured data is stored in the SRAM.
Once it finishes capturing the desired number of samples, the PLD interrupts the DSP-CPU. Upon
serving the interrupt, the DSP-CPU will initiate a QDMA request to move the captured data from
SRAM to DSP’s “own” external memory SDRAM space. Application modules can then start the
next capturing process (pipelining), and meanwhile starts processing the just-captured data stream.
2

3. In terms of C-programs, the following functions inside “RFIO.C” file controls the IF signal receiving
operations:
void RFIO_init(void);
void RFIN_start(void);
void RFIN_setiqsigsz(Int32 sig_sz);
Int32 RFIN_getsig(F32 *sig, Int32 sig_sz, Int32 ifc);
void SRAM_setup(SRAM_Mode mode, Int32 sz);
2.2 Transmit IF signal
To transmit IF signal, the DSP-CPU first generates the 60MHz sampled and 10MHz-centered IF
signal for at least a whole period of the signal. The DSP then places the data into the lower SRAM
through PLD, and then turn on the “START XDAC” bit-field of the PLD control register. The
PLD will start clocking out the data onto the DAC [2]. After reaching the last data sample, the
PLD will restart at the beginning again automatically. This means that the PLD is repetitively
sending the same block of signal whose period is the data length. So, the RF-DSP board can only
generate strictly periodic signal, and the signal is generated in non-real-time fashion. The maximum
period is constrained by the size of SRAM memory. Presently, the upper limit is about 8 ms. The
future hardware modifications will enlarge the size to at east 30 ms (so as to cover the 26.6667 ms
CDMA signal period). As in the receive side, the signal period (record length) information is used
to calculate the starting SRAM address, from which the transmitted signal will be stored.
The following C-functions handle the IF signal transmission.
void RFIO_init(void);
void RFOUT_start(F32 *sig, Int32 sz);
void RFOUT_stop(void);
void SRAM_setup(SRAM_Mode mode, Int32 sz);
2.3 SPI control of the RF front-end board
Before data acquisition or transmission can occur, the RF front-end must be set in a proper mode.
The SPI control to the RF front-end is operated through the McBSP0 port. The DSP’s McBSP
can be programmed to operate in a protocol that is compliant with the SPI protocol. Detailed
descriptions can be found in TI’s peripheral document [4]. Simply speaking, the McBSP’s PCR,
XCR, SPCR and DXR registers need to be loaded with some “special” values (look at the SPI init()
and SPI write() functions. Once set correctly, the McBSP will generate the correct framing pulse,
clocks and data pulses that the RF front-end devices need [3].
Two details are worth mentioning, first of all, the McBSP must work in the so-called clock-stop
mode for compliance with SPI (through the CLKSTP fields of the SPCR register). The data clock
rate needs to be low enough to work with RF front-end’s low-pass emission-protection filters.
The SRGR (sampling rate generator) of the McBSP is used to generate a clock output signal.
Ideally, the SRGR can use the internal DSP-CPU clock as input, and then divide the CPU clock
to a reasonable clock rate that is compatible with the SPI protocol. Unfortunately, the DSP-CPU
clock is a bit too high, and the SRGR dividing ratio is not big enough (only 8-bit). To solve this
3

4. problem, the TIMER0 output (TOUT) has been connected to the CLKS of McBSP0 as an input
clock source. The TIMER0 has been programmed to generate a clock output of 100KHz. That is
to say, the SPI bus is operating at a data rate of 100Kbps.
From software point of view, the front-end needs the following tuning processes:
1. Frequency and filter selection. The frequency of the first LO needs to be set to a correct
value when the user (through host) wants to analyze a portion of signal centered at some
known RF frequency. Associated with the center frequency is also a filter band selector. The
detailed register value calculations are described in [3]. More on frequency tuning later from
algorithmic point of view.
2. Receive path attenuator and amplifier control.
3. Transmit path source level gain control. The source level control register operates differently
from the rest of the control registers. Therefore, the source level is encapsulated separately.
The following functions implement the SPI communications with the RF front-end:
void SPI_init(void);
Int32 RF_tuning(Uint32 Fc);
void RF_gainctrl(Int32 rfdb, F32 ifdb, Int32 preamp);
void RF_sourcectrl(Uint32 srclvl);
void SPI_write(Uint32 reg, Uint32 addr);
2.3.1 Program the LO synthesizer, RF gain and filter selection registers
To program the front-end LO synthesizers (LO1, LO2 and LO3), RF gain/attenuation selection
and the band-selection filter control registers, the following C-function is called:
void SPI_write(Uint32 reg, Uint32 addr)
{
PLD_SPI=(addr<<16); //Register address selection via PLD_SPI control register.
McBSP0_PCR=0xa08; //PCR register of McBSP value, FSXP=1, frame sync pulse
//active low, CLKXM=1, CLKX is an output driven by SRGR,
//FSXM=1, frame sync generation by SRGR.
McBSP0_XCR=0x50080; //XWDLEN1=100b, 24-bits per frame transfer,
//XDATDLY=1, per TI requirement, XFIG=1, ignore unexpected
//frame pulse.
McBSP0_SPCR=0xc11800; //CLKSTP=11b, clock delayed by half-bit,
//XRST=1,enable serial port, FRST=1, GRST=1 for
//generating FSX from SRGR.
McBSP0_DXR=reg; //Send data bits out
DSP_pause(4); //Pause for 4 ms to make sure the bits are really
//out and the front-end stabilizes.
}
In essence, the above register values were designed to create the clock, data and framing timing
diagram shown in Figure 2.
4

5. B23 B22 B21 B1 B0
CLKX
DX
FSX
PLD_SPI_ADDR REG_SEL, 5-bits
SCLK
SDATA_IN
SLE
LO synthesizer, RF gain and filter selection registers programming
Figure 2: Clock, data and frame timing diagram for programming the RF LO, gain and
filter-selection registers. The notations at the left (CLKX, DX, FSX) are signals
from the DSP. The notations at the right are used in the RF document [3]. Key
things to notice: the rising edge of the FSX at the right serves as the SLE (Serial-
Latch-Enable) signal. The rising edge of the clock signal is delayed half-bit from
the rising edge of the data bit to meet the RF-board requirements. The RF-board
requires at most 20 bits, but the DSP is programmed to always output 24 bits. The
useful bits are the last 20 bits (B19 to B0). The first few bits are naturally ignored.
In programming, the useful bits are stored in the LSBs of a 32-bit word.
2.3.2 Program the 3rd IF gain and source level control registers
The RF-board requires slightly different timing diagram [3] when programming the 3rd IF gain
and source signal level control registers. To accommodate the differences, the following C-function
is designed:
void RF_sourcectrl(Uint32 srclvl)
{
srclvl&=0xfff;
if(srclvl!=SRC_STATE){ //program enabled only in the desired source level
//is different from the current one.
SRC_STATE=srclvl;
PLD_SPI=(0x1f0000); //Register (address) selection
McBSP0_PCR=0xa08; //Same as above
McBSP0_XCR=0x50080; //Same as above
McBSP0_SPCR=0xc11000; //CLKSTP=10b, no clock delay.
McBSP0_DXR=(srclvl<<8); //useful bits are the first 16-bits
DSP_pause(2);
}
}
The above C-function was designed to create the clock, data and frame timing diagram as shown
in Figure 3.
2.4 PLD interrupt and QDMA data transfer
After collecting the last data sample, the PLD interrupts the DSP-CPU (through EXT INT5). In
the interrupt service routine, the DSP programs the PLD to stop collection, put it in the DSP-read
5

6. B23 B22 B21 B1 B0
CLKX
DX
FSX
PLD_SPI_ADDR REG_SEL, 5-bits
SCLK
SDATA_IN
SLE
3rd IF gain and source level control registers programming
Figure 3: Clock, data and frame timing diagram for programming the 3rd IF gain
and source level control registers. Key things to notice: the falling edge of the
FSX at the left serves as the SLE (Serial-Latch-Enable) signal. The rising edge of
the clock signal coincides with the rising edge of the data bit to meet the RF-board
requirements. The RF-board requires 16 bits, but the DSP is programmed to always
output 24 bits. The useful bits are the first 16 bits (B23 to B8). The last 8 bits are
naturally ignored. In programming, the useful bits are originally stored in the 16
LSBs of a 32-bit word, and then left-shifted by 8 bits.
mode. Then it issues a QDMA transfer request to move that data from SRAM to SDRAM. Notice
that the EDMA has an element counter of 16-bit long. So, each QDMA request can only transfer
up to 65536 samples. In case when more samples need to be transfered, the DSP-CPU has to issue
more transfer requests. This logic is implemented inside the following function:
static void interrupt WBRF_getdata(void);
The main reason for moving data from SRAM to SDRAM is that the DSP-CPU’s access to SDRAM
is faster than SRAM. Secondly, this allows the capturing-analyzing pipelining. Right before the
DSP-CPU starts analyzing the current data stream, it requests the PLD to start capturing a new
block of data into the SRAM (SRAM is being used again). The QDMA data transfer between
SRAM and SDRAM relieves the burden from the DSP-CPU.
3 IF to base-band conversion and decimation
The IF signal from the RF front-end has a useful bandwidth of 5 MHz. 60 MHz is over-sampling,
from DSP point of view. To reduce the data rate, the IF signal needs to be down-converted to
baseband and decimated to a sampling rate of 10 MHz before the data go to any DSP application.
Figure 4 shows the signal flow diagram. This IF processing (down-conversion and decimation) is
performed as part of the data stream handling module implemented in the function IQconv dec6(..)
inside the RFIO.C file.
3.1 Down-conversion
Down-conversion can be simply described by the following equation:
z(n) = x(n) × ejnω
, n = 0, 1, 2, . . .
6

7. 60MHz
sampled,
10MHz
centered,
5MHz wide
IF signal in
SDRAM
Poly-
phase
Lowpass
filter
with
sampling
rate of
60MHz
and cutoff
at 5MHz
Decimate
by 6
10MHz sampled,
base-band
complex (I,Q)
signals to
all DSP
measurement
application
modules
cos(n*w)
+sin(n*w)_
I(n)
Q(n)
Figure 4: IF signal processing flow diagram. The 60MHz sampled, 10MHz centered IF
signal is down-converted to base-band complex signals (I,Q) and decimated by 6 to
10MHz sampling rate.
where ω is the normalized (by sampling rate) angular frequency. More specifically:
ω = π ×
±107 − δf
3 × 107
The sign of ±107 depends on whether it is tuned to PCS band or cellular band. The δf accounts for
the residual deviation from the ideal 10 MHz IF center frequency due to the fact that the current
RF front-end prototype can only achieve discrete tuning steps.
When tuned to the PCS band (> 1400MHz), the RF front-end takes the normal upper band of
the RF spectrum (that is, the LO frequency is less than the targeted frequency). In this case, the
DSP needs to down-convert the positive portion of spectrum, hence −107 in above equation. On
the contrary, when tuned to cellular band (< 1400MHz), the RF front-end takes the lower band
(the LO output is higher than the targeted frequency). In this case, the DSP needs to up-convert
the negative portion of the IF spectrum, therefore, 107 takes positive sign.
δf is simply calculated as:
δf = Ftarget − Fhadrware
where Ftarget is the actual center frequency that a user wants to tune to (1900.123456 MHz, for
example), Fhardware is the actual frequency that the front-end hardware can achieve (1900 MHz, for
example). The difference δf = 123456Hz has to be taken care of by the DSP in the IF processing
stage, so that all the DSP application modules will see a truly zero-centered base-band complex
signal.
If the front-end has 1 Hz level tuning step, then δf = 0 and ω = π
3 . In this case, the cos(nω)
and sin(nω) can be pre-calculated (for 6 samples) and stored in a table. This will be implemented
when future RF front-end is available.
For the current front-end hardware, where the LO only has discrete tuning steps (5MHz, 0.5MHz
etc), the cos(nω) and sin(nω) have to be generated in-fly as the δf value is “unpredictable” ahead
of time. Inside the “IQconvt dec6()” function, the sine and cosines are generated through the
following “digital oscillator”:
x(n) = 2cos(ω)x(n − 1) − x(n − 2)
Floating-point double precision is used to guarantee the computation accuracy.
7

8. 3.2 Low-pass filtering and decimation by 6
The down-converted signal is passed through a low-pass filter to reject the image signal at 20 MHz,
plus band-limiting the signal for the following decimation process.
The filtering and decimation procedures are actually handled “simultaneously” to take advantage
of the efficient poly-phase implementation. Simply speaking, the filter “weaves” through the input
I,Q signal in a step of 6 samples. At each step, the filter coefficients are correlated with the I,Q data
within the moving window. The result is the 10 MHz sampled output. The filter is then moved to
6 samples away.
If the IF is centered at a fixed 10 MHz, then further computational savings can be achieved by
fixing the filter length to 60, and using circular memory to cycle through the input data to eliminate
some unnecessary data copying. Details are quite self-evident in the IQconvt dec6() function.
The low-pass filter is right now designed through windowing method (Kaiser window of β = 9.0).
The filter has 60-taps, and cutoff frequency at 5 MHz.
The leading transients caused by the the 60-tap filter is skipped. This is equivalent to the fact
that, the captured signal has been moved ahead 59 samples at 60 MHz rate. The data-capturing
routine automatically captures 59 samples more to account for the skipping. Also notice that the
symmetric FIR filter has an inherent delay of 29.5 samples. So the end delay change that the
signal experienced is 29.5-59=-29.5 samples at 60 MHz (moving ahead). This is important for
delay related measurements as the PN-offset measurement in CDMA application.
3.3 Signal scaling
The base-band output signals (I(n) and Q(n) shown in Figure 4) are scaled down for the computa-
tional convenience of all DSP applications modules. The scaling factor is:
Scale =
1
2
1
2
1
215
1000
50
√
2 =
√
10
216
where, the first 1
2 is due to the Op-amp that precedes the ADC, the second 1
2 is due to the differential
mode of the ADC, 1
215 normalizes the integer ADC output to a fractional number between [-1,1)
(the ADC is 14-bit, but it is left-MSB-justified so that the output appears to be a 16-bit signed
integer to the DSP with full scale of −215 to 215 − 1), 1000 converts the output power from Watts
to milliwatts, and 50 (Ω) is the terminating impedance. The last
√
2 accounts for the 3-dB power
loss due to the mixing with cos(nω) and sin(nω).
The end goal of the scaling is such that, with a 0 dBm signal (within 5 MHz band) as input, the
down-converted (to base band) and decimated (to 10 MHz) complex I(n) and Q(n) values will yield
a correct 1 mW power, that is
1
N
ΣN
n=1(I2
(n) + Q2
(n)) = 1(mW)
when N is sufficiently large.
The scaling value is “embedded” into (multiplied with) the filter coefficients of the low-pass filter
shown in Figure 4.
8

9. 4 Application example, FFT-based spectrum analyzer
The purpose of this section is to use the spectrum analyzer as an example to further demonstrate
the signal flow-path leading to various applications. First, we need to know something about the
poly-phase-based sampling rate change.
4.1 Poly-phase-based sampling rate change
Software (or algorithm) based sampling rate change is the key to all RF measurement routines.
Poly-phase-based technique is the most efficient way of implementing the sampling rate change.
The academic background about sampling rate change can be found in text [5]. Here I make a few
key points that will help understand (and myself remember) the highly-efficient C-function that
implements the algorithm.
The problem can be simply put in this way: given an input data stream x(n), n = 0, 1, 2, . . . ,,
now interpolate the data by L-fold and decimate the signal by M-fold. More specifically, insert
(L-1) zeros between each two adjacent samples of x(n) and x(n+1), pass the zero-inserted signal
through a “smoothing” filter h(0), h(1), . . . , h(N − 1), and take the output once every M samples.
Figure 5 helps understand how this procedure can be performed efficiently by taking advantage of
the fact that, multiplying with zeroes should be omitted, and the output is only needed once every
M samples.
A brutal force approach requires an N-tap filter operating at a sampling rate of L × Finput. But a
correctly-implemented poly-phase approach requires (by average) an N
L -tap filter operating at the
output rate Fout = L
M Finput. The computational saving is tremendous when L and M, N and data
length become large, which is always the case for almost all DSP applications.
L LLLL
x(0) x(1) x(2) x(k0) x(k0+1) x(k0+2)x(k0-1)
M M
y(0) y(1) y(2) y(n) y(n+1)
M
h(0) h(i0) h(i0+L) h(i0+2L)
Figure 5: A diagram showing the efficient implementation of poly-phase sampling rate
change. The input sequence x(n) is inserted with (L-1) zeroes between adjacent
samples. The N-length filter is correlated with some of the input samples, and the
output is produced once every M samples.
The procedure shown in Figure 5 can be succinctly expressed as:
y(n) =
(kL−M)<N
k=k0
x(k)h(kL − nM), k0 =
nM
L
, n = 0, 1, 2, . . .
9

10. To most efficiently implement the above equation, the filter coefficients need to be re-organized as
follows:
1. Time reversing: the original N-tap filter coefficients g(n), n = 0, 1, 2, . . . , N − 1 need to be
time-reversed so that h(n) = g(N − 1 − n). For symmetric filter, this time-reversing step is
unnecessary.
2. Re-organize the time-reversed filter coefficients h(n), n = 0, 1, 2, . . . into an “interleaved”
fashion hh(0), hh(L), hh(2L), . . . , hh(1), hh(L + 1), hh(2L + 1), . . . , hh(2), hh(L + 2), hh(2L +
2), . . ..
3. The division operation implied in k0 = nM
L is avoided with successive additions in step of
L.
The C-functions that implement the above ideas are as follows:
/**Poly-phase-based sampling rate change***/
typedef struct {
float *htmp,**hp;
int N,M,L,*hlen;
int outsz;
} RSMP_Obj,*RSMP_Ptr;
RSMP_Ptr RSMP_open(int L, int M, int *iosz);
void RSMP_real(RSMP_Ptr,float*,float*);
void RSMP_cmplx(RSMP_Ptr,float*,float*);
void RSMP_close(RSMP_Ptr);
These functions are defined in the file “RFUTIL.C”.
Inside the RSMP Ptr RSMP open(...) function, a low-pass “smoothing” filter is defined. The filter
length is defined as N = 16 × MAX(L, M). The filter has a linear normalized (by sampling rate
L×Fsinput) digital cutoff frequency at fn = 16
N = 1
MAX(L,M) . The filter is a window-based low-pass
filter with Kaiser windowing of β = 10.0.
As shown in Figure 5, the filter transients are skipped, which is equivalent to moving the input
signal ahead by (N-1) samples at sampling rate L × Fsinput. Also notice that the symmetric FIR
filter has a natural delay of N−1
2 , hence the total delay experienced by the signal is 1−N
2 samples at
sampling rate L × Fsinput. This is again important for calibrating delay-sensitive measurements.
For all DSP applications, the desired number of output samples from the sampling rate change
module is known. For example, the spectrum analyzer module always requires the final output to
be 1024 complex sample pairs. The number of input samples then need to be determined as this
determines the number of samples that the PLD needs to acquire. A specific function static int
RSMP findinsz(L,M,N,outsz) was designed to find out the required input sample size depending on
the desired output sample size. The details are quite “self-evident” from the C-code itself.
10

11. 4.2 Definitions of resolution bandwidth, span and number of averaging (video-
bandwidth)
Before getting into the detailed discussions on the implementation of UCTT’s spectrum analyzer,
some terminologies need to be defined.
Assume we are performing a length N (N=1024, for example) FFT on an incoming data sampled
at a rate of Fs Hz, then:
1. Resolution bandwidth is δf = Fs
N .
2. When the host displays M+1 points of the calculated PSD (power-spectral-density), then the
span is span = Mδf.
3. By averaging K times, we mean this. Measure the PSD (through FFT) on K consecutive
blocks of data (each block consists of of N complex samples), add the K PSD values at each
frequency point, across all frequency points, and divide the results by K. In real implementa-
tion, the averaging is performed through a moving-window, so that the averaged results are
available at each data block, instead of every K data block. The relation between averaging
times K and the so-called “video bandwidth” used by scan-based spectrum analyzer remains
to be determined. Theoretically, averaging reduces the PSD estimation variance at each fre-
quency point, since the estimation variance is proportional to 1
N . In UCTT implementation,
K=0 and K=1 means the same thing (1-averaging or no averaging means the same thing
here).
4.3 Narrow-band Spectrum analyzer
By “narrow-band”, we mean the span width is no more than 5 MHz. The signal flow diagram for
this application is shown in Figure 6.
10MHz
sampled,
base-band
complex
(I,Q)
signals.
Poly-phase-
based
sampling rate
change by
32 x df
---------------
312500
1024-point
windowing
1024-point
complex
FFT
Scaling,
convert to
power,
and logorthmic
conversions
I(n)
Q(n)
Fs=10MHz Fs=1024 x df
Figure 6: Signal flow diagram for spectrum analyzer with span width no more than 5
MHz.
As shown in Figure 6, the FFT operates at a fixed-length (1024 complex pairs) regardless the
required resolution bandwidth and span width. It is the poly-phase sampling rate adaptors job
to make sure the final PSD output meet the required resolution bandwidth requirement. This
signal-processing architecture in Figure 6 is the most efficient approach.
11

12. More specifically, the resolution bandwidth is required to be an integer multiple of 100 Hz, that is
δf = k × 100Hz, k = 1, 2, 3, . . . , 500
With k value determined, the 10 MHz-sampled I(n) and Q(n) will be changed to a new sampling
rate of 32k
3125 MHz. For example, if δf = 100Hz is required, then the 10 MHz signal needs to be
interpolated by 32 times, and decimated by 3125 times so that the output (or input into the FFT
block) has a sampling rate of 102.4 KHz. If δf = 5000Hz is required, then the 10 MHz signal will
be interpolated by 64 times and decimated by 125 times to a new sampling rate of 5.12 MHz. So,
in summary, it is the resolution bandwidth that determines the sampling rate and also the data-
acquisition length. The smaller the resolution bandwidth, the longer the captured data sequence,
and larger sampling rate change is required, and therefore, the slower the DSP appears to be.
From a user point of view, however, one is more used to controlling the span width, instead of the
resolution bandwidth. In our implementation, the span width is related to the resolution bandwidth
by the number of points that are displayed on the screen:
Span = (P − 1)δf
where P designates the number of points to be displayed. For optimal visual effect, P is constrained
to 100 < P < 512.
So, when a user enters an arbitrary span width, the spectrum analyzer algorithm has to determine
both P and δf so that the equation span = (P −1)δf can be met. From all of the possible solutions,
the one with highest P value (< 512) (or finest δf value) will be selected. The chosen δf then
determines the sampling rate change ratio.
To guarantee span = (P − 1)δf will have integer solutions, the span width is constrained to be an
integer multiple of 1 KHz, in the range from 10 KHz to 5 MHz.
4.4 Wide-band spectrum analyzer
By wide band, we mean a span width wider than 5 MHz. Since the RF hardware only provides
a useful bandwidth of 5 MHz, to achieve the wide-band capability, a series of automatic and
coordinated front-end tuning, data gathering, signal processing and spectrum stitching are required
to generate the required spectrum. Figure 7 shows the simplified concept.
To make the stitching work smoothly with both the RF front-end hardware and the FFT algorithm,
the following restrictions apply:
1. The span width must be span = 5 × 2kMHz, k = 1, 2, 3, 4, 5, 6. This means the permissible
span width must be 5, 10, 20, 40, 80, 160 and 320 MHz.
2. The resolution bandwidth is no longer selectable. The resolution bandwidth is always tied to
the span width by δf = span/512.
3. The final stitched spectrum always contain 513 points to be displayed.
More specifically, the following steps are taken to generate the stitched wide-band spectrum.
1. Given a span width (in MHz), find G = span
5 , and make sure G = 2k, k = 1, 2, 3, 4, 5, 6.
Otherwise, adjust the span width to the nearest number that satisfies the constraints.
12

13. IF processing
block, IF to
base-band
connversion,
6:1 decimation
to generate
10MHz
sampled I,Q
output
Windowing,
FFTing
length
1024/(2^k)
I,Q data
sequence
Stich 2^k
segments
of spectra
together
Tune to f0
Tune to
f0+10MHz
Tune to
f0+5MHz
Tune to
f0+(2^k-
1)*5MHz
Final spectrum
Figure 7: A simplified block diagram of the wide-band spectrum analyzer implementa-
tion scheme.
2. From the given center frequency fc (in MHz), calculate the starting center frequency as
f0 = fc − (G − 1) × 2.5 MHz.
3. Tune the front-end to f0, acquire the IF data, and obtain D = 1024
G samples of the 10-MHz
sampled I,Q pairs. Perform a length D windowing and FFTing on the I,Q complex pairs.
Retain only the the D
2 + 1 points of the calculated PSD (power-spectral-density) centered on
the DC-component.
4. Tune the front-end to f0 + 5 MHz, repeat the data acquisition and FFT procedure of the
previous step, and obtain a new segment of PSD of length D
2 + 1. Stitch this segment with
previous segment by overlapping the first point with the last point of the previous segment,
so that the stitched 2-segment spectrum contain D + 1 points.
5. Tune the front-end to f0 + 10 MHz, repeat the above step to obtain the stitched 3-segment
spectrum that contains 3
2 D + 1 points.
6. Keep repeating the above step, until a total of 513 stitched points are acquired.
Despite the superficial complexity, the DSP works amazingly fast in the wide-band mode. This is
because the DSP is only processing very short segment of data, and no sampling rate change is
applied to any segment (the “short” FFT is directly applied to the 10-MHz sampled data sequence).
The hopping speed from one segment to the next is essentially dictated by the RF front-end’s
synthesizer’s stabilizing time.
4.5 Windowing functions
Windowing in time-domain can provide a visually more appealing spectrum in frequency domain,
especially for narrow-band signals such as discrete tones. UCTT’s spectrum analyzer provides
selection of the following window functions (for all windowing functions, N-point FFT is assumed
and t = (−1 : δt : 1), and δt = 2
N−1 ):
1. Uniform window (or no windowing):
w(n) = 1, n = 0, 1, 2, . . . , N − 1
13

14. 2. Kaiser window:
w(n) = I0(β 1 − t2)
where I0(x) is the zeroth-order modified Bessel function of the first kind, and typical β value
ranges from 6 to 13. In our implementation, β = 10 is used. For practical implementation,
the modified Bessel function is approximated with its series expansion to tolerable accuracy:
I0(x) = 1 +
∞
k=1
(
(x/2)k
k!
)2
3. Hanning window:
w(n) = 0.5 + 0.5cos(tπ)
4. Hamming window:
w(n) = 0.54 + 0.36cos(tπ)
5. Gauss window:
w(n) = e−βt2
where β is the same as that used in Kaiser window.
4.6 Normalization of the windowing functions
The windowing function should be normalized in such as way that the total power across the
anaylysis band is conserved (constant). More explicitly, the scale should be:
Scale =
N
N−1
n=0 w2(n)
But sadly, the establishment (existing FFT-based spectrum analyzer) seems to use the following
scaling factor:
Scale =
N
N−1
n=0 w(n)
The above scaling factor, although incorrect, does have the appeal that the peak value of a single-
tone input does not change. We are facing a dillema here. Should we do something that is
scientifically correct, or should we just follow the establishment, and keep repeating the same
mistake.
4.7 Some FFT technical details
The down-scaled, sampling-rate-changed and windowed complex sequence z(n) = I(n) + jQ(n) is
Fourier-transformed (through FFT) to frequency domain:
Z(k) =
N−1
n=0
z(n)ej 2πkn
N , k = 0, 1, 2, . . . , N − 1
The spectrum Z(k) itself is also complex. For “scalar” spectrum analyzer, only its power amplitude
is of interest. The normalized PSD (Power-Spectral-Density) is:
Pz(k) =
1
N2
|Z(k)|2
14

15. With the normalization and scaling described here, Pz(k) is the signal power (in unit of milliwatt)
within a band of δf Hz, and centered at the frequency point designated by index k. When converting
to logarithmic scale:
PdB(k) = 10 log 10(Pz(k))
PdB(k) measures the total power in unit of dBm within the bandwidth of δf. This PdB(k) is the
data to be displayed.
If a “true” power-density is needed, then the power Pz(k) needs to be normalized by the resolution
bandwidth δf:
Pn(k) =
Pz(k)
δf
Pn(k) then means the signal power density per Hz (mW/Hz).
For the N-point sequence Z(k) or Pz(k), most applications only require a short segment out of it,
and the short segment is DC-centered. Consider we need 2Q+1 points out of the N-point spectrum,
and the middle point corresponds to the DC, then the following circular swapping is needed:
Pnew(k + Q) = Pz((k + N)%N), k = −Q, −Q + 1, . . . , −1, 0, 1, . . . , Q − 1, Q
where x%N designates the modulo N calculation. This is used in all spectrum analyzer measure-
ments.
References
[1] Renshou Dai, “Managing the DS1 Data Streams between one TI C671x DSP and two Infineon
PEB2256 Framers,” Sage document, July, 2003.
[2] Royce W. Fletcher, “UCTT RF-DSP PLD-Core description,” Sage document, Feb., 2003.
[3] Mike Groh, “Hardware module specification of UCTT transceiver,” Sage document, May, 2003.
[4] “TMS320C6000 Peripherals Reference Guide”, Texas Instruments Literature Number
SPRU190D, Feb., 2001.
[5] P. P. Vaidyanathan, “Muiltirate systems and filter banks,” Prentice Hall Signal Processing
Series, 1993.
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