1. Characterisation of VHF Transistors
(Work done on Transistor 2N2222)
Presented by:
o Mohit Mukul 1104030
o Harsh Prakash Singh 1104062
o Rahul Kumar 1104063
Under the supervision of : Dr. Bijay Kumar Sharma
DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING,
NIT PATNA
2. Introduction
Objectives
Apparatus used
Literature survey
Observations made on various current sources under various
drive conditions
Results drawn
Work done till now
Conclusions derived from the former
Work to be done in the upcoming future
Phases of the project
3. Quest for Terra Hertz Si-Ge HBT(Heterojunction Bipolar Transistor) has led to sustained scaling
which has enabled the achievement of transit frequency = 315GHz at 300K but it has simultaneously
degraded BVCEO to 1.63V.
To maximize the safe-operating-area (SOA) beyond 1.63V, a theoretical formalism of the variable
latching phenomena of CE BJT under various drive conditions and under static and dynamic
conditions is one of the central problems in the design of high speed circuits.
Until this date multi-element models have been developed based on device physics to predict SOA
of CE Si-BJT beyond BVCEO under variable drive conditions.
Hence, we employ a circuit plus device approach to develop a single analytic relation to model the
variable latching phenomena of CE BJT current sources first discovered in 1989.
This analytic relationship has been verified by experimental results using 2N3055 CE current sources.
Once this is embedded in the compact model of future HSPICE, simulation software will enable
model-to-hardware correlation in future simulation and prediction of SOA.
Accurate and realistic simulation will lead to reduced concept-to-design-to-production time
considerably improving the scale of economy of industrial production of IC chips.
Introduction
4. To find the correct relation for Ro (Output Impedance)
To find the relation between Ro (output impedance) and the
Breakover voltage.
To develop a single analytic relation to model the variable
latching phenomena of the current sources under various drive
conditions
To maximize the Safe Operating Area (SOA), typically called the
sustaining voltage Vs, at high Ultra High Frequency (order of THz)
beyond the BVceo of a CE BJT.
Objectives
5. Model 4200-SCS (Semiconductor Characterisation System) by
KEITHLEY Instruments Pvt. Ltd.
A PC/laptop with installed Matlab (2011a version) on it.
200 npn (until we get a perfectly matched pair) 2N2222
transistors to be matched by Impedance testing
Resistances of different values (0.98k, 0.461k, 0.2185k and
others as per need)
A bread board with atleast 10 connecting wires
Apparatus used
6. The maximum usable voltage of CE BJT, popularly known as the Sustaining Voltage (VS), varies
with drive conditions.
At constant base current drive condition in CE Configuration for IB = 0, VS is slightly less than
BVCEO (break-over voltage between collector and emitter with base open) exhibiting a
Negative-Impedance-Region of S-Type.
At constant emitter current drive condition in CB Configuration at IE = 0, the maximum usable
voltage is Avalanche Breakdown Voltage of CB Junction namely BVCBO.
It is observed that at high speed operations due to high current demand, the sustaining voltage
is reduced. Therefore an accurate model of variable sustaining voltage is one of the central
problems of high speed Si- Bipolar Circuit Design.
Here, we have used two analytic relationships on the basis of the small signal parameter R0(the
output impedance of the current source) and on the basis of large signal parameter, the Break-
over Voltage/Latching Voltage/Sustaining Voltage, symbolized by BVCEX. These relationships will
determine the device parameters and the circuit parameters required for the simulation of the
variable latching phenomena.
Literature Survey
7. The maximum usable voltage of CE BJT ,
popularly known as the Sustaining Voltage
(Vs), varies with drive conditions.
At constant base current drive condition
in CE Configuration for Ib = 0, Vs is slightly
less than BVceo (break-over voltage
between collector and emitter with base
open) exhibiting a Negative-Impedance-
Region of S-Type.
The slope in this figure is due to the base
width modulation also known as Early
effect. Ic=Iceo when Ib=0 mA. This is the CB
junc. leakage current with base open and
is of micro Ampere range.
CE BJT Configuration
9. Let us consider: then if f M=1:
At this point, break-over occurs and we have BVceo= Break-over Voltage with Base
circuit open.
When fM=1, that is: => =>
(cont.)
10. but we know that:
Thus:
Thus:
Thus we have seen that break-over occurs at fM=1. At low current f is very small, almost equal
to 0.1. Therefore, voltage has to be taken to a large value to satisfy this. But as soon as break-over
occurs, large current starts flowing. With large current f moves from 0.1 to 0.99. Hence it is
satisfied at lower voltage Vs. Thus break-over curves settles down at Vs. Because Vs<BVceo, we
get a Negative Impedance Region (NIR).
(cont.)
12. At constant emitter current drive condition
in CB Configuration at Ie=0, the maximum
usable voltage is Avalanche Breakdown
Voltage of CB Junction namely BVcbo.
Ic = Icbo/ {1-(Vcb/BVcbo)^n}
where Ic is the collector current, Icbo is the
reverse leakage current at the collector
junction with the emitter open, Vcb is the
voltage bias, BVcbo is the Avalanche
breakdown of the CB junction with emitter
open and n = miller indices (2-6).
Also, M = 1/{1-(Vcb/BVcbo)^n}
Where M = Avalanche Multiplication factor
CB BJT Configuration
13. Here,
Ic= fMIe + Icbo
Where f = DC Forward
current transfer ratio of CB
BJT = Ic/Ie;
M= Avalanche multiplication
factor at BC junction. Ic=Icbo
when Ie=0 mA. This is the
reverse leakage current (nA
range).
(cont.)
15. A current mirror is a circuit designed to copy a current through
one active device by controlling the current in another active
device of a circuit, keeping the output current constant regardless
of loading.
The current being 'copied‘ can be, and sometimes is, a varying
signal current.
Conceptually, an ideal current mirror is simply an ideal inverting
current amplifier that reverses the current direction as well or it is a
current-controlled current source (CCCS).
The current mirror is used to provide bias currents and active
loads to circuits.
It is used as a Constant Current Source.
It has a high O/P impedance.
It is used as an Active load in the Differential amplifier to a very
high d.m. voltage gain.
This differential amplifier is the building block of the operational
amplifier.
Current Mirror Configuration
16. F1 (V) Ic (mA) Ro (K ohm)
4.7249 1.0701 149.000
4.8242 1.0708 124.000
4.9284 1.0716 141.857
5.0277 1.0723 141.857
5.1270 1.0730 124.000
5.2262 1.0738 134.803
Observations for Current Mirror
Configuration
17. The basic current mirror source has a drawback
that for a low value current source, the
resistance R required is sufficiently large and
can’t be fabricated economically in the IC
circuit.
So, we use Widlar Current Source which is
particularly suitable for low values of current.
Its circuit differs from the basic current mirror
only in the resistance Re that is included in the
emitter lead of the transistor Q2
A voltage difference is caused across the
emitter resistor Re so that VBE2 is lesser than VBE1.
A smaller VBE1 produces a smaller collector
current. So, Iout is lesser than Iref.
Widlar Current Source
21. Current Source Break-over voltage
Constant Base current driven CE BJT (BVceo) 62V
Constant Emitter current driven CB BJT (BVcbo) 106.64V
Asymmetric Widlar (Re1=0, Re2=0.98k) (BVce_widlar) 104.9V
Symmetric Widlar (Re1=Re2=0.98k) (BVcex5) 104.62V
Symmetric Widlar (Re1=Re2=0.461k) (BVcex4) 103.2V
Symmetric Widlar (Re1=Re2=218.5ohm) (BVcex3) 102.66V
Results for Break-over voltages
22. Current Source 2N2222
CB BJT Configuration 2.5542M
CE BJT Configuration 129.47k
Current Mirror Config. 134.803k
Symmetric Widlar Config. 2.002M
Symmetric Widlar Config. 952.925K
Symmetric Widlar Config. 483.95K
Results for Output Impedance (Ro)
23. Impedance matching of the transistors and selecting two
matched transistors as our Device Under Test (DUT)
Obtained the value of the Miller indices using the least squared
error method and finding the best fit (in MATLAB)
Observation of the I-V characteristics of the different current
sources under various drive conditions.
Validating the observed values using the analytical relation of
the parameters.
Work done till now
24. αmin+∆(VCEXj)+(VCEX/BVCBO)^n=1 ……..(1)
Rearranging the terms we get the total α derivative
dα/dVCE={1/R0j(1+β)IEQ}
Thus, integrating w.r.t. VCE, we get:
∆α(BVCEXj)=∫{1/R0j(1+β}*dVCE(0,BVCEX)
Substituting in equation (1), we get:
αmin+∫{1/R0j(1+β)IEQxdVCE}+(VCEX /BVCBO)^n=1
Finally the theoretical formula can be depicted as below:
α min +Log{(R0jI EQ + (1 + β0)(BVCEXj + VAj)}/(1+β0)
−Log[(R0jIEQ+ (1 +β 0)(VAj)]/(1+β0)+(VCEX /BVCBO)^n=1
After substituting the values for different variables under different drive conditions, we found
that the theoretical formalism above has been satisfied. Experimental values of the latching
voltages and theoretical values of the output impedance have satisfied theoretical formalism with
less than 2.5 percentage error.
Conclusion
25. The incremental slope of I-V characteristics of higher order current
sources can easily be measured by Keithley’s Instrument with much
higher accuracy.
In future work Keithley characterization system will be used and high
frequency Si BJT and SiGe BJT will be subjected to these tests to
establish the validity.
In this study only static tests have been made and investigated. The safe
voltage limit has to be studied in dynamic conditions and the lowering
of voltage limit under high frequency signal conditions have to be
studied.
Work to be done in future
26. 1. THEORETICAL FORMULATION OF VARIABLE LATCHING
PHENOMENA in different configurations of CURRENT
SOURCES using CE BJT-2N3055 by Dr. B.K.Sharma
2. Solid State Physics and Devices by Streetman & Banerjee
3. Solid State Physics & Devices – The Harbinger of Third Wave of
Civilization (www.cnx.org)
4. Wikipedia (www.wikipedia.org)
5. Electronic Devices & Circuit Theory by Robert Boylestad and
Louis Nashelsky.
References
