1. Satellite Optical Payload
Controller and Data processing
Embedded System
By-Priyanka Goswami(12BIC053)
Guided by- Prof. H.K Patel
Mr. Jimit Gadhiya,
(SCPD/SEDA, SAC, ISRO)

2. Electro-Optical Payload
• Electro optical satellite payload is a special instrument designed and developed
for operating on a satellite deck.
• It carries out the remote sensing of the earth surface which is then used to
generate images for carrying out weather and atmospheric observations and
resource mapping of earth surface and also in interplanetary missions.
• The EO Payload has the following components:
1. Telescope
2. Sensor/Detector Array
3. The analog signals from the pixels of the detector are connected to
electronic processing circuits like pre-amplifiers followed by ADC.
4. The digitised output stream is further processed/formatted and then
transferred to other satellite sub-systems like data transmitters and RF
antennas.
5. Payload commanding and control system (Payload Controller).
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3. Payload Controller
• A payload controller is designed, developed and incorporated in the instrument
for remote control and monitoring of complex instrument like the EO payload.
• Main task performed by the controller are:
1. Interfacing the payload with the satellite systems like on-board
computer(OBC) telemetry and tele- command system and interfacing it
with the data handling system.
2. Commanding.
3. Power on/off and special power sequence.
4. Enabling and disabling clocks and timing signals, timer. based on/off and
period of operation.
5. Mode selection (calibration, de-contamination, etc)
6. Control of the temperature using heaters.
7. Ensuring that the above tasks are run in a proper schedule.
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4. Figure.1: Block Diagram of Payload Controller with other sub-systems
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5. Payload Controller
• The payload controller is implemented using a dedicated micro-controller based
system on a single FPGA (SoC) with a defined interfacing logic.
• It consists of a dedicated embedded hardware which includes:
1. MIL1553 controller
2. Microcontroller like 8051
3. GPIO ports
4. Timer
5. APB3 Bus
6. Memory blocks
• Software which includes the initialisation program, scheduler and application
programs and will run on the embedded hardware.
• The embedded hardware is developed using IP Cores from the Microsemi
Library in VHDL in LiberoIDE for radiation hardened device like RTAX2000.
• The System Initialization, Scheduler and Application program is developed in
Embedded C in Keil uVision 5 software.
• The simulation of the complete project is done using ModelSIM.
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6. Embedded Hardware in SoC
Figure.2: Block Diagram of Embedded Hardware developed in LiberoIDE
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7. • In-built IP Core available in the Microsemi library.
• 8-bit embedded microcontroller having similar functionalities like the
Intel 8051 or Atmel AT89c51.
• It performs the task of initialising the 1553BRM IP Core internal
registers, CoreTimer, various Interrupts and running the scheduler
• Uses the Harvard architecture (separate memory spaces for code and
data).
Core8051s
Figure.3 : Core8051s I/O PortsInstitute of Technology, Nirma University 7

8. Core8051s Memory
1. Program memory (PROM) - Core8051s can address up to 64K (0x0000 to 0xFFFF) of
program memory. It is accessed by the core whenever the MEMPSRD signal goes high
and the op-code located at the address determined by MEMADDR is fetched and sent
through the input port MEMDATAI.
Figure.4: Core8051s reading Op-Code from Program Memory
2. Internal Memory - The Core8051s has an internal memory of 256x8 bytes that has
been divided into two parts: 1). Add. 0x80 to 0xFF are reserved for the SFRs and 2).
Add. 0x00 to 0x7F is reserved for internal RAM.
The SFRs are accessed through direct addressing. Since the SFRs of Core8051s and
Intel 8051 are different a separate library file was created in Keil for utilising the
various SFRs.
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9. Core8051s Memory
3. External Data Memory: The Core8051s can address external data memory of
maximum 64K (0x0000 to 0xFFFF). For the payload controller the External
data memory has been synthesised within the FPGA using a Two Port RAM IP
core which is available in the Microsemi Core Library.
Table.1: Memory Mapping of External Data Memory
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10. MIL-STD-1553 Protocol & 1553BRM IP Core
• MIL-STD-1553 Protocol was first defined by the United States Department of
Defense as a U.S. Air Force standard in 1973.
• It has 3 types of terminal : Bus Controller (BC), Remote Terminal (RT) and Bus
Monitor (BM).
• The words are of following types (as used in project):
1. Command Word
2. Data Word
• Each word is transmitted in Manchester encoded form. A packet will be made of
3-bit sync pulse followed by the 16-bit word and 1 bit for odd parity.
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11. • For example: Command word: (0x0822) 16 = (0000100000100010)2. The
transmitted command word after being converted to Manchester encoded form
is:
Figure.4: Waveform showing Manchester encoding of Command and 2 Data words
• The IP Core (developed in VHDL) performs the function of the MIL1553 controller
and is operated in RT mode with 24MHz clock.
• It receives command and data words from the On Board Computer (OBC) through
the MIL-STD-1553 bus in Manchester encoded form.
• The Core8051s is used to initialise the control registers of the MIL1553 IP Core to
set its mode of function, internal parameters, descriptor blocks and enable the
interrupts. Institute of Technology, Nirma University 11

12. • The ‘Sub address Accessed’ Interrupt of the 1553BRM IP Core is enabled through
the Interrupt Mask register by setting the bit ‘1’.
• INTOUTM (mapped to a input port bit of Core8051s) goes high when a new
message is received and remains so till acknowledged (INTACKM given high to low
pulse).
Table.2: 1553BRM IP Core Internal Registers for RT mode of operation
Figure.5: Simulation of 1553BRM IP Core Interrupt
• 8051 accesses the internal registers of 1553BRM through the following external
memory addresses:
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13. 1553BRM IP Core
• Descriptor block for RT Mode Operation : A block of 512 consecutive words is
reserved in the memory for storing the sub addresses and the descriptor table.
The following information is store:
1. Control Word - It is a 16-bit word used by the core to process the message, details
about the transaction and is initialised by the CPU .
2. Data Pointer A or B- It contains the 16 bit starting address where the message
received by the core is stored and can be later retrieved.
Figure.6: Simulation of 1553BRM IP Core receiving Data Words and storing in the backend memory
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14. Core Timer
• Decrementing counter based timer IP core available in the Microsemi library.
• Used for providing periodic ticks to the Core8051s required for execution of the
scheduler.
• Required as the Core8051s does not have an internal timer or counter.
• It is an APB slave and hence is interfaced through the CoreAPB3 to the 8051s
(which is an APB master).
• The timer registers are initialised by the 8051s by writing to the corresponding
addresses of the external memory (reserved by APB3).
• The timer is being operated in the continuous mode.
Table.3: Memory Map for APB3-Core Timer Interface
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15. • The TIMINT pin of the CoreTimer is connected to the INT1 pin of 8051s. When the
decrementing counter becomes zero an interrupt is generated and in the interrupt
service routine Timer interrupt pin is cleared for the next cycle.
• For generating timer ticks at 0.25ms time interval:
The PCLK runs at a frequency of 24MHZ = 0.041667us
The Pre-scale value = (64)10
Hence counter will decrement at timer interval = 0.041667us x 128 = 5.33us.
To get tick interval at 0.25ms = 250us:
250us/5.33us = (46)10 = (2E) 16
Figure.7: Simulation of CoreTimer for generating 0.25ms ticks
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16. AMBA Bus & CoreAPB3
• The Advanced Microcontroller Bus Architecture (AMBA) was first introduced in
1996
• It is widely used interconnection standard for high performance embedded
processors which can be implemented in System on Chip (SoC) design.
• The CoreAPB3 is a bus component that provides AMBA 3 Advanced Peripheral
Bus fabric for interconnecting an APB master and up to 16 APB slaves.
• The APB bus is used in the project for interfacing the Core8051s, which is an
embedded processor and a APB master to the CoreTimer which a APB slave .
• The APB3 bus reserves the top 4K of the external memory for the interfacing of
the slave devices with the master.
• The APB3 interfaces the first peripheral from the address 0xF000 onwards with
offsets of 0x04, 0x08, 0x0C etc.
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17. Figure.8: Simulation of CoreAPB3 transaction with Core8051s and CoreTimer
• When the Core8051s writes an 8-bit data in the memory address 0xF000, the
address (through PADDR port) and the 8-bit data (through PWDATA port) is sent
to the corresponding ports of the CoreAPB3.
• Also since the data is written on address 0xF000 the Core8051s also sends a
PSELS signal to select the APB3 slave 0 (CoreTimer).
• The data then gets latched to the bus and is sent to the slave and gets written in
the 0x00 addressed internal register of the peripheral.
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18. Testing of Embedded Hardware
• Tested by adding a Testbench which mimics the On-Board Computer and sends
command and data words in Manchester Encoded form to the Core1553 and
generates the 24Mhz system clock and system reset signals.
Figure.9: Simulation of embedded hardware using TestbenchInstitute of Technology, Nirma University 18

19. Scheduler
• Scheduler is an application that handles the sharing of the CPU and resources
like I/O ports among different tasks.
• The scheduler has to maintain two types of task queues:
– The Job Queue
– The Ready Queue
• The scheduler will have the following functions:
– Initialise CoreTimer and MIL1553 IP Core
– Start the Timer and also enable the Core8051s INT1 interrupt
– Add task to the Job Queue
– Check the task delay and flag and execute task.
– Decrement the delay counter and update job queue (implemented as ISR when the
CoreTimer generates an interrupt)
– Wait state (interrupted by the scheduler/timer tick).
• For the Payload Controller, three types of scheduler algorithms were designed:
– Co-operative type Scheduler.
– Round-Robin type Scheduler.
– Round-Robin Scheduler with one Interrupt based High Priority Task (Hybrid-
Scheduler).
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20. Co-Operative Scheduler
• Advantages:
– It is the simplest type of scheduler
algorithm to implement.
– There is no risk of task being
interrupted as the next task in
queue is executed only when the
first task has been executed.
– Program size is 631 bytes.
• Disadvantages:
– All the tasks have to be designed
such that their total execution time
is less than the timer period.
– If a task gets into an endless loop
the other tasks will not get
executed as the timer will reset the
scheduler and a new cycle will task.
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21. Round-Robin Scheduler
• Advantages:
– It is a deterministic scheduler.
– No task monopolises the CPU for time
more than that set by the timer after
which the task queue is updated.
– Periodic task will always be executed
at the pre-determined time-interval.
• Disadvantages:
– No task can be assigned a higher
priority.
– If no task is to be executed for a
particular period, then the scheduler
goes to wait state.
– Program size is 700 bytes which is
more compared to Co-operative
scheduler.
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22. Round-Robin Scheduler with High Priority Task
• Advantages:
– Task can be assigned a higher priority.
– It also ensures that there is no loss of data
(which will be coming in real time) .
– Critical tasks will be serviced immediately.
• Disadvantages:
– It is an un-deterministic scheduler as
current task execution will be stopped and
the scheduler can be interrupted at any
point of execution,
– Point of return from the interrupt is hence
scheduler can fail.
– Program size is 763 bytes .
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23. Simulation Results
Figure:10. Simulation of Co-operative Scheduler
Figure:11. Simulation of Round-Robin Scheduler
Figure:12. Simulation of Round-Robin Scheduler with High Priority Task
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24. Payload Controller Applications
• In the project two tasks have been developed:
1. Task1 : Receiving and Storing Data Words received from the OBC
Core8051s reads two data words (DW1 and DW2) coming from the 1553BRM IP
Core and stores a copy in the external data memory. It then generates a high to
low pulse bit 2 of output port 5 (which is mapped to INTACKM input pin) to clear
interrupt of 1553BRM IP Core for next data packet. The 16-bit data words will be
stored in two 8 bit words (MSB and LSB).
Figure.13: Simulation of Task 1- Receiving and Storing Data Words
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25. 2. Task 2: Interpreting the data words to determine the type of command to be
executed and implementing the corresponding function by processing them.
– The program first reads the MSB of DW1 and determines the type of command to
be executed (Table.4).
– Depending on command it will process DW2 to generate either on/off pulse on
particular bits of o/p port or send it as a data command in serial form.
Table.4: Command types with corresponding identification parameter
• For example if OBC sends DW1 and DW2 as E1AA and 89F3 respectively then the On
command will be scheduled and when task is executed a pulse will be generated on bit 2
of output port 1.
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26. Implementation and Testing of Payload
Controller
Figure.16: Simulation of Payload Controller system with multiple on, off and data commands
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27. Project Outcome
• A System on Chip (SoC/FPGA) based payload controller has been designed and
tested for use in electro-optical payloads like GISAT, Chandrayaan-2 and OCM
satellites.
• The LiberoIDE software was used for designing the embedded hardware and I/O
port mapping. A custom Testbench developed in VHDL was used for testing and
simulation of the system using the ModelSIM software.
• The software was written in Embedded C language and compiled in Keil
uVision5 software .
• Study of the MIL-STD-1553 and AMBA protocol was carried out.
• The project included developing of the controller software, which included
initialization of the 1553BRM IP Core registers and use of CoreTimer.
• A study and development of different Scheduler algorithms was carried out and
the Round-Robin type of scheduler was selected for the payload controller.
• Pulse command and Data Command payload applications were designed and
implemented using the scheduler.
• The whole payload controller system (hardware and software) was tested and
simulated successfully and ready for hardware implementation.
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28. Thank You
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