The document discusses the ARM architecture. It describes the history and development of ARM, including being developed in the 1980s in England and the founding of ARM Limited in 1990. It notes ARM is based on the RISC architecture and enhances it for embedded applications. ARM implements both 32-bit and 16-bit instruction sets. The document outlines key features of the ARM architecture like the Thumb instruction set, memory management, register-based operations, conditional execution, and the instruction set categories.

1. UNIT II

2. VON NEUMANN ARCHITECTURE VS
HARVARD ARCHITECTURE

5. ARM

6. History
• ARM was developed at Acron Computer Limited
of Cambridge, England between 1983 and 1985
• RISC concept introduced in 1980 at Stanford and
Berkley
• ARM Limited founded in 1990
• ARM Cores
– Licensed to partners to develop and fabricate new
micro-controllers
– Soft-core

7. ARM Architecture
• Based upon RISC Architecture with enhancements to
meet requirements of embedded applications
– A large uniform register file
– Load-store architecture, where data processing operations
operate on register contents only
– Uniform and fixed length instructions
– 32-bit processor
– Instructions are 32-bit long
– Von Neuman-type bus structure (ARM7), Harvard (ARM9)
– Good Speed/Power Consumption Ratio
– High Code Density

8. • Most ARM's implement two instruction sets
1. 32-bit ARM Instruction Set
2. 16-bit Thumb Instruction Set
• Data type can be
– 8 bit bytes
– 16 bit half-words
– 32 bit words
– may be seen as a byte line folded into 4-byte
words.

10. ARM Features
• Thumb Set designed for 16-bit word lengths and
instructions, which internally executes by same 32-
bit core.
• ARM views memory as a linear collection of bytes
numbered upwards from zero. it contains memory
management unit and memory protection unit.
• Most operations are executed over registers.
• All instructions can be conditional.
• it uses Big-endian and Little-endian method.

11. ARM Features
• The ARM processor supports 25 different instruction
• ARM provides no explicit return instruction.
• The Software Interrupt (SWI) instruction is the only
way an ARM processor can access resources controlled
by the operating system.
• Many Thumb data processing instructions use a 2-
address format.
• The ARM architecture has a large variety of addressing
modes

12. ARM Architecture
• The ARM cortex is a complicated microcontroller
within the ARM family that has ARMv7 design. There
are 3 subfamilies within the ARM cortex family:
a) ARM Cortex Ax-series
b) ARM Cortex Rx-series
c) ARM Cortex Mx-series
• • The ARM Architecture consists of following:
a) Arithmetic Logic Unit
b) Booth multiplier
c) Barrel shifter
d) Control unit
e) Register file

15. • Priority encoder
• Multiplexers
• Arithmetic Logic Unit (ALU)
• Booth multiplier factor
• Barrel Sifter
• Control unit
• Incrementer
• Address Register
• Instruction decoder
• Register file

17. The Program Status Registers

18. Processor Modes

22. Format summary

25. Conditional Execution

26. The Condition Field

27. Instruction Set
• The instruction set can be broadly classified as
follows:
i) Data processing instructions
ii) Load store instructions—single register, multiple
register
iii) Branch instructions
iv) Status register access instructions

28. Data Processing Instructions

29. ARM data processing instructions

30. Data processing Instruction Format

31. Arithmetic Operations

32. Comparisons

33. Logical Operations

34. Data Movement

35. Multiplication Instructions

36. Shift Instructions

37. Load / Store Instructions

38. Single register data transfer

39. Single register data transfer format

40. Load and Store Word or Byte: Base
Register

41. • In register-indirect addressing, the value
stored in the register is used as the address to
be fetched from memory; the result of that
fetch is the desired operand value.
• LDR r0,[r1]
• LDR r0,[r1, -r2]
• LDR r0,[r1, #4]

42. Load and Store Word or Byte: Offsets
from the Base Register

43. Load and Store Word or Byte: Pre-
indexed Addressing

44. Load and Store Word or Byte: Post-
indexed Addressing

45. Load and Stores with User Mode
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