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MIPI DevCon 2016: Troubleshooting MIPI M-PHY Link and Protocol Issues

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The M-PHY specification is designed to allow mobile devices to have a low power, high performance interface. Several higher level protocols use the M-PHY physical layer for storage, I/O and memory in mobile devices. In this presentation, Gordon Getty of Teledyne LeCroy discusses how higher layer protocols, including UniPro and UFS, use the M-PHY physical layer to provide an efficient, low power storage protocol to be enabled on mobile platforms. It also covers debug and analysis techniques for UFS and UniPro technologies to allow root-cause analysis to be performed in an efficient and effective manner.

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MIPI DevCon 2016: Troubleshooting MIPI M-PHY Link and Protocol Issues

  1. 1. Troubleshooting MIPI M-PHY Link and Protocol Issues Gordon Getty Application Engineer Teledyne LeCroy
  2. 2. Objective 2 A major component of the "Internet of Things" is mobile device support. The MIPI M-PHY specification is designed to allow mobile devices to have a low power, high performance interface. Several higher level protocols use the M- PHY physical layer for storage, I/O and memory in mobile devices. This paper will discuss how higher layer protocols such as MIPI UniPro, and UFS use the M-PHY physical layer to allow traditional PC type protocols to be enabled on mobile platforms.
  3. 3. Internet of Things “IoT” MIPI/Mobile Market Overview
  4. 4. “Internet of Things” 4
  5. 5. New Markets Reaching 1 Billion Milestone Quickly •  Cell phones sold 1 Billion units in 7.5 years, PCs took 21 years. •  Mobile shipped 4 Billion units in 12.5 years, PC market will take over 33 years. •  Tablets will hit 1 Billion in 6 years. 5
  6. 6. Mobility Driving Growth 6 •  Mobile market will be >8 times the size of the PC market •  Notebook PCs evolving into large tablets
  7. 7. Market Trends •  Smartphone market driving innovation •  Large volumes, fast design cycles •  Personal, always at hand •  Other markets will leverage smartphone designs •  •  Increasing number of MEMS per system •   Eroding ASPs •  Sensor Hub will become more specialized •  32-bit MCU will be challenged 7
  8. 8. MIPI Technologies
  9. 9. Physical Layer Interconnects •  Low Speed Interconnects •  MIPI SlimBus •  Audio •  MIPI SoundWire •  Audio •  CMOS I/O •  Chip to Chip •  High Speed Interconnects •  MIPI D-PHY •  Camera, Display •  MIPI M-PHY •  MIPI UniPro/UniPort •  Camera (Unipro), Storage (UniPro), Modem, Interchip 9
  10. 10. MIPI M-PHY Protocols •  MIPI M-PHY protocols are used based on interface used in each application. •  Multiple protocols can be used in a single device. 10
  11. 11. MIPI M-PHY
  12. 12. Why MIPI M-PHY? From the M-PHY Specification V4.0: “Mobile devices face increasing bandwidth demands for each of its functions as well as an increase of the number of functions integrated into the system. This requires wide bandwidth, low-pin count (serial) and highly power-efficient (network) interfaces that provides sufficient flexibility to be attractive for multiple applications, but which can also be covered with one physical layer technology. M-PHY is the successor of D- PHY, requiring less pins and providing more bandwidth per pin (pair) with improved power efficiency.” 12
  13. 13. M-PHY Lane Example - Terminology 13
  14. 14. Line States •  M-PHY technology exploits only differential signaling. a LINE can show the following states: •  A positive differential voltage, driven by the M-TX, which is denoted by LINE state DIF-P •  A negative differential voltage, driven by the M-TX, which is denoted by LINE state DIF-N •  A weak zero differential voltage, maintained by M-RX, which is denoted by LINE state DIF-Z •  An unknown, floating LINE voltage, or no LINE drive, which is denoted by LINE state DIF-Q 14
  15. 15. Signal Amplitudes •  All communication is based on low-swing, DC-coupled, differential signaling •  The LINE driver in an M-TX may support two drive strengths, resulting in different signal amplitudes. •  Large Amplitude (LA) is about 400 mVPK_NT (and roughly 200 mVPK_RT) •  Small Amplitude (SA) is about 240 mVPK_NT (and roughly 120 mVPK_RT) 15
  16. 16. Signaling Schemes •  LS and HS Speed (Optional) •  May use a shared clock or different reference clocks •  Uses NRZ signaling 16
  17. 17. Data Rates •  LS-MODE •  Gears 0-7 •  HS-MODE •  Gears 1-3 •  All Modules (Host and Device) must support LS •  Default for PWM is Gear1 3-9Mbs •  Each Gear supports 2x higher speeds •  one GEAR below the default speed range (PWM-G0) •  HS-Mode is Optional •  HS-MODE includes a default GEAR (HS-G1) •  Two optional GEARs (HS-G2 and HS-G3) at incremental 2x higher rates •  Each GEAR includes two data rates for EMI mitigation reasons •  HS-G1 supports 1.25 Gbps and 1.45 Gbps •  These two data rates are known as A & B •  Support for a LS or a HS GEAR requires support for all GEARs below 17
  18. 18. M-PHY Data Rates 18 Low-Speed Gears - Pulse-Width-Modula0on (PWM) - Self-Clocking High-Speed Gears - Non-Return-to-Zero(NRZ) - Small and large amplitude modes
  19. 19. Clock Rate Differences •  Clock Rate A or B 19
  20. 20. State Machine 20 •  Two operating modes, •  HS-MODE •  LS-MODE •  A data transmission (BURST) state and a MODE-specific power saving (SAVE) state •  STALL is the SAVE state of HS-MODE •  SLEEP is the SAVE state of LS-MODE •  HS-MODE: STALL, HS-BURST •  LS-MODE (Type-I MODULE): SLEEP, PWM- BURST, LINE-CFG •  LS-MODE (Type-II MODULE): SLEEP, SYS- BURST
  21. 21. Data Bursts •  Data transmission occurs in BURSTs with power saving states between BURSTs •  BURST starts from the SAVE state •  Transition from DIF-N to DIF-P for period called PREPARE •  Generate SYNC Pattern •  Send Marker0 followed by mix of DATA0 - 255, Markers, FILLER •  Marker0 used for receiver alignment, similar to SKIP ordered sets in PCIe •  Burst ends with TAIL-OF-Burst Symbol 21
  22. 22. HIBERN8 •  HIBERN8 state enables ultra-low power consumption, while maintaining the configuration settings. •  A MODULE shall support HIBERN8. •  The M-TX shall be high-impedance in HIBERN8, •  M-RX shall hold the LINE at DIF-Z. •  Under these conditions, the M-RX is considered to be in squelch. •  When entering HIBERN8 from LS-MODE or HS-MODE, the Protocol Layer shall not request a MODULE exit HIBERN8 before a minimum period in HIBERN8 of THIBERN8, •  THIBERN8, is the larger of local TX_Hibern8Time_Capability and remote RX_Hibern8Time_Capability. •  Optional calculations of HIBERN8 based on the implementation •  (see the spec for additional details) 22
  23. 23. MIPI Universal Protocol (UniPro)
  24. 24. MIPI UniPro •  MIPI specification to the define protocol used to transfer data between Devices that implement the UniPro Specification. •  This includes definitions of data structures, such as Packets and Frames, used to convey information across the Network. •  Flow control, error handling, power and state management, and connection services are also defined in this specification •  UniPro version 1.61, the use of M-PHY is mandated for chip-to-chip interconnections 24
  25. 25. Phy Adapter Layer - L1.5 •  PHY Adapter Layer is responsible for abstracting the details of the PHY technology, thus providing a PHY-independent interface (PA_SAP) to higher protocol layers. •  The PHY Adapter Layer provides bandwidth scalability by supporting up to four PHY Data Lanes per direction. •  Supports Asymmetrical Data Lanes •  When multiple Data Lanes are available, they are assumed to have identical capabilities. •  Lanes are assumed to be in the same state, and L1.5 handles all details of how the Lanes are used autonomously. 25
  26. 26. L1.5 Protocol •  The L1.5 for M-PHY automates a significant part of the required steps used for Power Modes control, utilizing an L1.5-to-L1.5 communication protocol known as PACP (PHY Adapter Control Protocol). •  PDUs (“PACP frames”) generated by L1.5 are multiplexed with the symbol stream received from L2 and can be recognized by a unique header pattern. 26
  27. 27. L1.5 Power States and Power Modes •  The difference between Power States and Power Modes are as follows: •  An Application can set only a Power Mode, but cannot set a Power State •  An Application can get a Power Mode and get a Power State •  the gettable value of a Power Mode simply reflects the value that was set •  the gettable value of a Power State may change spontaneously when in FastAuto_Mode or SlowAuto_Mode 27
  28. 28. PACP Capability Exchange 28
  29. 29. Layer 1.5 Example – PACP_PWR_REQ 29 Used for power mode changes
  30. 30. Data Link Layer – L2 •  The Data Link Layer provides reliable Links between a transmitter and a directly attached receiver •  Multiplexes and arbitrates multiple types of data traffic (priorities) •  Data Link Layer clusters the 17-bit PA_PDU symbols into Data Frames •  Every Data Frame consists of a 1-symbol header, a payload of up to 144 symbols and a 2-symbol trailer including a 16-bit CRC. 30
  31. 31. •  Network Layer is to allow data to be routed to the proper destination in a networked environment. •  Network Layer introduces a new PDU known as a Packet •  When a Packet is passed down to L2, the Packet is encapsulated between an L2 header and an L2 trailer to form a single L2 Frame •  UniPro supports Networks of up to 128 Devices 31 Network Layer – L3
  32. 32. Transport Layer L4 •  Transport Layer is the highest UniPro protocol layer •  Transport Layer mechanisms allow a single physical Packet stream between two Devices to support multiple, independent, logical Packet streams or “Connections”. •  Transport Layer supports multiple bidirectional Connections •  Connections can span a single hop or multiple hops using Switches •  Switches not yet defined by the UniPro spec •  UniPro guarantees that data sent over a single Connection arrives in the order in which it was sent 32
  33. 33. Preemption (UniPro) •  In order to reduce delays in the transmission of high priority Frames and to improve QoS in conjunction with upper layers, the DL Layer can insert high priority Frames within a low-priority Data Frame if the latter one is already in transmission. •  This functionality is known as preemption of a Frame. Support of preemption functionality is optional for the transmitter, whereas the receiver shall always be able to receive preempted and non-preempted Frames. 33
  34. 34. Preemption (UniPro) •  Uses COF – Continuation of Frame header 34 This Frame consists of 2 fragments, the second fragment star0ng with COF
  35. 35. Universal Flash Storage (UFS) JEDEC
  36. 36. UFS – Universal Flash Storage •  Universal Flash Storage – JEDEC Standard JESD220C •  Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial interface. •  It is primarily used in mobile systems, between host processing and mass storage memory devices. •  M-PHY and UniPro make up the interconnect for UFS •  UFS is architected on SCSI SAM •  UFS uses the command layers from SCSI SPC and SBC 36
  37. 37. Why UFS? 1. Be5er User Experience: •  Higher performance, efficiency & responsiveness - Leading to Instant ON, Mul0-Tasking, Fast app loading and swapping •  Low Power – Longer BaQery life even with larger screens and mul0-tasking •  Security and Reliability – Enterprise applica0on support and Secure Mobile shopping •  Small and Scalable – Thinner and lighter devices 2. Easier technological integra>on: •  SoTware compa0bility with the wide spread SCSI framework - UFS 2.0 Specifica0on follows the SCSI programming model enabling soTware reuse •  Simpler Host design due to the well-defined UFS Host controller interface (UFSHCI) specifica0on •  Apart from these UFS 2.0 requires only single UniPro Transport layer CPort and does not use the built in end-to-end flow control capabili0es of UniPro. It does not require the low latency TC1 support or Pre- emp0on. This leads to simplifica0on of the MIPI UniPro controller design as well. 3. Be5er u>liza>on of bandwidth: •  JEDEC UFS is able to fully u0lize the duplex bandwidth provided by the MIPI UniPro transport. 37
  38. 38. UFS Architecture 38
  39. 39. Physical Layer •  UFS interface can support multiple lanes. •  Each lane consists of a differential pair. •  Basic configuration is based on one transmit lane and one receive lane. •  Optionally, a UFS device may support two downstream lanes and two upstream lanes. An equal number of downstream and upstream lanes shall be provided in each link. •  Links must be symmetrical 39
  40. 40. Application Layer •  The application layer consists of the UFS Command Set layer (UCS), the device manager and the Task Manager •  The UCS will handle the normal commands like read, write, and so on. •  UFS may support multiple command sets. •  UFS is designed to be protocol agnostic. This version UFS standard uses SCSI as the baseline protocol layer. •  A simplified SCSI command set was selected for UFS. •  UFS Native command set can be supported when it is needed to extend the UFS functionalities. •  The Task Manager handles commands meant for command queue control. •  The Device Manager will provide device level control like Query Request and lower level link-layer control. 40
  41. 41. SCSI Read Command 41 SCSI Level UTP Level
  42. 42. SCSI Write Command 42 SCSI Level UTP Level
  43. 43. Debugging M-PHY Problems
  44. 44. Debug process for Serial Protocols 44 Analyze and find root cause Pick the correct tool Iden0fy the Layer
  45. 45. Debugging M-PHY problems •  Typically M-PHY production systems are chip to chip, no connector •  Development systems may have SMA connections between devices •  First challenge is to access link •  Probing Type: •  SMA •  Multi Lead •  Midbus •  Check electrical first before debugging protocol problem 45
  46. 46. Probing Options •  Identify the appropriate probing solution •  SMA •  Multi-Lead – Solder Down 46 Mul0-Lead Solder Down SMA
  47. 47. Using the correct tool •  Is problem related to Signal Integrity? •  Are devices physically connected? •  Are both devices providing M-PHY compliant signaling? •  Use an Oscilloscope to verify •  Is problem related to Connectivity •  Is a link established between the 2 devices? •  Is the data rate as expected? •  Can software see the devices – •  for UFS, can the storage be seen? •  Use a Protocol analyzer to verify 47
  48. 48. Which Layer is causing the problem? •  Same principle applies regardless of MIPI M-PHY upper layer protocol •  Identify the layer •  Performance? •  Reliability? •  Errors? 48
  49. 49. Protocol Analyzer sees nothing? •  Is there a signal present? •  Connect the analyzer probe output to an Oscilloscope to verify. 49
  50. 50. •  Is there a signal present? •  Connect the analyzer probe output to an Oscilloscope to verify. Protocol Analyzer sees nothing? 50 DUT
  51. 51. •  Is there a signal present? •  Connect the analyzer probe output to an Oscilloscope to verify. Protocol Analyzer sees nothing? 51 DUT
  52. 52. Set Up Trigger •  What to trigger on? •  Depending on layer, trigger condition may vary •  Look for PACP on Boot to see initialization •  Higher level SCSI trigger for looking at software problem 52 SCSI Op Code
  53. 53. Protocol Issues – Look at upper layers 53
  54. 54. References •  M-PHY Specification v4.0 •  MIPI UniPro Specification v1.61 •  JEDEC Spec JESD220C (UFS) rev 2.1 56

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