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MIPI DevCon 2016: Using MIPI Conformance Test Suites for Pre-Silicon Verification

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MIPI Alliance conformance test suites provide a valuable set of tools improving interoperability of MIPI specification-based products. While the main purpose of conformance test suites is to verify conformance of these products at post-silicon stages, a significant number of these tests can be used in pre-silicon verification of MIPI-based designs in order to improve the product quality and increase confidence for being spec-conformant in very early design stage. This presentation by Ofir Michaeli of Cadence Design Systems focuses on the following topics: selection of appropriate CTS tests for pre-silicon verification, integrating CTS tests into the verification plan, and modification of the verification test bench to accommodate CTS tests. These topics are explained by the examples of integration of DSI, D-PHY and C-PHY conformance test suites into verification plans and would be relevant for every engineer who designs or verifies MIPI-based interfaces.

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MIPI DevCon 2016: Using MIPI Conformance Test Suites for Pre-Silicon Verification

  1. 1. Using MIPI Conformance Test Suites for pre-silicon verification Ofir Michaeli MIPI VIP R&D Team Leader Cadence Design Systems, Inc.
  2. 2. Agenda •  Compliance Verification Concerns •  MIPI CTS – what is it? •  Pre-Silicon verification principles •  The 4 steps for Compliance testing •  Using the MIPI CTS for pre-silicon verification •  Lesson learned from real life projects 2
  3. 3. Compliance Verification Concerns •  “How do we know that all spec related scenarios have been covered?” •  “How do we create tests to cover all these scenarios?” •  “After running the tests, some areas are still not covered. How do I retarget the tests to fill the holes?” •  “The spec has changed, how do I apply the change while ensuring nothing has broken?” 3
  4. 4. MIPI CTS – what is it? •  List of tests that complements the specification and enables measurement of conformance •  Used for interoperability testing at official Lab (Post Silicon) •  Covers all specification main flows •  Product must pass conformance testing to be on the Integrators List •  NOT a comprehensive verification plan 4
  5. 5. MIPI CTS – what is it? 5 UniPro Example Purpose Spec ref Test scenario Expected results
  6. 6. !  SW model, based on the MIPI specification !  Designed to run against RTL implementation at cycle accurate level Pre-Silicon Verification of standard interface Simulation (SW) Verification/ Design engineer HW Simulator EnginePCIe model/ VIP ‘Physical view’ Copyright © 2012, PCI-SIG, All Rights Reserved MIPI
  7. 7. The Four Steps to Compliance •  Based on MIPI Specification 7 Define and refine your completeness criteria based on the spec/CTS Create self –checking logic in your testbench Create intelligent sAmuli generator Assess and report status of completeness Done?
  8. 8. The Four Steps to Compliance •  Based on MIPI Specification 8 Define and refine your completeness criteria based on the spec/CTS Create self –checking logic in your testbench Create intelligent sAmuli generator Assess and report status of completeness Done?
  9. 9. Defining completeness criteria based on MIPI CTS (MIPI D-PHY example) 9 What does it take to verify it?
  10. 10. Defining completeness criteria based on MIPI CTS (D-PHY example) 10 VerificaAon plan for D-PHY Escape mode scenarios All permutaAons required to ensure compliance ‘Grade’ that shows the progress based on actual traffic over the D-PHY interface
  11. 11. The Four Steps to Compliance •  Based on MIPI Specification 11 Define and refine your completeness criteria based on the spec/CTS Create self –checking logic in your testbench Create intelligent sAmuli generator Assess and report status of completeness Done?
  12. 12. Self–checking logic: MIPI UniPro Example 12 CTS test if (result) { if (should_set_rreq_bit_on_nac()) { CDN_MIPI_UNIPRO_CHECK_THAT error_id = ERR_CDN_MIPI_UNIPRO_DLL108_NO_NAC_WITH_CLEARED_RREQ_WHEN_EXPECTED, condiAon = not (frame.direcAon == TRANSMIT and frame.ctrl_id != NAC and should_send_a_nac(CHECKING) and nac_sending_tolerance_passed() and should_set_rreq_bit_on_nac()), spec_secAon = "UNDEF", relevant_di = frame, err_msg = append ("Should send a NAC frame with rreq bit cleared, but instead sending ", frame); }; AutomaAc Monitor check
  13. 13. The Four Steps to Compliance •  Based on MIPI Specification 13 Define and refine your completeness criteria based on the spec/CTS Create self –checking logic in your testbench Create intelligent sAmuli generator Assess and report status of completeness Done?
  14. 14. Intelligent stimuli generator Example – MIPI D-PHY Example 14 Test Scenario: 1.  Configure the Test Setup to transmit a valid image or video sequence to the DUT. 2.  Modify the sequence by inserBng an LP-11/10/00/01/11 invalid Escape Mode Entry sequence between HS bursts on the Data Lane (keeping all other necessary video Bmings intact, as needed), and re- transmit the sequence to the DUT. 3.  Repeat the previous step for LP-11/10/11/11/11. Randomize Invalid Escape mode and Aming Randomize Image/Video sequence content Randomize different orders
  15. 15. The Four Steps to Compliance •  Based on MIPI Specification 15 Define and refine your completeness criteria based on the spec/CTS Create self –checking logic in your testbench Create intelligent sAmuli generator Assess and report status of completeness Done?
  16. 16. Assess and report status of completeness 16 100% coverage? DONE!
  17. 17. Summary •  CTS are aimed for post silicon interoperability testing •  It can be leveraged for pre-silicon verification •  Use each CTS scenario as reference for the 4 steps for compliance: •  Completeness criteria: executable and measurable •  Self–checking logic: Based on the expected results of the CTS test •  Intelligent stimuli generator: to cover all relevant CTS scenarios •  Report status of completeness: To show clear view of the progress for each CTS test 17

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