MIPI DevCon 2016: Meeting Demands for Camera and Sensor Interfaces in IoT and Automotive Applications
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Enhanced IoT and automotive applications are driving demand for multiple camera interfaces to enable embedded vision use cases. In this presentation, Synopsys' Hezi Saar outlines typical camera and display use cases for automotive and IoT applications, and how multiple Rx and Tx image streams can be integrated into an SoC to create a flexible and reusable architecture. The presentation will also provide a quick overview of the MIPI CSI-2 and I3C specifications and their key features that are important to meeting the required functionality, performance and power targets.
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MIPI DevCon 2016: Meeting Demands for Camera and Sensor Interfaces in IoT and Automotive Applications
- 1. Meeting Demands For Camera and Sensor Interfaces in IoT and Automotive Applications Hezi Saar Synopsys, Inc.
- 2. Agenda • Implementation of MIPI interfaces in mobile applications and beyond • Advantages of implementing MIPI interfaces • MIPI CSI-2, MIPI DSI, MIPI D-PHY, MIPI I3C • SoC design considerations • Summary
- 3. MIPI Display & Camera Interfaces Mobile Applications • MIPI CSI-2 and MIPI DSI protocols enable application- optimized SoCs primarily used in mobile electronics • Use of multiple cameras and displays for beyond traditional mobile applications
- 4. MIPI Interfaces in New Applications Automotive, IoT/Wearables, Virtual/Augmented Reality
- 5. MIPI Camera & Display Interfaces in IoT Linux/Rich OS Ext Flash Memory Controller LPDDR eMMC ARC HS Processor HMI MIPI DSI GPU Communications Bluetooth Smart SDIO USB Vision MIPI CSI-2 Vision Processor On-Chip Memories ROM SRAM Sensor & Control Subsystem Processor ADC MIPI I3C / I2C SPI Security Secure Core Private Key Public Key Accelerator True Random Number Generator Crypto Accelerators Logic Libraries • MIPI DSI, MIPI CSI-2, MIPI I3C • LPDDR, eMMC, ADC, BT, USB • Embedded Vision • Security • Sensor Fusion Point-of-Sale IC
- 6. Advanced Driver Assistance Systems (ADAS) A Rapidly Evolving Technology • Passive Driver Assistance Systems • Back-up camera system • Distance alert system • Active Driver Assistance Systems • Back-up camera w/ ID & breaking • Collision avoidance
- 7. Example: Surround View Using MIPI CSI-2 Image Sensors & MIPI DSI Display Rear Camera Display CAN Interface MPU Proprietary, LVDS or Ethernet Switch DRAM Flash Memory Power Supply Front Camera Module Left Camera Module Right Camera Module Rear Camera Module Other Camera Module Vbat LVDS or Ethernet Link MIPI CSI-2 Image Sensors MIPI DSI Display Front Camera Left Camera Right Camera Other Camera Module
- 8. Typical Automotive SoC High-End ADAS Infotainment • MIPI DSI, MIPI CSI2, MIPI I3C, MIPI SoundWire • LPDDR4, Ethernet AVB, HDMI, PCIe, SATA, ADC • Embedded Vision • Security • Sensor Fusion • Requires FuncEonal Safety • MIPI DSI, MIPI CSI2, MIPI I3C , MIPI SoundWire • USB, LPDDR4, Ethernet AVB, HDMI, PCIe, SATA, ADC • eMMC -> UFS • Real-Eme MulEmedia • Security • Sensor Fusion I3C I3C I3C MIPI D-PHY MIPI D-PHY
- 9. Augmented, Virtual, Mixed Reality Enterprise Use-Cases
- 10. Virtual Reality System Teardown HTC Vive Source: iFixit
- 11. Examples of New Use-Cases MIPI Display, Camera & Sensor Interfaces
- 12. Microsoft HoloLens Processing Unit • Processor packaged together with 1GB LPDDR3 and Intel Atom x86 processor • Uses 5 camera interfaces, depth and motion sensor for image identification and processing, recognizing gestures (*) Source: EETimes analysis (*) Source: MicrosoR
- 13. ADVANTAGES OF THE MIPI SPECIFICATIONS MIPI CSI-2, MIPI DSI, MIPI I3C
- 14. MIPI CSI-2 Over MIPI D-PHY CSI-2 Device D - P H Y CSI-2 Host D - P H Y Clk+ Clk- L0+ L0- Clk+ Clk- L0+ L0- L1+ L1- L1+ L1- Frame Buffer CSI-2 TransmiYer Packet Builder Lane DistribuEon CCI Slave SCL SDA SCL SDA CCI Master CSI-2 Packet CSI-2 Packet D-PHY HS Burst D-PHY HS Burst CSI-2 Receiver Packet Decoder Lane Merger CSI-2 Packet CSI-2 Packet Frame Buffer CRC D T WC ECC Payload byte size Data CRC processing ECC protecEng the header Data Format DefiniEon Virtual Channel IdenEficaEon Packet Builder
- 16. Virtual Channels Virtual Channel 0 – Line 0 Virtual Channel 0 – Line 1 Virtual Channel 0 – Line 2 Virtual Channel 0 – Line 3 Virtual Channel 0 – Line 4 Virtual Channel 0 – Line N Virtual Channel 1 – Line 0 Virtual Channel 1 – Line 1 Virtual Channel 1 – Line 2 Virtual Channel 1 – Line 3 Virtual Channel 1 – Line 4 Virtual Channel 1 – Line M
- 17. DSI SPacke t DSI SPacke t CRC WC ECC Payload byte size Data CRC processing ECC protecEng the header Data Format definiEon Virtual Channel IdenEficaEon Packet Builder – LONG Packet MIPI DSI over MIPI D-PHY Example: DSI Video Example - DPI D - P H Y D - P H Y Clk+ Clk- L0+ L0- Clk + Clk- L0+ L0- L1+ L1- L1+ L1- DSI TransmiYer Packet Builder Lane DistribuEon DSI Receiver Packet Decoder Lane Merger VSS HSE DATA0 ECC ECC ProtecEng the Short Packet Data Format DefiniEon Virtual Channel IdenEficaEon Packet Builder – SHORT Packet DATA1 D-PHY HS Burst D-PHY HS Burst DSI LPacket Valid Image Line DSI SPacke t VSS DSI SPacke t HSE D-PHY HS Burst D-PHY HS Burst D-PHY HS Burst D-PHY HS Burst DSI LPacket Valid Image Line
- 18. MIPI D-PHY Architecture The Popular Physical Layer Used for MIPI CSI-2 & MIPI DSI Protocols • Synchronous Forwarded DDR clock link architecture • One clock and multiple data lanes configuration • Static/dynamic de-skew supported through calibration • Calibration hand-shake not supported • No encoding overhead Two Data Lane Configura0on • Low-power and high-speed modes • Primarily targeting camera and display • Spread spectrum clocking supported for EMI/EMC considerations • Large eco-system, proven in millions of phones, cars
- 19. Benefits and Evolution of MIPI D-PHY • Higher data rate enables ultra-high-definition cameras and displays • Easier adaption of newer technologies • Backward compatible • Reliable with sufficient margins • New specs augment existing ecosystem • Growing market applications and segments • Longer channel length
- 20. MIPI I3C Specification Overview Types of Devices in an I3C System • MIPI I3C main master • MIPI I3C secondary master(s) • MIPI I3C slave(s) • I2C slave(s)
- 21. Examples of MIPI I3C Use-Cases Sensor Hub Sensor Subsystem Image Sensors
- 22. MIPI I3C Sensor Hub Use Case • The I3C bus has a secondary master that acts as a hub • Takes ownership of the I3C bus and communicates to the sensors directly • As soon as the secondary master has the relevant sensor data available on its I3C bus, it can communicate to the main master, which propagates the data to the CPU
- 23. MIPI CSI-2 Use of MIPI I3C for Control & Always-ON Imaging • Supports advancements in imaging for new applications: Health, Convenience, Security, Lifestyle, Efficiency • Camera Controller Interface (CCI) and Always-ON advancement considerations using I2C and future MIPI I3C
- 24. MIPI CSI-2 Use of MIPI I3C for Control & Always-ON Imaging • Supports advancements in imaging for new applications: Health, Convenience, Security, Lifestyle, Efficiency • Camera Controller Interface (CCI) and Always-ON advancement considerations using I2C and future MIPI I3C
- 26. MIPI CSI-2, MIPI DSI & MIPI D-PHY Technical Considerations • Bandwidth required • D-PHY version/speed, number of ports and lanes • Determine optimal interfaces to Tx/Rx image for memory storage or image • Configuration & interrupts • Memory usage
- 27. Target Multiple Applications with Flexible SoC Implementation MIPI CSI-2 Host Controller MIPI CSI-2 Host Controller MIPI CSI-2 Host Controller MIPI CSI-2 Host Controller 2Lane MIPI D-PHY 2Lane MIPI D-PHY 2Lane MIPI D-PHY 2Lane MIPI D-PHY Applica7on A Applica7on B OR
- 28. Form Factor Reference Channels Variety of Applications
- 29. MIPI CSI-2, MIPI DSI, MIPI I3C & MIPI D-PHY IP • Complete, Production-Proven, Interoperable
- 30. Summary • MIPI CSI-2, DSI, MIPI D-PHY and MIPI I3C • Leveraged for mobile and beyond – IoT, automotive and AR/VR • Synopsys provides complete camera, display and sensor interface IP • Enables new set of applications in automotive, AR/VR, IoT markets • Lowers integration risk for application processors, bridge ICs & multimedia co-processors • Future proof IP supporting variety of speeds, proven in silicon • Reduces cost and power for multiple instantiations • Testability features enable low cost manufacturing Industry’s first MIPI I3C Demo Visit the Synopsys Booth to See Our Demo Today!