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Interrupts_S05,interrupt vector table.ppt
- 1. 1 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupts Nurudeen Olayiwola Thomas Gutierrez • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example • Non-maskable interrupts • Conclusion
- 2. 2 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Question?? • When you are at home sitting on your lazy boy, how do you know when someone wants to talk to you on the phone? – Do you periodically get up and pick up the phone to see if someone is there? – Or do you wait till the phone rings to answer it? • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 3. 3 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Answer? • The first scenario shows a person doing what is known as polling. • The second case illustrates an interrupt-driven person. • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 4. 4 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Polling • AKA “busy waiting”; looping program • Continues checking status register until a particular state exists • “Are we there yet? Are we there yet? Are we there yet?” • What happens if something occurs at other devices while the processor is busy waiting?? • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 5. 5 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupt • Device sends a special signal to CPU when data arrives. • “Wake me up when we get there.” • Responds to hardware interrupt signal by interrupting current processing. • Now CPU can perform tasks before and after interrupt instead of just polling!! Good! • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 6. 6 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion General Interrupt Flow 1. Completes current instruction 2. Saves current state to status registers 3. Identify source 4. Jump to and activate Interrupt Service Routing (ISR) 5. Return to original program (RTI) and restore state Register Interrupt driven CPU I/O device I/O device • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 7. 7 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupts: Flow Chart SOFTWARE INTERRUPT STACK MPU REGISTER CONTENTS SET APPROPRIATE BIT IN CCR LOAD INTERRUPT VECTOR INTO PROGRAM COUNTER VECTOR TABLE HARDWARE INTERRUPT MASK SET? N Y EXECUTE INTERRUPT SERVICE ROUTINE $FFC0 $FFFF CONTINUE MAIN PROGRAM • General Info
- 8. 8 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Brief Background • Univac 1103/1103A (1953-56) – first recognized CPU with interrupts. Current instruction was stored in memory and program counter loaded with a fixed address. • Other notables: – IBM (1954) – first to use interrupt masking – NBS DYSEAC (1954) – first with I/O interrupts • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 9. 9 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Purpose/Applications • To modify or do additional instructions based on internal requests and/or external devices. • Provide a means for suspending current instructions for more important tasks. • Hardware (called Interrupts or Resets) – Reset – User-defined interrupt – Timer operations – CPU operations monitor failure • Software – Illegal instruction – SWI • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 10. 10 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Purpose/Applications (cont.) • Coordinating I/O operations • Notifies the CPU that an input is ready or an output can be changed • Timing • Periodic (clock-driven) interrupts remind the CPU of the passage of time • Multi-tasking • Updating counters • Timing during interactive programs • Errors • Interrupts can notify of error situations • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 11. 11 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Purpose/Applications (cont.) • Practical uses/examples • Change direction of a motor. • Auto wiper speed increased or decreased. • Pressing a pause button on a VCR • HC11 controlled transmission system • Etc. • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 12. 12 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Types of interrupts • Ignorable interrupts (or Maskable) – Most often used – Good for using when computer needs to do something more important – When the interrupt mask is set, interrupts are hidden and therefore are ignored. • Non-ignorable interrupts (Non- maskable) • NMI’s take precedence and interrupt any task • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 13. 13 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupt Vector Table • When an interrupt occurs, control of the program moves to the interrupt handling routine – Event similar to subroutine – How do we know where the handler routine is though?? • The address of the handler is provided by the interrupt vector table – IVT has one entry for each type of interrupt – Each entry is indexed by interrupt type, and includes a pointer to the handler • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 14. 14 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Interrupt Vector Table Maskable when the I- bit of CCR is set Unmaskable lowest priority highest priority • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 15. 15 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Maskable/Unmaskable • 6 Non-Maskable – always interrupt the program execution • 15 Maskable – can enable or disable by mask bits – HOW? • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 16. 16 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Stacking order When an interrupt occurs: 2. HC11 pushes on stack: PC, accumulators and registers, CCR 3. HC11 sets the I-bit Masks interrupts - can’t interrupt an interrupt 4. Looks up vector of highest-priority interrupt 5. Branches to interrupt service routine Executes until RTI is encountered 6. Restores accumulators and registers, CCR from stack (note: this includes restoring the I-bit of CCR) 7. Returns to instruction after the one that was interrupted (note: other interrupts may be pending now) 1. Finish execution of the current instruction Note: Non-maskable interrupts and resets happen immediately SP-9 SP-8 SP-7 SP-6 SP-4 SP-5 SP-3 SP-1 SP-2 SP-0 CCR ACCB ACCA IXH IXL IYH IYL PCH PCL • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 17. 17 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Controlling Interrupts: The I-bit • Exists as bit 4 in the Condition Code Register (CCR) – When set (I=1), interrupts will be inhibited and placed as pending – When cleared (I=0), interrupt servicing will be allowed when asked • The I bit is always set while servicing an interrupt; Interrupts can’t nest • Set during RESET to allow minimum system initialization • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 18. 18 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Controlling Interrupts: The I-bit • Can also be set by software to prevent execution of maskable interrupts – SEI (SEt Interrupt Mask) • Can be cleared by software instructions – CLI (CLear Interrupt Mask) • Automatically cleared by RTI instruction • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 19. 19 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Maskable Interrupt: HPRIO • Can elevate the priority of one of the maskable interrupts. • Uses bits 0-3 of HPRIO (Highest PRIOrity Interrupt Register) • Default is IRQ. • Can be set at anytime during program as long as I bit is set. • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 20. 20 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Maskable Interrupt: IRQ • Highest priority maskable interrupt • IRQ pin provides additional external interrupting source • Other additional MCU pins can be used as interrupt inputs: – Example: • XIRQ input • Main-Timer Capture Pins • Pulse Accumulator Pin • IRQE Bit in the OPTION control used to specify IRQ pin configuration – IRQE = 0 -> Low level sensitive – IRQE = 1 -> Low-going edge sensitive (single source only) • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 21. 21 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Maskable Interrupt: IRQ • Controlled by a pin on the HC11 • A low signal will initiate interrupt sequence OPTION $1039 7 6 5 4 3 2 1 0 ADPU CSEL IRQE DLY CME CR1 CR0 0 1 IRQE = IRQ Select Edge Sensitive Only (Time Protected) 0 = IRQ configured for low LEVEL (default) 1 = IRQ configured for falling EDGEs • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 22. 22 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Non-maskable Interrupt: XIRQ • Enabled by TAP instruction by clearing X-bit upon system initialization • After being cleared, software cannot set the X-bit, thus XIRQ is non-maskable. • Higher priority than any source maskable by the I-bit. • Both the X and I bits are automatically set by hardware after stacking the CCR. • RTI restores X and I bit to pre-interrupt states • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example • Non-maskable interrupts
- 23. 23 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Non-maskable Interrupt: SWI • Software instruction, thus cannot be interrupted until completed • Uninhibited by global mask bits in the CCR • Similar to other interrupts, sets the I- bit upon servicing • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example • Non-maskable interrupts
- 24. 24 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Example - IRQ handler IRQHANDLE ORG $3000 ldaa count ; A <-- current count inca ; increment count staa count ; write back count ldx #msg ; print out msg jsr OUTSTRG ldx #count ; print out count jsr OUT1BYT rti ; all done – return org $2000 ; data section msg fcc “Number of times button pressed:” fcb $04 count fcb 0 ; button counter org $00ee JMP IRQHANDLE org $2200 ; main program cli ; enable interrupts loop bra loop ; endless loop 1. Write the IRQ handler routine IRQ vector at $FFF2 3. Do-nothing program! 2. Write the initialization and main routine >>Whenever button is pushed, update a counter and print out the current count • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example
- 25. 25 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion The SIX untouchables: NONMASKABLE • RESET • CLOCK MONITOR • COP Watchdog • Illegal Opcode • XIRQ • SWI • Conclusion • Conclusion
- 26. 26 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Advantages and Disadvantages • Advantage 1. Efficient, better than polling 2. Multitasking • Disadvantage 1. They can occur randomly 2. Requires additional hardware, sometimes • Conclusion • Conclusion
- 27. 27 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion Questions?? • General Info • Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Example • Conclusion
- 28. 28 • General Info •Purpose/ Applications • Interrupt Priority/ IVT • Controlling Interrupts • Maskable interrupts • Non-maskable interrupts • Example • Conclusion References http://courses.cs.tamu.edu/cpsc462/ walker/Slides/Exceptions_Interrupts_1.ppt http://oa-003.spu.edu/bolding/ee3280/nosound/16-Exceptions. ppt Previous semester presentations…