1. A Family of MPEG Video Encoder and Decoder Chips
optimized for consumer applications
Martin Bolton
SGS-Thomson Microelectronics
Grenoble, France
Summary
• Design Strategy: Architecture, Hardware/Software Partitioning
• MPEG Video Overview
• The generic architecture
• MPEG 1/H.261 decoders
• MPEG1 encoder
• MPEG2 decoder for TV applications
5.3.1
2. Design Strategy
• Architecture
• goal is to minimize area and power consumption by:
• keeping clock frequencies as low as possible
• "distributing control, only clocking operators when necessary
• constraining programmability to the needs of a single application
• Technology
- ASIC methodology: standard cells and application-specific macrocells
· Synthesis used where advantageous
- CMOS 0.7 micron technology, direct migration path to 0.5 micron/3.3V
• Hardware/Software Partitioning Criteria
- on chip:
• in standard microcontroller:
high compution rate (high-rate operations)
limited flexibility (fixed by standard)
real-time constraints
low compution power (low-rate operations)
high fexibility (application-dependant)
lower real-time constraints
•
Hardware/Software Partitioning
MPEG hierarchy
5.3.2
Sequence
Group of Pictures
Picture
Slice!
Sequence of Macroblocks
Macroblock
Block
Software
- - - - - -,- - - - - - - .
Hardware
3. Generic Architecture
Pixel
InpUV
Display
Video
Interface
Shared Memory
("Local Memory")
Filter, Q, 10. Run/Level Coder
("Pipeline")
Set-Up
Parameters
Address
Control
Header
Processing,
VLCNLD,
Local
Memory
Controller
Compressed
Data
To Controlling
Micro
MPEG/H.261 Video Decoders
Main Features
• Real-time decoding for MPEG1 SIF and H.261 ("p X 64")
SIF: 352 X 240 @ 29.97 Hz. 352 X 288 @ 30 Hz
H.261 CIF: 352 X 288 @ 29.97 Hz
• Die size 72 sq mm (no OCT). 85 sq mm (with OCT)
• Power consumption 0.25 W, max ext clock freq 48/50 MHz, 144-pin PQFP package
• Single external memory (DRAM) holds picture buffers and bit buffer
• Low demand on controlling micro (5% of standard 16-bit micro)
5.3.3
4. Decoder System Block Diagram
OCT
-
.
,
256K X 16
DRAM
ICf
, DO -016
•
Decoder
Host Bus
-
'-
Video
Timing
Generator
D-A
converters
Syncs
--Ｎｾ
-
Display
Interface
Storage medium
or communications
interface
Microprocessor
5.3.4
MPEG1 Decoder Die Photograph
___----------=-.(.-.._:__-"'-.J!l-:.---="-;;";''::...;-,'-".,...L..........;:.....
5. •
MPEG/H.261 Video Encoder
Main Features
• Real-time decoding for MPEG1 SIF and H.261 (lip X 64")
SIF: 352 X 240 @ 29.97 Hz, 352 X 288 @ 30 Hz
H.261 elF: 352 X 288 @ 29.97 Hz
• Designed to support range of encoder applications. trom minimum cost to bighe3t quality
• "Two-pass" encoding possible
• Bit-rate control system gives many user options
• Single external memory (DRAM) holds picture buffers and bit buffer
+
Ｍｾ ｾＢ ｾ
fi..../inlerpclator
The
Encoding
Process
contrOl
OCT
Jnv
o
tnv
oc
T
+
5.3.5
6. Encoder System Block Diagram
Search Window &reference block
.----------_.....l Video DRAM local memory
•
STI3220 vectors & decision
Microprocessor Interface
J.-..--- Sync
....---- Blanking
('--_----, Digital
Video1,....---J
Input
Compressed
Data, serial
output
MEC
Data _--1--------.1FWquest
ＺＧｵｾｩ _ _
Port L - . - -
RAM Interface
Encoder Architecture
•5.3.6
Microprocessor Interface
7. •
Bit Rate Control Principle
Picture
Bit Budget
uniform
allocation
NMU-by-NMU
allocation
e =bit eror
NMU =N-m3:;roblock unit
Quantizer =k X e
o Macroblocks
Bit-Rate Control Loop
ｐｾ
Margin
BitslNMU
Compressed
Data
t2
BitS/PIcture
Packer &
Bit Butter
Control
Bits/MB
VLC
Error ---r-------...,
FMdtlBdt o.in
(with poss. IoCIII
correclion)
ｾＢＢＢ｟ｾｚＲＦｒｌｃ
panic mode
,-- - - - - - - - - - - - - - - --,I mｾｳｴｲｵ･ｴｩｯｮ I
I Bit Bufler I
I I
I
I
I
I
I
Ouantizer
Second
Stage
ACI<J.l: :::l
Externally [}---o'ICalculated '
Os
(Inter and Intra)
Quantizer
Fl'St
Stage
!rom OCT
5.3.7
8. MPEG2 Video Decoder
• Architecture is a scaled version of the MPEG1 decoder
Memory bus extended from 16 bits to 64
External clock 55 MHz
• Real-time decompression of CCIR 601 (720 X 480/576) interlaced pictures
• Power consumption < 1 W. 144-pin PQFP ｰＳ｣ｫＳｊｾ
Additional Features
• Field- or frame-based prediction
• On-screen display
• Horizontal interpolation for format conversion
• Error concealment
MPEG2 Handles Interlaced Pictures
•
• Second field can be predicted from first
• A OCT performed on blocks from one fi31j
can often give fewer high frequency components
than a OCT performed on blocks containing data
from both fields.
5.3.8
field 1
field 2
