1. ECE 403
FINAL PROJECT
OPERATIONAL AMPLIFIER
DESIGN
ROBERT J. ROUSE
MONDAY, APRIL 26, 2012
N O R T H C A R O L I N A S T A T E U N I V E R S I T Y
E L E C T R I C A L A N D C O M P U T E R E N G I N E E R I N G
2. Contents
Design Specifications....................................................................3
Problem 1.........................................................................................5
Problem 2
Biasing Common Source Gain Stage........................................9
Problem 3
Analysis of voltage swing...........................................................10
Problem 4
Systematic offset...........................................................................13
Problem 5.......................................................................................14
Correction of systematic offset................................................14
Problem 6.......................................................................................15
Bode plot of Uncompenstated op amp.................................15
Problem 7.......................................................................................16
Design a Miller comp. Capacitor (CC)...................................16
Problem 10.....................................................................................17
Problem 11.....................................................................................19
Problem 12.....................................................................................20
Problem 13.....................................................................................21
3. DESIGN SPECIFICATIONS
The goal of this project is to design an operational amplifier implemented with p-type and n-type
MOSFETS. As the project designer, I will apply Johns & Martins, 0.8 µm, and minimum design rules to
determine the junction geometries for the n-type and p-type transistors. For this project I will refer to the
area of the drain and source by the following: ADrain and ASource. The area of both drain and source are
dependent upon the value of lambda. Lambda, 𝜆, refers to the minimum feature size within a transistor and
is equivalent to 0.8µm as defined in the project parameters.
ADrain = ASource = 5𝜆W.
The perimeter of the drain and source junctions have the following relationship to lambda:
PSOURCE = PDRAIN = 10𝜆 + W
Using, the 0.8𝝁m process design rules, the minimum feature size 0.8𝝁m and the gate length, L, is defined as
twice 2 𝜆. Therefore, the gate lengths will be equivalent in all n-type and p-type transistors.
𝐿 = 2𝜆 => 𝐿 = 2 ∗ (0.8µ 𝑚)
LNMOS=LPMOS=1.6µm
JUNCTION GEOMETRIES
WIDTH LENGTH (L) AD AS PD PS
NMOS 100 µm 1.6µm 800pm2 800pm2 208µm 208um
PMOS 200 µm 1.6µm 400 pm2 400 pm2 108 µm 108µm
Table 1: Area and Perimeter Geometries of MOSFETS
Table 2 is a listing of the properties of the operational amplifier design of defined by the project guidelines.
JUNCTION
GEOMETRIES
VTO
(V)
µO
(
𝑐𝑚2
𝑉 · 𝑠
)
TOX
(m)
LD
(m)
GAMMA PHI
(V)
NSUB
(cm3)
PB
(V)
CJ
(
𝐹
𝑚2
)
CJSW
(
𝐹
𝑚
)
MJ MJSW CGSO CGDO
NMOS 0.7 500 1.8e-8 6e-8 0.5 0.7 3e16 0.9 2.5e-4 2e-10 0.5 0.3 2e-10 2e-10
PMOS -0.9 175 1.8e-8 1.8e-8 0.8 0.7 7.5e16 0.9 4e-4 2.8e-10 0.5 0.3 2e-10 2e-10
Table 2: Level 3 Design Specifications
Using the values of TOX as defined through the project parameters, which are listed in the above table, I was
able to calculate the values of KP and KN.
𝐾𝑃 = 𝐶 𝑂𝑋 ∗ µ 𝑃 And 𝐶 𝑂𝑋 =
𝐾 𝑂𝑋∗𝞮
𝒕 𝑶𝑿
- tox, is the thickness of the oxide
- Kox, is the constant 3.9
- 𝞮 is the permittivity of free space
4. 𝐶 𝑂𝑋 =
(3.9)∗8.854𝑒−18
𝐹
𝑚
1.8𝑒−8 𝑚
𝐶 𝑂𝑋=1.918367 𝑥 10−9 𝐹
𝑚2
𝐾𝑃 = (1.918367 𝑥 10−9 𝐹
𝑚2
)( 17500
𝑚2
𝑉·𝑠
)
𝐾𝑃 = 33.75
µ𝐴
𝑉2
𝐾 𝑁 = 95.92
µ𝐴
𝑉2
In this section we have designed a Common-Source Amplifier.
Figure 1: Common-Source Gain Stage Amplifier
5. PROBLEM 1
Common Source Gain Stage
Figure 2: Common Source Gain Stage Vout=2.5 volts
The Common Gain Stage is the second stage of the operational amplifier. It is composed of a PMOS current
mirror, which is biased with a 100µA dependent current source. VDD is a 5volt DC voltage source that drives
the PMOS transistors makes up the current mirror. Transistors M6 and M7 will have a constant current of
100 µA due to the PMOS current mirror. As part of the project criteria we are asked to find the value of
VIN that result in a VOUT that is equal to 2.5 volts. Initially, I used PSpice to determine the gate voltage,
VIN, was equal to 881.1 mV. I then verified the result by analytically calculating the value of VGS assuming
active region of operation. The following equation describes the behavior for a NMOS transistor
operating in the active region or saturation region of operation.
ID = (
W
L
)Kn(VGS − VTN)2
100uA = (
100
1.6
)(95.9183
µA
V2
) (VGS − 0.7)2
VGS = 0.829154414 Volts
PSPICE OUTPUT
Analytically, I the value of VIN when VOUT was equal to 2.5 volts was equal to 0.8291544 volts dc.
**** 04/24/12 21:12:38 ******* PSpice 16.2.0 (Oct 2008) ******* ID# 0 ********
6. ** Profile: "SCHEMATIC1-common_source_vbias_Vout_equal_2.5v" [ K:ECE 403Final
ProjectCommon Source Gain Stagecommon source gain
****************************** CIRCUIT DESCRIPTION ***********************************
** Creating circuit file "common_source_vbias_Vout_equal_2.5v.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
.LIB "../../../common source gain stage-pspicefiles/common source gaing stage.lib"
* From [PSPICE NETLIST] section of C:CadenceSPB_16.2toolsPSpicePSpice.ini file:
.lib "nom.lib"
*Analysis directives:
.OP
.SAVEBIAS "common_source_gain_stage" OP
.OPTIONS LIST
.OPTIONS NODE
.OPTIONS NOOUTMSG
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source COMMON SOURCE GAING STAGE
I_I1 N00547 0 DC 100u
M_M6 VOUT N00547 VDD VDD Mbreakp
+ L=1.6u
+ W=200u
+ AD=800e-12
+ AS=800e-12
+ PD=208u
+ PS=208u
M_M7 VOUT VG7TEMP 0 0 MbreakN
+ L=1.6u
+ W=100u
+ AD=400e-12
+ AS=400e-12
+ PD=108e-6
+ PS=108e-6
M_M0 N00547 N00547 VDD VDD Mbreakp
+ L=1.6u
+ W=200u
+ AD=800e-12
+ AS=800e-12
+ PD=208u
+ PS=208u
V_Vin VG7TEMP 0 DC .881126 AC 0 0
V_V1 VDD 0 DC 5 AC 0 0
**** RESUMING common_source_vbias_Vout_equal_2.5v.cir ****
.END
**** 04/24/12 21:12:38 ******* PSpice 16.2.0 (Oct 2008) ******* ID# 0 ********
8. *************************** INDEPENDENT SOURCES *******************************
NAME NODES DC VALUE AC VALUE AC PHASE
V_Vin VG7TEMP 0 8.81E-01 0.00E+00 0.00E+00 degrees
V_V1 VDD 0 5.00E+00 0.00E+00 0.00E+00 degrees
I_I1 N00547 0 1.00E-04 0.00E+00 0.00E+00 degrees
************************************** MOSFETS ******************************************
NAME D G S B MODEL
(line 2) L AD PD RD RG M
(line 3) W AS PS RS RB
M_M6 VOUT N00547 VDD VDD Mbreakp
1.60E-06 8.00E-10 2.08E-04 0.00E+00 0.00E+00 1.00E+00
2.00E-04 8.00E-10 2.08E-04 0.00E+00 0.00E+00
M_M7 VOUT VG7TEMP 0 0 MbreakN
1.60E-06 4.00E-10 1.08E-04 0.00E+00 0.00E+00 1.00E+00
1.00E-04 4.00E-10 1.08E-04 0.00E+00 0.00E+00
M_M0 N00547 N00547 VDD VDD Mbreakp
1.60E-06 8.00E-10 2.08E-04 0.00E+00 0.00E+00 1.00E+00
2.00E-04 8.00E-10 2.08E-04 0.00E+00 0.00E+00
**** 04/24/12 21:12:38 ******* PSpice 16.2.0 (Oct 2008) ******* ID# 0 ******** ** Profile: "SCHEMATIC1-
common_source_vbias_Vout_equal_2.5v" [ K:ECE 403Final ProjectCommon Source Gain Stagecommon source gain
**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( VDD) 5.0000 ( VOUT) 2.5012 (N00547) 3.8708 (VG7TEMP) .8811
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_Vin 0.000E+00
V_V1 -2.023E-04
TOTAL POWER DISSIPATION 1.01E-03 WATTS
*** 04/24/12 21:12:38 ******* PSpice 16.2.0 (Oct 2008) ******* ID# 0 ********** Profile: "SCHEMATIC1-
common_source_vbias_Vout_equal_2.5v" [ K:ECE 403Final ProjectCommon Source Gain Stagecommon source gain
****OPERATING POINT INFORMATIONTEMPERATURE=27.000 DEG C
**************************************** MOSFETS ***************************************
NAME M_M6 M_M7 M_M0
MODEL Mbreakp MbreakN Mbreakp
ID -1.02E-04 1.02E-04 -1.00E-04
VGS -1.13E+00 8.81E-01 -1.13E+00
VDS -2.50E+00 2.50E+00 -1.13E+00
VBS 0.00E+00 0.00E+00 0.00E+00
VTH -9.00E-01 7.00E-01 -9.00E-01
VDSAT -1.85E-01 1.58E-01 -1.85E-01
Lin0/Sat1 -1.00E+00 -1.00E+00 -1.00E+00
if -1.00E+00 -1.00E+00 -1.00E+00
ir -1.00E+00 -1.00E+00 -1.00E+00
TAU -1.00E+00 -1.00E+00 -1.00E+00
GM 8.92E-04 1.13E-03 8.71E-04
GDS 1.42E-06 2.32E-06 2.12E-06
GMB 4.12E-04 3.28E-04 4.03E-04
CBD 2.04E-13 6.59E-14 2.59E-13
CBS 3.78E-13 1.22E-13 3.78E-13
CGSOV 4.00E-14 2.00E-14 4.00E-14
9. CGDOV 4.00E-14 2.00E-14 4.00E-14
CGBOV 0.00E+00 0.00E+00 0.00E+00
CGS 3.79E-13 1.89E-13 3.79E-13
CGD 0.00E+00 0.00E+00 0.00E+00
CGB 0.00E+00 0.00E+00 0.00E+00
JOB CONCLUDED
**** 04/24/12 21:12:38 ******* PSpice 16.2.0 (Oct 2008) ******* ID# 0 ********
** Profile:"SCHEMATIC1-common_source_vbias_Vout_equal_2.5v" [ K:ECE 403Final ProjectCommon Source Gain Stagecommon source
gain
**** JOB STATISTICS SUMMARY
Total job time (using Solver 1) = .09
The small signal parameter specifically transconductance are directly proportional to lambda. The value of
GDS is equal to
1
𝑅 𝐷𝑆
where 𝑅 𝐷𝑆 =
1
𝐼 𝐷 𝑆 𝜆
.
PROBLEM 2
BIASING COM M ON SOURCE GAIN STAGE
Biasing Point VOUT=2.5 Volts
d
Figure 3: Common Source Gain Stage Biased
10. PROBLEM 3
ANALYSIS OF VOLTAGE SWING
Figure 4: Differential Input Stage Circuit
The input voltages at the gates of Vg1 and Vg2 will determine the operational swing of the differential input
stage. Transistors Q1 and Q2 are connected to Q5 which is the second leg of the current mirror. In order
to calculate the swing of the differential input stage we need to find the point at which VS1 stops responding
to the small changes in the input. The swing of the differential input stage can be analyzed by determining
the small signal operation of this device. By directing our attention to the output node of the current mirror
where the voltages of the source of transistors, Q1 and Q2 are equivalent to the drain of transistor Q5.
𝑉𝑆𝑜𝑢𝑟𝑐𝑒1 = 𝑉𝑆𝑜𝑢𝑟𝑐𝑒 2 = 𝑉𝐷𝑟𝑎𝑖𝑛 5
The swing of the differential input stage can be analyzed by determining the small signal operation of this
device. The device has a constant slope between -1.02 Volts and 3.6845 Volts. However the differential is
active between -2 Volts and 4.10 Volt. Below I have detailed the relationship between the large signal
operation and the small signal operation of the differential stage.
11. Figure 5: Swing of the Differential Amplifier
Figure 6: Small Signal and Large Signal Relationship
12. In order for Q5 to remain in the saturation region of operation the drain voltage, VD5, must be less than its
source voltage, V5. If this condition is not met Q5 will transition from the active region into the triode
region of operation. Therefore the contributing voltages of the Vs3 or Vs4 cannot exceed a voltage that will
make the VD5 > VS5. The equations below will describe how the upper bounds on the input voltage were
analytically calculated.
𝑉𝑑𝑠5 < 𝑉𝑆5 + √(
2𝐼𝑑5
𝐾𝑝5
)
𝑉𝑑𝑠5 < 𝑉𝑠5 − √(
2𝐼𝑑5
𝐾𝑝5
)
𝑉𝑔1 − 𝑉𝑇𝑃 + √(
2𝐼𝑑1
𝐾𝑝1
) < 𝑉𝑠5 − √(
2𝐼𝑑5
𝐾𝑝5
)
𝑉𝑔1 < 𝑉𝑠5 − √(
2𝐼𝑑5
𝐾𝑝5
) + √(
2𝐼𝑑1
𝐾𝑝1
) + 𝑉𝑡𝑝
𝑉𝑔1 = 𝑉𝑐𝑚
𝑉𝑐𝑚 < 3.7781 𝑉𝑜𝑙𝑡𝑠
An additional bound occurs at on the limits of VCM is to ensure that transistor Q3 and Q4 are operating in the active region
of operation. The lower bound of VCM focuses on the relationship between VD5 and VS1 . The drain of the n-type
transistor Q3, is connected to the drain of the p-type transistor Q1. In addition, the two gates of the transistor are
connected by the VD1 and VD3. If the voltage drops below a value of effective voltage of the transistor VG3 and VG4 then
the transistors will enter the cutoff stage. Transistors Q3 and Q4 will not function and the differential stage of the circuit
will not function below this value of VCM, which is equal to VG1.
13. SYSTEM ATIC OFFSET
Figure 6: Affect of Systematic Offset on Q6
I picked 1.850 to be the midpoint of my swing. After solving for a bias point I obtained the following circuit. Upon
analysis of the circuit I did notice that the current flow through transistor Q6 and Q7 did were only half of the value
of the bias point current. The transistor, Q6, was not operating in the active region of operation due to the voltage at
the drain of the PMOS. To compensate for the systematic off set I increase the width of transistor Q6 so that it
would be in the saturation region of operation.
14. PROBLEM 5
CORRECTION OF SYSTEM ATIC OFFSET
I found that the width of Q6 was equal to 203µm using the following equation.
𝑉𝐺𝑆7 = √
2𝐼 𝐷6
𝐾𝑛 ∗ (
𝑊
𝐿
)7
+ 0.7
Figure 8: Width Adjustment of Transistor Q7
15. PROBLEM 6
BODE PLOT OF UNCOM PE NSTATED OP AM P
I was able to find the unity transition frequency, wta, which occurs when the gain of the amplifier is
equivalent to 1. The corresponding point on a log scale is the point where the magnitude crosses the x axis
zero therefore the corresponding point on the graph represents the wta frequency.
Figure 8: Original Frequency Response
The pole, wp1 is located at 29kHz and the unity transistion frequency is 360.89 MHz.
𝑤𝑡𝑎 = 2𝛱 ∗ 360 106 𝐻𝑧 and 𝑤𝑡𝑎 =
75398.2𝑟𝑎𝑑
𝑠𝑒𝑐
Wp1=2 𝛱 * 29 kHz => wp1=1.82212374e5 rad/sec
AV is equal to 101.49 dB and this value corresponds to a gain of 33.706385.
16. PROBLEM 7
DESIGN A M ILLER COM P. CAPACITOR (CC)
***************************************MOSFETS**************************************
NAME M_Q7 M_Q4 M_Q5 M_Q1 M_M6 M_M0 M_Q3 M_Q2
MODEL MbreakN MbreakN Mbreakp Mbreakp MbreakN Mbreakp MbreakN Mbreakp
ID 1.04E-04 5.04E-05 -1.01E-04 -5.04E-05 -1.04E-04 -1.00E-04 5.04E-05 -5.04E-05
GS 8.30E-01 8.30E-01 -1.13E+00 -1.59E+00 -1.13E+00 -1.13E+00 8.30E-01 -1.59E+00
VDS 1.27E+00 8.30E-01 -1.56E+00 -2.61E+00 -3.73E+00 -1.13E+00 8.30E-01 -2.61E+00
VBS 0.00E+00 0.00E+00 0.00E+00 1.56E+00 0.00E+00 0.00E+00 0.00E+00 1.56E+00
VTH 7.00E-01 7.00E-01 -9.00E-01 -1.43E+00 -9.00E-01 - 9.00E-01 7.00E-01 -1.43E+00
VDSAT 1.13E-01 1.13E-01 -1.85E-01 -1.36E-01 -1.85E-01 1.13E-01 -1.36E-01
Lin0/Sat1 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
if -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
ir -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
TAU -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
GM 1.59E-03 7.73E-04 8.79E-04 6.56E-04 9.06E-04 8.71E-04 7.73E-04 6.56E-04
GDS 3.26E-06 1.97E-06 1.79E-06 6.79E-07 1.18E-06 2.12E-06 1.97E-06 6.79E-07
GMB 4.67E-04 2.26E-04 4.06E-04 1.73E-04 4.19E-04 4.03E-04 2.26E-04 1.73E-04
CBD 8.11E-14 8.99E-14 2.37E-13 1.70E-13 1.77E-13 2.59E-13 8.99E-14 1.70E-13
CBS 1.22E-13 1.22E-13 3.78E-13 2.37E-13 3.78E-13 3.78E-13 1.22E-13 2.37E-13
CGSOV 4.06E-14 2.00E-14 4.00E-14 4.00E-14 4.00E-14 4.00E-14 2.00E-14 4.00E-14
CGDOV 4.06E-14 2.00E-14 4.00E-14 4.00E-14 4.00E-14 4.00E-14 2.00E-14 4.00E-14
CGBOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGS 3.84E-13 1.89E-13 3.79E-13 3.79E-13 3.79E-13 0.00E+00 3.79E-13 3.89E-13
CGD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGB 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
I was however able to obtain a phase margin, ΦM, of 55 degrees. We know that frequency of the pole occurs when
there is a -20dB per decade slope of the magnitude dB.
𝑤𝑝1 =
1
( 𝑅1 𝑅2 𝑔 𝑚7) 𝐶 𝑐
, 𝑅1 =
1
(𝑔𝑑𝑠2+𝑔𝑑𝑠4)
, 𝑅2 =
1
( 𝑔𝑑𝑠6+𝑔𝑑𝑠7)
𝑤 𝑝1 = 7.53982 𝑥 104
𝑟𝑎𝑑
𝑠𝑒𝑐
, 𝑅1 = .33475 𝑀Ω, 𝑅 2 = .225225 𝑀Ω, 𝑔𝑚1 = 6.56 𝑥 10−4 𝑆
CC-Calculated = 1.2583541 pF
17. PROBLEM 10
Figure 9: Calculated CC Bode.
The unity transition frequency for the problem was found to graphically occur at a frequency of 315.228
MHz. I found that w3dB = 1.986919 e9 radians per second and a CC-Calcuated I obtain a phase margin of only
40 degrees.
Figure 10: Miller Capactor & Phase Margin=55 °
18. The actual Capacitance was very close to the anticipated value. WTA is equal to the transconductance, gm1, of which
was divided by CC.
𝑊𝑇𝐴 =
𝑔𝑚1
𝐶𝑐 𝐴𝑐𝑡𝑢𝑎𝑙
CC-Actual=4.06 pF
Figure 11
21. The addition of the load capacitor has greatly affects the dynamics of the system. There is a clear phase
lead addition around 1GHz and the primary pole which previously occurred around 10 MHz has
seemed to disappear. I was unable to get the magnitude plot to reach 0 db, which means the phase
margin doesn't exist. Changing the Vcm DC and AC magnitude only effected the bode plot at low
frequencies. Changing the resistor or Cc never helped me reach 0 dB.
PROBLEM 13
𝜏 =
1
𝛽 𝑇𝐴
𝜏 = 6.07 × 10−9 𝑠𝑒𝑐𝑜𝑛𝑑
22. The circuit response to a step input resulted in a significant amount of overshoot. In order to decrease the
amount of overshoot I responded by tuning Cc to produce less phase lead. The system is not perfect but
resembles a critically damped system.
