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Dsp 2812
- 1. F28x –Digital I/O Digital Signal Controller TMS320F2812 RANJA N SINGH
- 2. t32x32x323 2bbii 32x32 bit Multiplier SSectectoorr eded FFllashash Sectored Flash A(18-0) D(15-0) Data Bus RRAAMMRAM Boot ROM 22 32-32- bbiitt AAuuxixilliiaarrys 32-bit Auxiliary Registers 33 3232 bbiitt 3 32 bit Timers RReaeallttiimme e Realtime JTAG Register Bus CPU RR--MM-W AAttoommii AALLUU R-M-WW Atomic ALU PIE Interrupt Manager 32 32 32 EEvveenntt MMaannaaggeerrAAanagerM Event A EEvveenntt MMaannaaggeerrBBanagerM Event B 1122-bbiittAADDCC12-bit ADC WWaattcchhddooggWatchdog MMccBBSSPPMcBSP CCAANN22..00BBCAN2.0B SSCCII-AASCI-A SSCCII-BBSCI-B SSPPIISPI GGPPIIOGPIO RANJA N SINGH C281x Block Diagram
- 3. TMS320F2812 Memory Map MO SARAM (1K) LO SARAM (4K) L1 SARAM (4K) HO SARAM (8K) MP/MC=0 BROM vector (32) MP/MC=0 ENPIE=0 OTP (2K) reserved Boot ROM (4K) reserved M1 SARAM (1K) PF 0 (2K) reserved ENPIE=1 XINT Zone 0 (8K) XINT Zone 1 (8K) XINT Zone 2 (0.5M) XINT Zone 6 (1M) XINT Zone 7 (16K) MP/MC=1 XINT Vector-RAM (32) MP/MC=1 ENPIE=0 reserved reserved reserved 00 1000 reserved 00 6000 PF 2 (4K) reserved 00 7000 PF 1 (4K) reserved 00 0000 00 0400 00 0800 00 0D00 PIE vector (256) reserved 00 8000 00 9000 00 A000 3D 7800 3D 8000 3F 8000 3F A000 3F F000 3F FFC0 3F C000 08 0000 10 0000 20 0000 00 2000 00 4000 Data | Program Data | Program FLASH (128K) 128-Bit Password CSM: LO, L1 OTP, FLASHRANJA N SINGH
- 4. GPIO A GPIOA0 / PWM1 GPIOA1 / PWM2 GPIOA2 / PWM3 GPIOA3 / PWM4 GPIOA4 / PWM5 GPIOA5 / PWM6 GPIOA6 / T1PWM_T1CMP GPIOA7 / T2PWM_T2CMP GPIOA8 / CAP1_QEP1 GPIOA9 / CAP2_QEP2 CAP3_QEPI1 TDIRA TCLKINA C1TRIP C2TRIP C3TRIP GPIOB0 / PWM7 GPIOB1 / PWM8 GPIOB2 / PWM9 GPIOB3 / PWM10 GPIOB4 / PWM11 GPIOB5 / PWM12 GPIOB6 / T3PWM_T3CMP GPIOB7 / T4PWM_T4CMP GPIOB8 / CAP4_QEP3 GPIOB9 / CAP5_QEP4 CAP6_QEPI2 TDIRB TCLKINB C4TRIP C5TRIP C6TRIP GPIOD0 / T1CTRIP_PDPINTA GPIOD1 / T2CTRIP / EVASOC GPIOD5 / T3CTRIP_PDPINTB GPIOD6 / T4CTRIP / EVBSOC GPIO E GPIOE0 / XINT1_XBIO GPIOE1 / XINT2_ADCSOC GPIOE2 / XNMI_XINT13 GPIOA10 / GPIOA11 / GPIOA12 / GPIOA13 / GPIOA14 / GPIOA15 / GPIO F GPIOF0 / SPISIMOA GPIOF1 / SPISOMIA GPIOF2 / SPICLKA GPIOF3 / SPISTEA GPIOF4 / SCITXDA GPIOF5 / SCIRXDA GPIOF6 / CANTXA GPIOF7 / CANRXA GPIOF8 / MCLKXA GPIOF9 / MCLKRA GPIOF10 / GPIOF11 / GPIOF12 / GPIOF13 / GPIOF14 / MFSXA MFSRA MDXA MDRA XF GPIOB10 / GPIOB11 / GPIOB12 / GPIOB13 / GPIOB14 / GPIOB15 / GPIO G GPIOG4 / SCITXDB GPIOG5 / SCIRXDB Note: GPIO are pin functions at reset GPIO A, B, D, E include Input Qualification feature C28x GPIO Pin Assignment RANJA N SINGH
- 5. • 0 • •1 MUX Control Bit 0 = I/O Function 1 = Primary Function Pin Primary Peripheral Function I/O DAT Bit (R/W) In Out • I/O DIR Bit 0 = Input 1 = Output GPxMUX GPxDIR GPxDAT QUALPRDreserved 7 - 015 - 8 GPxQUAL 00h 01h no qualification (SYNC to SYSCLKOUT) QUALPRD = SYSCLKOUT/2 0 .2h . FFh QUAL .PRD = SYSCL .KOUT/4 . . QUALPRD = SYSCLKOUT/510 Some digital I/O and peripheral I/O input signals include an Input Qualification feature C28x GPIO Functional Block Diagram RANJA N SINGH
- 6. C28x GPIO MUX/DIR Registers Address Register Name 70C0h 70C1h 70C2h GPAMUX GPADIR GPAQUAL GPIO A Mux Control Register GPIO A Direction Control Register GPIO A Input Qualification Control Register 70C4h 70C5h 70C6h GPBMUX GPBDIR GPBQUAL GPIO B Mux Control Register GPIO B Direction Control Register GPIO B Input Qualification Control Register 70CCh 70CDh 70CEh GPDMUX GPDDIR GPDQUAL GPIO D Mux Control Register GPIO D Direction Control Register GPIO D Input Qualification Control Register 70D0h 70D1h 70D2h GPEMUX GPEDIR GPEQUAL GPIO E Mux Control Register GPIO E Direction Control Register GPIO E Input Qualification Control Register 70D4h 70D5h GPFMUX GPFDIR GPIO F Mux Control Register GPIO F Direction Control Register 70D8h 70D9h GPGMUX GPGDIR GPIO G Mux Control Register GPIO G Direction ControlRegister RANJA N SINGH
- 7. Address Register Name 70E0h 70E1h 70E2h 70E3h GPADAT GPASET GPACLEAR GPATOGGLE GPIO A Data Register GPIO A Set Register GPIO A Clear Register GPIO A ToggleRegister 70E4h 70E5h 70E6h 70E7h GPBDAT GPBSET GPBCLEAR GPBTOGGLE GPIO B Data Register GPIO B Set Register GPIO B Clear Register GPIO B ToggleRegister 70ECh 70EDh 70EEh 70EFh GPDDAT GPDSET GPDCLEAR GPDTOGGLE GPIO D Data Register GPIO D Set Register GPIO D Clear Register GPIO D ToggleRegister 70F0h 70F1h 70F2h 70F3h GPEDAT GPESET GPECLEAR GPETOGGLE GPIO E Data Register GPIO E Set Register GPIO E Clear Register GPIO E ToggleRegister 70F4h 70F5h 70F6h 70F7h GPFDAT GPFSET GPFCLEAR GPFTOGGLE GPIO F Data Register GPIO F Set Register GPIO F Clear Register GPIO F ToggleRegister 70F8h 70F9h 70FAh GPGDAT GPGSET GPGCLEAR GPIO G Data Register GPIO G Set Register GPIO G ClearRegister C28x GPIO Data Registers GPGTOGGLE RANJA N SINGH
- 8. C28x Oscillator / PLL Clock Module PLLCR @ 7021h DIV3 DIV2 DIV1 DIV0 Clock Frequency (CLKIN) 0 0 0 0 OSCCLK x 1 / 2 (no PLL) 0 0 0 1 OSCCLK x 1 / 2 0 0 1 0 OSCCLK x 2 / 2 0 0 1 1 OSCCLK x 3 / 2 0 1 0 0 OSCCLK x 4 / 2 0 1 0 1 OSCCLK x 5 / 2 0 1 1 0 OSCCLK x 6 / 2 0 1 1 1 OSCCLK x 7 / 2 1 0 0 0 OSCCLK x 8 / 2 1 0 0 1 OSCCLK x 9 / 2 1 0 1 0 OSCCLK x 10 / 2 PLLCR bits 15:4 reserved crystal X1 /CLKIN X2 XTALOSC Watchdog Module PLL Clock Module 4-bit PLLSelect PLLCLK /2 OSCCLK • CLKIN MUX XF_XPLLDIS 1 0 HISPCP LOSPCP C28x Core SYSCLKOUT • HSPCLK LSPCLK • RANJA N SINGH
- 9. RANJA N SINGH Peripheral Clock Control Register Module Enable Clock Bit 0 = disable 1 = enable 0 reserved reserved reserved reserved ADC ENCLK reserved EVB ENCLK EVA ENCLK 1234567 reserved HECCA ENCLK reserved MA ENCLK SCIB ENCLK SCIA ENCLK reserved SPIA ENCLK HSPCLK PCLKCR @ 701Ch LSPCLK 15 14 13 12 11 10 9 8
- 10. RANJA N SINGH High / Low – Speed Peripheral Clock Pre- scale Registers HISPCP @ 701Ah / LOSPCP @ 701Bh 15 - 3 2 1 0 reserved HSPCLK2 HSPCLK1 HSPCLK0 01215 - 3 reserved LSPCLK2 LSPCLK1 LSPCLK0 H/LSPCLK2 H/LSPCLK1 H/LSPCLK0 Peripheral Clock Frequency 0 0 0 SYSCLKOUT / 1 0 0 1 SYSCLKOUT / 2 (default HISPCP) 0 1 0 SYSCLKOUT / 4 (default LOSPCP) 0 1 1 SYSCLKOUT / 6 1 0 0 SYSCLKOUT / 8 1 0 1 SYSCLKOUT / 10 1 1 0 SYSCLKOUT / 12 1 1 1 SYSCLKOUT / 14
- 11. RANJA N SINGH Watchdog Timer • Resets the C28x if the CPU crashes – – – Watchdog counter runs independent of CPU If counter overflows, reset or interrupt is triggered CPU must write correct data key sequence to reset the counter before overflow • Watchdog must be serviced (or disabled) within ~4,3ms after reset (30 MHz external clock) • This translates into 6.3 million instructions!
- 12. RANJA N SINGH Watchdog Timer Module 6 - Bit Free - Running Counter CLR /2 /4 /16 /8 OSCCLK System Reset 100 011 010 001 000 /64 111 /32 110 101 • • • • 8 - Bit Watchdog Counter CLR One-Cycle Delay Watchdog Reset Key Register 55 +AA Detector • Good Key Bad Key 1 0 1 • • • • 3/ 3/ WDCR . 2 - 0 WDCR . 6 WDPS WDDIS WDCR . 7 WDFLAG WDCNTR . 7 - 0 WDKEY . 7 - 0 WDCR . 5 - 3 WDCHK 2-0 Bad WDCR Key /512 Output Pulse WDRST WDINT SCSR .1 WDENINT • • • SCSR . 0 WDOVERRIDE
- 13. RANJA N SINGH Watchdog Timer Control Register • WDCR @ 7029h 7 6 5 4 3 2 1 0 reserved WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 Logic Check Bits WD Prescale Write as 101 or reset Selection Bits immediately triggered Watchdog Disable Bit (Functions only if WD OVERRIDE bit in SCSR is equal to 1) 15 - 8 WD Flag Bit Gets set when the WD causes a reset • Writing a 1 clears this bit • Writing a 0 has no effect
- 14. RANJA N SINGH Resetting the Watchdog • Allowable write values: 55h - counter enabled for reset on next AAh write AAh - counter set to zero if reset enabled • Writing any other value immediately triggers a CPU reset • Watchdog should not be serviced solely in an ISR – – If main code crashes, but interrupt continues to execute, the watchdog will not catch the crash Could put the 55h WDKEY in the main code, and the AAh WDKEY in an ISR; this catches main code crashes and also ISR crashes WDKEY @ 7025h 7 6 5 4 3 2 1 0 reserved D7 D6 D5 D4 D3 D2 D1 D0 15 - 8
- 15. RANJA N SINGH Sequential Step Value Written to WDKEY Result 1 AAh No action 2 AAh No action 3 55h WD counter enabled for reset on next AAh write 4 55h WD counter enabled for reset on next AAh write 5 55h WD counter enabled for reset on next AAh write 6 AAh WD counter is reset 7 AAh No action 8 55h WD counter enabled for reset on next AAh write 9 AAh WD counter is reset 10 55h WD counter enabled for reset on next AAh write 11 23h CPU reset triggered due to improper write value WDKEY Write Results
- 16. RANJA N SINGH System Control and Status Register SCSR @ 7022h WD Override (protect bit) After RESET - bit gives user ability to disable WD by setting WDDIS bit=1 in WDCR •clear only bit and defaults to 1 after reset 0 = protects WD from being disabled by s/w •bit cannot be set to 1 by s/w (clear-only by writing 1) 1 = (default value) allows WD to be disabled using WDDIS bit in WDCR • once cleared, bit cannot set to 1 by s/w 15 - 3 2 1 0 reserved WDINTS WDENINT WD OVERRIDE WD Interrupt Status (read only) 0 = active 1 = not active WD Enable Interrupt 0 = WD generates a DSPreset 1 = WD generates a WDINT interrupt
- 17. RANJA N SINGH Low Power Mode CPU Logic Clock Peripheral Logic Clock Watchdog Clock PLL / OSC Normal Run on on on on IDLE off on on on STANDBY off off on on HALT off off off off Low Power Modes
- 18. RANJA N SINGH Low Power Mode Control Register 0 7 - 215 - 8 reserved QUALSTDBY LPM1 LPM0 Low Power Mode Entering 1. Set LPM bits 2. Enable desired exit interrupt(s) 3. Execute IDLE instruction 4. The Power down sequence of the hardware depends on LP mode Low Power Mode Selection 00 = Idle 01 = Standby 1x = Halt Qualify before waking from STANDBY mode LPMCR0 @ 701Eh 000000 = 2 OSCCLKs 000001 = 3 OSCCLKs 111111 = 65 OSCCLKS 1 0
- 19. RANJA N SINGH Wake device from STANDBY mode 0 = disable 1 = enable 0 C1TRIP T4CTRIP T3CTRIP T2CTRIP T1CTRIP WDINT XNMI XINT1 CANRXA SCIRXB SCIRXA C6TRIP C5TRIP C4TRIP C3TRIP C2TRIP 1234567 89101112131415 Low Power Mode Control Register 1
- 20. RANJA N SINGH Exit Interrupt Low Power Mode RESET External or Wake up Interrupts Enabled Peripheral Interrupts IDLE yes yes yes STANDBY yes yes no HALT yes no no Note: External or Wake up include XINT1, PDPINT, TxCTRIP, CxTRIP NMI, CAN, SPI, SCI, WD Low Power Mode Exit
- 21. RANJA N SINGH DEDICATED TO MY LOVE P. SINGH03/03/2019