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Collaboration opportunities with
open-source CHERI foundations
Prof. Simon Moore
University of Cambridge
cheri-cpu.org
Collaboration opportunities
• Software above CHERI hardware
• Hypervisors, operating systems, compilers/toolchain/debuggers, software
compartmentalization, managed languages, applications, and evaluation
• Lead: Robert Watson
• CHERI semantics and verification
• Analysis, proof, model-checking, and testing for CHERI security and
correctness, for CHERI assembly and CHERI C; verified compilation and linking
• CHERI hardware verification; CHERI SoC semantics
• Lead: Peter Sewell
• Maturing CHERI-RISC-V ISA and providing a range of implementations
• Currently focused on small microcontrollers (complements ARM’s work)
• Exploring wider use-cases, e.g. CHERI for industrial controllers and “IoT”
• Lead: Simon Moore
cheri-cpu.org
Open-source CHERI artefacts available
• CHERI ISA v7 architecture spec. includes
• CHERI-MIPS (mature), CHERI-RISC-V (experimental), CHERI-x86 (sketch)
• Formal ISA models in Sail (to C emulator, Coq, HOL4, Isabelle, SMT )
• ARMv8-A, RISC-V, CHERI-ARM, CHERI-MIPS and CHERI-RISC-V
• Tools: Clang/LLVM compiler, LLD linker, GDB debugger support
• CHERI-ARM, CHERI-MIPS, CHERI-RISC-V (experimental)
• OS support
• CheriBSD (FreeBSD derived) on CHERI-ARM, CHERI-MIPS, CHERI-RISC-V (soon)
• CheriFreeRTOS on CHERI-RISC-V
• Many C/C++ applications ported (generally with little effort)
cheri-cpu.org

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Digital Security by Design: Collaboration opportunities with open-source CHERI foundations - Prof. Simon Moore, University of Cambridge

  • 1. Collaboration opportunities with open-source CHERI foundations Prof. Simon Moore University of Cambridge cheri-cpu.org
  • 2. Collaboration opportunities • Software above CHERI hardware • Hypervisors, operating systems, compilers/toolchain/debuggers, software compartmentalization, managed languages, applications, and evaluation • Lead: Robert Watson • CHERI semantics and verification • Analysis, proof, model-checking, and testing for CHERI security and correctness, for CHERI assembly and CHERI C; verified compilation and linking • CHERI hardware verification; CHERI SoC semantics • Lead: Peter Sewell • Maturing CHERI-RISC-V ISA and providing a range of implementations • Currently focused on small microcontrollers (complements ARM’s work) • Exploring wider use-cases, e.g. CHERI for industrial controllers and “IoT” • Lead: Simon Moore cheri-cpu.org
  • 3. Open-source CHERI artefacts available • CHERI ISA v7 architecture spec. includes • CHERI-MIPS (mature), CHERI-RISC-V (experimental), CHERI-x86 (sketch) • Formal ISA models in Sail (to C emulator, Coq, HOL4, Isabelle, SMT ) • ARMv8-A, RISC-V, CHERI-ARM, CHERI-MIPS and CHERI-RISC-V • Tools: Clang/LLVM compiler, LLD linker, GDB debugger support • CHERI-ARM, CHERI-MIPS, CHERI-RISC-V (experimental) • OS support • CheriBSD (FreeBSD derived) on CHERI-ARM, CHERI-MIPS, CHERI-RISC-V (soon) • CheriFreeRTOS on CHERI-RISC-V • Many C/C++ applications ported (generally with little effort) cheri-cpu.org