Dispositivos digitales

1. DIGITAL DEVICES
TSU. MECATRÓNICA

2. EVALUATION CRITERIA
• Attendance………….10%
• Participation………..10%
• Homework…………..30%
• Case study……………20%
• Write test…………….30%

3. LEARNING UNITS
• Unit 1. Programmable Logic Devices
• Unit 2. Sequential Circuits
• Unit 3. Analog - Digital (ADC) and Digital - Analog (DAC) Converters

4. UNIT 1. PROGRAMMABLE LOGIC DEVICES
• Topic 1. Programmable Logic Devices
• Topic 2. PLD programming and simulation environment

5. UNIT 1. PROGRAMMABLE LOGIC DEVICES
A logic device is an electronic component which performs a definite function which is
decided at the time of manufacture and will never change.
For example, a NOT gate always inverts the logic level of the input signal and does/can-
do-nothing else.
On the other hand, Programmable Logic Devices (PLDs) are the components which do
not have a specific function associated with them.
These can be configured to perform a certain function by the user, on a need basis and can
further be changed to perform some other function at the later point of time, i.e. these are
re-configurable. However, the amount of flexibility offered depends on their type.

6. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Programmable Logic Devices (PLDs) are the integrated circuits which contain an array
of AND gates & another array of OR gates.
The process of entering the information into these devices is known as programming.
Here, the term programming refers to hardware programming but not software
programming.
The internal logic gates AND/OR connections of PLD´s can be changed/configured by a
programming process.

7. UNIT 1. PROGRAMMABLE LOGIC DEVICES
One of the simplest programming technologies is to use fuses. In the original state of the
device, all the fuses are intact.
Programming the device involves blowing those fuses along the paths that must be
removed in order to obtain the particular configuration of the desired logic function.
The purpose of a PLD device is to permit elaborate digital logic designs to be
implemented by the user in a single device. Can be erased electrically and reprogrammed
with a new design, making them very well suited for academic and prototyping.

8. UNIT 1. PROGRAMMABLE LOGIC DEVICES
A typical programmable logic device may have hundreds to millions of gates
interconnected through hundreds to thousands of internal paths.
In order to show the internal logic diagram in a concise form, it is necessary to employ a
special gate symbology applicable to array logic.

9. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Programmable Arrays
All PLD´s are made up of programmable matrices. A programmable array is a network of
conductors distributed in rows and columns with a fuse at each intersection point.
OR matrix.
It is made up of a series of OR gates connected to a programmable matrix with fuses at
each intersection point of a column and a row. The array is programmed by blowing fuses
to remove selected variables from the output functions. For each of the OR gate inputs,
only one fuse remains intact that connects the desired variable to the gate input. Once the
fuse is blown it cannot be reconnected.

10. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Programmable Arrays
AND matrix.
This type of matrix is ​​made up of AND gates connected to a programmable matrix with
fuses at each intersection point. Just as the OR matrix is ​​programmed by blowing fuses to
remove variables from the output functions.

11. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Classification of Programmable Logic Devices
They are classified according to their architecture, that is, the functional arrangement of
the internal elements that gives the device its specific characteristics.
• Programmable Read Only Memory (PROM)
• Programmable LogicArray (PLA)
• ProgrammableArray Logic (PAL)
• Generic Array Logic (GAL)

12. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Types of Programmable Logic Devices
Programmable Read Only Memory (PROM)
It is made up of a fixed set of AND gates (not programmable) connected as a decoder and
a programmable OR matrix. It is used as addressable memory and not as a logical device.
Programmable ROM is a one-time programmable chip that, once programmed, cannot be
erased or altered. PROM is also referred as One Time Programmable(OTP)

13. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Programmable LogicArray (PLA)
It is a PLD circuit that can be programmed to execute a complex function. They are
typically used to implement combinational logic but some PLAs can be used to
implement sequential logic designs. PLA is a single integrated circuit solution to many
logic problems, which can have many inputs and many outputs..
It is a PLD formed by a programmable AND matrix and a programmable OR matrix. It is
also called FPLA (Field Programmable Logic Array) because it is the user and not the
manufacturer who programs it.

14. UNIT 1. PROGRAMMABLE LOGIC DEVICES
ProgrammableArray Logic (PAL)
The PALs are matrix arrangements of fuses and diodes that, through a certain logic, can
perform any Boolean function.
It has been developed to overcome certain disadvantages of PLA, such as long delays
due to additional fuses resulting from the use of two programmable arrays and increased
circuit complexity.
The basic PAL is made up of a programmable AND matrix and a fixed OR matrix with
the output logic.

15. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Generic Array Logic (GAL)
GALs are designed to “emulate” many common PALs using macrocells. This can reduce the different types of
devices purchased and only maintain a single model type.
Allowing to reduce costs, since in general a large quantity of the same device decreases acquisition and storage
costs. These devices are “REPROGRAMMABLE” and electrically erasable which makes them very useful to
design engineers.
It is the most recent development. Like the PAL, it is formed with a programmable AND matrix and a fixed
OR matrix. The two main differences are:
• It is reprogrammable.
• Has programmable output settings.

16. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Memories
Memories are long- or short-term binary data storage devices. In topic 3 we looked at shift
registers, which are types of storage devices. Essentially a shift register is a small scale memory.
This chapter studies memories for long-term storage and large amounts of information.
As a general rule, memories store data in units generally of 8 bits (bytes). A complete unit of
information is called a word and is made up of one or more bytes.
The basic operations of memory are writing and reading. The write operation places the data at a
specific memory location and the read operation extracts the data from a specific memory
location.

17. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Types of Memories
There are different forms of memory that have different characteristics. The main ones are:
• Random Access Memory (RAM)
• Static Random Access Memory (SRAM)
• Dynamic Random Access Memory (DRAM)
• Read-Only Memory (ROM)
• Flash memory
• Simple Programmable Logic Devices (SPLD)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field-Programmable Gate Array)

18. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Random Access Memory (RAM)
It is the name assigned to the fast write and read memory. The name is due to the fact that
on these devices any byte of information can be accessed with the same speed (this is not
true for storage devices such as magnetic tapes, as it will take longer to reach the data at
the end of the the tape than those at the beginning).
A more appropriate name would be read/write memory, but the word RAM is in universal
use and has become established.

19. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Random Access Memory (RAM)
RAM is implanted using one of the following two techniques:
Static RAM (SRAM)
Uses a bistable circuit. Information written to this device is maintained indefinitely as
long as power is maintained. The cell is selected by setting the row and column lines
high. When the WRITE line is low (write), the input data bit is written to the cell. When
the WRITE line is high (read), the cell is not affected, but the stored data bit (Q) is
passed to the data output line.

20. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Random Access Memory (RAM)
RAM is implanted using one of the following two techniques:
Dynamic RAM (DRAM)
Stores information by charging or discharging an array of capacitors. Dynamic RAM
requires far fewer components per bit of stored information, allowing more storage
elements to be integrated within a single chip. However, it has the disadvantage that the
charges on the capacitor tend to deteriorate over time, which makes it necessary to
refresh the devices periodically by applying an appropriate sequence of control signals.
In this type of cell the transistor acts as a switch.

21. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Read-Only Memory (ROM)
It is read-only memory, that is, the processor can read from it but cannot write to it. These
devices are non-volatile, and therefore are suitable for storing programs or any
information that should not change.
There are many types of ROM:
• PROM Programmable read-only memory
• EPROM Erasable programmable read-only memory
• EEPROM Electrically erasable programmable read-only memory

22. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Flash memory
Flash memories are high-density (high-density refers to large bit storage capacity)
read/write memories that are non-volatile, meaning data can be stored indefinitely without
the need for power.
Because it has high density, it can store a large number of cells in a small chip surface
area. This high density is achieved with cells made up of a single MOS transistor.
One bit of data is stored with the load or absence of load on the gate.

23. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Types of Programmable Logic Devices
• Simple Programmable Logic Devices (SPLD)
• Complex Programmable Logic Device (CPLD)
• Field Programmable Gate Array (FPGA)

24. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Simple Programmable Logic Devices (SPLD)
They are the simplest, smallest and least expensive forms of programmable logic devices.
SPLDs can be used on boards to replace standard logic components (AND, OR and NOT
gates).
SPLDs are a combination of a logic device (AND gate array, followed by another OR
gate array, one or both of these programmable arrays, some include Flip Flops) and
memory. The memory is used to store the pattern that has been given to the chip during
programming. Most methods for storing data on an integrated circuit have been adapted
for use in SPLDs. These include: silicon antifuses, SRAMs, EPROM or EEPROM cells
and flash memory.

25. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Simple Programmable Logic Devices (SPLD)
Silicon antifuses are responsible for forming connections by applying voltage to a modified area
of ​​the chip. They are called antifuses because they work in the opposite way to normal rifles, which
allow the connection until they break due to excess electrical current.
SRAM, or static RAM, is a volatile type of memory, meaning its contents are lost each time it is
disconnected. SRAM-based SPLDs have to be programmed every time the circuit is powered up.
Generally this is done by another part of the circuit.
An EPROM cell is a MOS (metal-oxide-semiconductor) transistor that can be activated by trapping
an electrical charge permanently in its gate, which is done by a PAL programmer. The charge
remaining for a few years can only be removed by exposing the chip to strong ultraviolet light in a
device called an EPROM eraser.
Flash memories are non-volatile, so they retain their contents even when power is removed. They
can be erased and reprogrammed as needed, making them useful for SPLD memories.

26. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Simple Programmable Logic Devices (SPLD)
Structure
The typical structure consists of "sum of products"
• Programmable AND matrix + Fixed OR matrix
• Any function can be implemented with n inputs of up to p product terms.

27. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Complex Programmable Logic Device (CPLD)
It is an electronic device that extends the concept of a PLD to a higher level of integration
since it allows more effective systems to be implemented because they use less space,
improve design reliability and reduce costs.
They were created to be able to design very complex digital systems that SPLDs, due to
their simplicity, were incapable of solving. For this reason, CPLDs were created with the
idea of ​​being a set of blocks of SPLDs interconnected through a connection matrix.

28. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Complex Programmable Logic Device (CPLD)
Architecture of the CPLDs.
Most CPLDs have the same internal architecture, divided into three parts:
• Global connection matrix
• Logic blocks with their macrocells
• Input and output blocks

29. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Field Programmable Gate Array (FPGA)
It is a complex programmable digital integrated circuit composed of configurable logic
blocks (CLB) and input/output ports (IOB), whose interconnection and functionality can
be programmed using a specialized description language.
Their main feature and advantage is that they can be reprogrammed for a specific job or
change their requirements after being manufactured. This also means that in many cases
physical changes can be made without making costly modifications to the board that
supports it.

30. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Field Programmable Gate Array (FPGA)
Basically, an FPGA is a set of multiple circuits (logical and other types) arranged in a
matrix, whose interconnections are programmable by the user for the required
application. In an FPGA its hardware is programmed, unlike
microcontrollers/microprocessors, in which there is only fixed hardware and its software
(firmware) is programmed.
FPGAs, in addition to containing AND and OR logic gates, have RAM memory, clock
controllers, etc., making them very appropriate for the design of embedded systems with
a microprocessor.

31. UNIT 1. PROGRAMMABLE LOGIC DEVICES
Field Programmable Gate Array (FPGA)
Architecture of the FPGA
An FPGA is made up of a large number of elements called Configurable Logic Blocks
(CLB) - also called Logic Cells (LC) - that are interconnected by a series of
programmable connections called Fabric, which serve as buses (paths) for the exchange
of signals between CLBs. The interface that controls communication between the FPGA
and external devices is made up of the input/output (I/O) blocks.