The document covers lectures 11-13 with a focus on microprogrammed control, specifically addressing the microprogram sequencer and its role in determining microinstruction addresses. It introduces various concepts like instruction op-code mapping and pipeline registers for improving execution speed. Additionally, it outlines the structure of subsequent sections related to these topics.

1. Lectures 11-13: Overview

2. Lectures 11-13: Section 7-1:

3. Lectures 11-13:
Microprogrammed Control
Section 7-1:
TERMINOLOGY
Sequencer (Microprogram Sequencer)
A Microprogram Control Unit that determines
the Microinstruction Address to be executed in
the next clock cycle
- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping
Pipeline Register
A register that holds the current micro-
instruction being executed. This is needed
when the microinstruction execution and the
control storage access for the next micro-
instruction are to be overlapped for speed
improvement.
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4. Lectures 11-13: Section 7-1:

7. Lectures 11-13: Section 7-2:

9. Lectures 11-13: Section 7-2:

10. Lectures 11-13: Section 7-2:

12. Lectures 11-13: Section 7-3:

13. Lectures 11-13: Section 7-3:

14. Lectures 11-13: Section 7-3:

15. Lectures 11-13: Section 7-3:

16. Lectures 11-13: Section 7-3:

17. Lectures 11-13: Section 7-3:

18. Lectures 11-13: Section 7-3:

19. Lectures 11-13: Section 7-3:

20. Lectures 11-13: Section 7-4:

21. Lectures 11-13: Section 7-4:

22. Lectures 11-13: Section 7-4:

23. Lectures 11-13: Section 7-4:

24. Lectures 11-13: Section 7-4:

25. Lectures 11-13: Section 7-4:

26. Lectures 11-13: Section 7-4:

27. Lectures 11-13: Section 7-4: