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Computer Aided Design: Global Routing

This document describes the process of global routing in VLSI physical design. Global routing assigns wiring paths between circuit components at a coarse level of granularity by partitioning the chip into routing regions and assigning nets to these regions. It aims to minimize total wirelength and reduce delays on critical nets. Routing regions are represented using graphs to model available routing resources. Common algorithms discussed include rectilinear Steiner tree construction and sequential Steiner tree heuristics to find minimum path routes between pins in the global routing stage.

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 1 Global Routing Presented By: Rajesh Yadav 12ECP01P M.Tech VLSI ITMU
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 2 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and Signoff Fabrication System Specification Architectural Design Chip Packaging and Testing Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis Introduction
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 3 C D A B 43 21 4 3 4 1 1 654 Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} Technology Information (Design Rules) Placement result Introduction: General Routing Problem
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 4 Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} Technology Information (Design Rules) Introduction: General Routing Problem C D A B 43 21 4 3 4 1 1 654 N1
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 5 Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} Technology Information (Design Rules) Introduction: General Routing Problem C D A B 43 21 4 3 4 1 1 654 N2 N3N4 N1
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 6 Timing-Driven Routing Global Routing Detailed Routing Large Single- Net Routing Coarse-grain assignment of routes to routing regions Fine-grain assignment of routes to routing tracks Net topology optimization and resource allocation to critical nets Power (VDD) and Ground (GND) routing Routing Geometric Techniques Non-Manhattan and clock routing Introduction Multi-Stage Routing of Signal Nets
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 7 • Wire segments are tentatively assigned (embedded) within the chip layout • Chip area is represented by a coarse routing grid • Available routing resources are represented by edges with capacities in a grid graph ⇒ Nets are assigned to these routing resources Global Routing Introduction ©2011SpringerVerlag
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 8 N3 N3 N1 N2N1 N3 N1 N2 N3 N3 N1 N2N1 N3 N1 N2 Horizontal Segment Via Vertical Segment Detailed Routing Introduction Global Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 9 5.1.2 Globalverdrahtung Detailed Routing Placement Wire Tracks Global Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 10 • Global routing seeks to − determine whether a given placement is routable, and − determine a coarse routing for all nets within available routing regions • Considers goals such as − minimizing total wirelength, and − reducing signal delays on critical nets Optimization Goals
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 11 Optimization Goals Full-custom design B F A C D E H V H A B F D H V C E 1 2 3 4 5 5 B F A C D E1 2 3 4 (2) Channel ordering B F A C D E (1) Types of channels Layout is dominated by macro cells and routing regions are non-uniform
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 12 Optimization Goals Standard-cell design A A A A A Feedthrough cells If number of metal layers is limited, feedthrough cells must be used to route across multiple cell rows Variable-die, standard cell design: Total height = ΣCell row heights + All channel heights
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 13 Optimization Goals Gate-array design Available tracks Unrouted net Cell sizes and sizes of routing regions between cells are fixed Key Tasks: Determine routability Find a feasible solution
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 14 • Routing regions are represented using efficient data structures • Routing context is captured using a graph, where − nodes represent routing regions and − edges represent adjoining regions • Capacities are associated with both edges and nodes to represent available routing resources Representations of Routing Regions
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Grid graph model ggrid = (V,E), where the nodes v ∈ V represent the routing grid cells (gcells) and the edges represent connections of grid cell pairs (vi,vj) Representations of Routing Regions
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 16 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Channel connectivity graph G = (V,E), where the nodes v ∈ V represent channels, and the edges E represent adjacencies of the channels Representations of Routing Regions
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Switchbox connectivity graph G = (V, E), where the nodes v ∈ V represent switchboxes and an edge exists between two nodes if the corresponding switchboxes are on opposite sides of the same channel Representations of Routing Regions
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 18 The Global Routing Flow 1. Defining the routing regions (Region definition) − Layout area is divided into routing regions − Nets can also be routed over standard cells − Regions, capacities ancd connections are represented by a graph 1. Mapping nets to the routing regions (Region assignment) − Each net of the design is assigned to one or several routing regions to connect all of its pins − Routing capacity, timing and congestion affect mapping 1. Assigning crosspoints along the edges of the routing regions (Midway routing) − Routes are assigned to fixed locations or crosspoints along the edges of the routing regions − Enables scaling of global and detailed routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 19 B (2, 6) A (2, 1) C (6, 4) B (2, 6) A (2, 1) C (6, 4) S (2, 4) Rectilinear Steiner minimum tree (RSMT) Rectilinear minimum spanning tree (RMST) 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 20 Characteristics of an RSMT • An RSMT for a p-pin net has between 0 and p – 2 (inclusive) Steiner points • The degree of any terminal pin is 1, 2, 3, or 4 The degree of a Steiner point is either 3 or 4 • A RSMT is always enclosed in the minimum bounding box (MBB) of the net • The total edge length LRSMT of the RSMT is at least half the perimeter of the minimum bounding box of the net: LRSMT  LMBB / 2 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 21 Transforming an initial RMST into a low-cost RSMT p1 p2 p3 p1 p3 p2 S1 p1 p3 p2 Construct L-shapes between points with (most) overlap of net segments p1 p3 S p2 Final tree (RSMT) 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 22 Hanan grid • Adding Steiner points to an RMST can significantly reduce the wirelength • Maurice Hanan proved that for finding Steiner points, it suffices to consider only points located at the intersections of vertical and horizontal lines that pass through terminal pins • The Hanan grid consists of the lines x = xp, y = yp that pass through the location (xp,yp) of each terminal pin p. 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 23 Hanan points ( ) RSMTIntersection linesTerminal pins 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 24 Definining routing regions Pins assigned to grid cellsPin connections 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 25 Pins assigned to grid cells Assigned routing regions and feedthrough cells A A A A A A A A A A A Rectilinear Steiner minimum tree (RSMT) Sequential Steiner Tree Heuristic 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 26 A Sequential Steiner Tree Heuristic 1. Find the closest (in terms of rectilinear distance) pin pair, construct their minimum bounding box (MBB) 2. Find the closest point pair (pMBB,pC) between any point pMBBon the MBB and pCfromthe set of pins to consider 3. Construct the MBB of pMBB and pC 4. Add the L-shape that pMBB lies on to T (deleting the other L-shape). If pMBB is a pin, then add any L-shape of the MBB to T. 5. Goto step 2 until the set of pins to consider is empty 5.6.1 Rectilinear Routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 27 1 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 28 1 2 1 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 29 1 2 3 1 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic MBB pc
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 30 1 2 3 1 2 3 1 2 4 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic pMBB
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 31 1 2 3 1 2 3 4 5 1 2 3 4 1 2 3 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 32 1 2 3 1 2 3 4 5 1 2 3 4 1 2 3 4 56 1 2 3 4 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 33 1 2 3 4 56 7 1 2 3 1 2 3 4 5 1 2 3 4 1 2 3 4 56 1 2 3 4 5 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 34 1 2 3 4 56 7 1 2 3 1 2 3 4 5 1 2 3 4 56 7 1 2 3 4 1 2 3 4 56 1 2 3 4 5 6 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 35 1 2 3 4 56 7 1 2 3 1 2 3 4 5 1 2 3 4 56 7 1 2 3 4 1 2 3 4 56 1 2 3 4 5 6 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 36
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 37 • Finds a shortest path between two specific nodes in the routing graph • Input − graph G(V,E) with non-negative edge weights W, − source (starting) node s, and − target (ending) node t • Maintains three groups of nodes − Group 1 – contains the nodes that have not yet been visited − Group 2 – contains the nodes that have been visited but for which the shortest-path cost from the starting node has not yet been found − Group 3 – contains the nodes that have been visited and for which the shortest path cost from the starting node has been found • Once t is in Group 3, the algorithm finds the shortest path by backtracing 5.6.2 Finding Shortest Paths with Dijkstra’s Algorithm
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 38 1 4 7 2 5 8 3 6 9 s t 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Find the shortest path from source s to target t where the path cost ∑w1 + ∑w2 is minimal 5.6.2 Finding Shortest Paths with Dijkstra’s Algorithm Example
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 39 1 4 7 2 5 8 3 6 9 s t 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 (1) Current node: 1
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 40 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 parent of node [node name] ∑w1(s,node),∑w2(s,node) Group 2 Group 31 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Current node: 1 Neighboring nodes: 2, 4 Minimum cost in group 2: node 4 s t
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 41 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 Current node: 4 Neighboring nodes: 1, 5, 7 Minimum cost in group 2: node 2 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 42 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 N [3] 9,10 W [5] 10,12 N [3] 9,10 Current node: 2 Neighboring nodes: 1, 3, 5 Minimum cost in group 2: node 3 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 43 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 N [3] 9,10 W [5] 10,12 N [3] 9,10W [6] 18,18 N [5] 10,11Current node: 3 Neighboring nodes: 2, 6 Minimum cost in group 2: node 5 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 44 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 N [3] 9,10 W [5] 10,12 N [3] 9,10W [6] 18,18 N [5] 10,11 N [6] 12,19 W [8] 12,19 W [7] 9,12 Current node: 5 Neighboring nodes: 2, 4, 6, 8 Minimum cost in group 2: node 7 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 45 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 (1) N (2) 8,6 W (4) 1,4 W (4) 1,4 N (5) 10,11 W (7) 9,12 N (2) 8,6 N (3) 9,10 W (5) 10,12 N (3) 9,10W (6) 18,18 N (5) 10,11 N (6) 12,19 W (8) 12,19 W (7) 9,12N (8) 12,14 N (8) 12,14 Current node: 7 Neighboring nodes: 4, 8 Minimum cost in group 2: node 8 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 46 1 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 (1) N (2) 8,6 W (4) 1,4 W (4) 1,4 N (5) 10,11 W (7) 9,12 N (2) 8,6 N (3) 9,10 W (5) 10,12 N (3) 9,10W (6) 18,18 N (5) 10,11 N (6) 12,19 W ((8)) 12,19 W (7) 9,12N ((8)) 12,14 N (8) 12,14 Retrace from t to s s t 4
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 47 1 4 7 2 5 8 3 6 9 1,4 9,12 12,14 Optimal path 1-4-7-8 from s to t with accumulated cost (12,14) s t
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 48 Thank You

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In this document
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Introduction to Global Routing in VLSI Design presented by Rajesh Yadav, M.Tech VLSI. Discusses the context and scope of Chapter 5 of the referenced text.

Overview of the VLSI design flow, including design stages like circuit design, functional design, placement, signal routing, and timing closure.

Introduction to the general routing problem with examples of netlists and technology information. Discusses placement results and wiring configurations.

Describes timing-driven routing strategies and the distinction between global and detailed routing in VLSI physical design.

Optimization goals in global routing including minimizing wire length and signal delay, with design considerations like channel ordering.

Efficient representation of routing regions using graph structures where nodes represent regions and edges represent connections.

Steps in the global routing process, including defining regions, mapping nets to regions, and midway routing assignments.

Introduction to Rectilinear Steiner minimum trees (RSMT), characteristics, and the importance of Hanan grids in reducing wire length.

Details and steps of the Sequential Steiner Tree Heuristic for constructing low-cost rectilinear routing solutions.

Dijkstra’s Algorithm for finding the shortest paths in routing graphs, with a detailed example illustrating the process.

Computer Aided Design: Global Routing

  • 1.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 1 Global Routing Presented By: Rajesh Yadav 12ECP01P M.Tech VLSI ITMU
  • 2.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 2 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and Signoff Fabrication System Specification Architectural Design Chip Packaging and Testing Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis Introduction
  • 3.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 3 C D A B 43 21 4 3 4 1 1 654 Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} Technology Information (Design Rules) Placement result Introduction: General Routing Problem
  • 4.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 4 Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} Technology Information (Design Rules) Introduction: General Routing Problem C D A B 43 21 4 3 4 1 1 654 N1
  • 5.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 5 Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} Technology Information (Design Rules) Introduction: General Routing Problem C D A B 43 21 4 3 4 1 1 654 N2 N3N4 N1
  • 6.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 6 Timing-Driven Routing Global Routing Detailed Routing Large Single- Net Routing Coarse-grain assignment of routes to routing regions Fine-grain assignment of routes to routing tracks Net topology optimization and resource allocation to critical nets Power (VDD) and Ground (GND) routing Routing Geometric Techniques Non-Manhattan and clock routing Introduction Multi-Stage Routing of Signal Nets
  • 7.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 7 • Wire segments are tentatively assigned (embedded) within the chip layout • Chip area is represented by a coarse routing grid • Available routing resources are represented by edges with capacities in a grid graph ⇒ Nets are assigned to these routing resources Global Routing Introduction ©2011SpringerVerlag
  • 8.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 8 N3 N3 N1 N2N1 N3 N1 N2 N3 N3 N1 N2N1 N3 N1 N2 Horizontal Segment Via Vertical Segment Detailed Routing Introduction Global Routing
  • 9.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 9 5.1.2 Globalverdrahtung Detailed Routing Placement Wire Tracks Global Routing
  • 10.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 10 • Global routing seeks to − determine whether a given placement is routable, and − determine a coarse routing for all nets within available routing regions • Considers goals such as − minimizing total wirelength, and − reducing signal delays on critical nets Optimization Goals
  • 11.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 11 Optimization Goals Full-custom design B F A C D E H V H A B F D H V C E 1 2 3 4 5 5 B F A C D E1 2 3 4 (2) Channel ordering B F A C D E (1) Types of channels Layout is dominated by macro cells and routing regions are non-uniform
  • 12.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 12 Optimization Goals Standard-cell design A A A A A Feedthrough cells If number of metal layers is limited, feedthrough cells must be used to route across multiple cell rows Variable-die, standard cell design: Total height = ΣCell row heights + All channel heights
  • 13.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 13 Optimization Goals Gate-array design Available tracks Unrouted net Cell sizes and sizes of routing regions between cells are fixed Key Tasks: Determine routability Find a feasible solution
  • 14.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 14 • Routing regions are represented using efficient data structures • Routing context is captured using a graph, where − nodes represent routing regions and − edges represent adjoining regions • Capacities are associated with both edges and nodes to represent available routing resources Representations of Routing Regions
  • 15.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Grid graph model ggrid = (V,E), where the nodes v ∈ V represent the routing grid cells (gcells) and the edges represent connections of grid cell pairs (vi,vj) Representations of Routing Regions
  • 16.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 16 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Channel connectivity graph G = (V,E), where the nodes v ∈ V represent channels, and the edges E represent adjacencies of the channels Representations of Routing Regions
  • 17.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Switchbox connectivity graph G = (V, E), where the nodes v ∈ V represent switchboxes and an edge exists between two nodes if the corresponding switchboxes are on opposite sides of the same channel Representations of Routing Regions
  • 18.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 18 The Global Routing Flow 1. Defining the routing regions (Region definition) − Layout area is divided into routing regions − Nets can also be routed over standard cells − Regions, capacities ancd connections are represented by a graph 1. Mapping nets to the routing regions (Region assignment) − Each net of the design is assigned to one or several routing regions to connect all of its pins − Routing capacity, timing and congestion affect mapping 1. Assigning crosspoints along the edges of the routing regions (Midway routing) − Routes are assigned to fixed locations or crosspoints along the edges of the routing regions − Enables scaling of global and detailed routing
  • 19.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 19 B (2, 6) A (2, 1) C (6, 4) B (2, 6) A (2, 1) C (6, 4) S (2, 4) Rectilinear Steiner minimum tree (RSMT) Rectilinear minimum spanning tree (RMST) 5.6.1 Rectilinear Routing
  • 20.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 20 Characteristics of an RSMT • An RSMT for a p-pin net has between 0 and p – 2 (inclusive) Steiner points • The degree of any terminal pin is 1, 2, 3, or 4 The degree of a Steiner point is either 3 or 4 • A RSMT is always enclosed in the minimum bounding box (MBB) of the net • The total edge length LRSMT of the RSMT is at least half the perimeter of the minimum bounding box of the net: LRSMT  LMBB / 2 5.6.1 Rectilinear Routing
  • 21.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 21 Transforming an initial RMST into a low-cost RSMT p1 p2 p3 p1 p3 p2 S1 p1 p3 p2 Construct L-shapes between points with (most) overlap of net segments p1 p3 S p2 Final tree (RSMT) 5.6.1 Rectilinear Routing
  • 22.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 22 Hanan grid • Adding Steiner points to an RMST can significantly reduce the wirelength • Maurice Hanan proved that for finding Steiner points, it suffices to consider only points located at the intersections of vertical and horizontal lines that pass through terminal pins • The Hanan grid consists of the lines x = xp, y = yp that pass through the location (xp,yp) of each terminal pin p. 5.6.1 Rectilinear Routing
  • 23.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 23 Hanan points ( ) RSMTIntersection linesTerminal pins 5.6.1 Rectilinear Routing
  • 24.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 24 Definining routing regions Pins assigned to grid cellsPin connections 5.6.1 Rectilinear Routing
  • 25.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 25 Pins assigned to grid cells Assigned routing regions and feedthrough cells A A A A A A A A A A A Rectilinear Steiner minimum tree (RSMT) Sequential Steiner Tree Heuristic 5.6.1 Rectilinear Routing
  • 26.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 26 A Sequential Steiner Tree Heuristic 1. Find the closest (in terms of rectilinear distance) pin pair, construct their minimum bounding box (MBB) 2. Find the closest point pair (pMBB,pC) between any point pMBBon the MBB and pCfromthe set of pins to consider 3. Construct the MBB of pMBB and pC 4. Add the L-shape that pMBB lies on to T (deleting the other L-shape). If pMBB is a pin, then add any L-shape of the MBB to T. 5. Goto step 2 until the set of pins to consider is empty 5.6.1 Rectilinear Routing
  • 27.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 27 1 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 28.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 28 1 2 1 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 29.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 29 1 2 3 1 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic MBB pc
  • 30.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 30 1 2 3 1 2 3 1 2 4 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic pMBB
  • 31.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 31 1 2 3 1 2 3 4 5 1 2 3 4 1 2 3 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 32.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 32 1 2 3 1 2 3 4 5 1 2 3 4 1 2 3 4 56 1 2 3 4 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 33.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 33 1 2 3 4 56 7 1 2 3 1 2 3 4 5 1 2 3 4 1 2 3 4 56 1 2 3 4 5 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 34.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 34 1 2 3 4 56 7 1 2 3 1 2 3 4 5 1 2 3 4 56 7 1 2 3 4 1 2 3 4 56 1 2 3 4 5 6 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 35.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 35 1 2 3 4 56 7 1 2 3 1 2 3 4 5 1 2 3 4 56 7 1 2 3 4 1 2 3 4 56 1 2 3 4 5 6 5.6.1 Rectilinear Routing: Example Sequential Steiner Tree Heuristic
  • 36.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 36
  • 37.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 37 • Finds a shortest path between two specific nodes in the routing graph • Input − graph G(V,E) with non-negative edge weights W, − source (starting) node s, and − target (ending) node t • Maintains three groups of nodes − Group 1 – contains the nodes that have not yet been visited − Group 2 – contains the nodes that have been visited but for which the shortest-path cost from the starting node has not yet been found − Group 3 – contains the nodes that have been visited and for which the shortest path cost from the starting node has been found • Once t is in Group 3, the algorithm finds the shortest path by backtracing 5.6.2 Finding Shortest Paths with Dijkstra’s Algorithm
  • 38.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 38 1 4 7 2 5 8 3 6 9 s t 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Find the shortest path from source s to target t where the path cost ∑w1 + ∑w2 is minimal 5.6.2 Finding Shortest Paths with Dijkstra’s Algorithm Example
  • 39.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 39 1 4 7 2 5 8 3 6 9 s t 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 (1) Current node: 1
  • 40.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 40 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 parent of node [node name] ∑w1(s,node),∑w2(s,node) Group 2 Group 31 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Current node: 1 Neighboring nodes: 2, 4 Minimum cost in group 2: node 4 s t
  • 41.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 41 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 Current node: 4 Neighboring nodes: 1, 5, 7 Minimum cost in group 2: node 2 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
  • 42.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 42 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 N [3] 9,10 W [5] 10,12 N [3] 9,10 Current node: 2 Neighboring nodes: 1, 3, 5 Minimum cost in group 2: node 3 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
  • 43.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 43 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 N [3] 9,10 W [5] 10,12 N [3] 9,10W [6] 18,18 N [5] 10,11Current node: 3 Neighboring nodes: 2, 6 Minimum cost in group 2: node 5 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
  • 44.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 44 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 [1] N [2] 8,6 W [4] 1,4 W [4] 1,4 N [5] 10,11 W [7] 9,12 N [2] 8,6 N [3] 9,10 W [5] 10,12 N [3] 9,10W [6] 18,18 N [5] 10,11 N [6] 12,19 W [8] 12,19 W [7] 9,12 Current node: 5 Neighboring nodes: 2, 4, 6, 8 Minimum cost in group 2: node 7 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
  • 45.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 45 1 4 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 (1) N (2) 8,6 W (4) 1,4 W (4) 1,4 N (5) 10,11 W (7) 9,12 N (2) 8,6 N (3) 9,10 W (5) 10,12 N (3) 9,10W (6) 18,18 N (5) 10,11 N (6) 12,19 W (8) 12,19 W (7) 9,12N (8) 12,14 N (8) 12,14 Current node: 7 Neighboring nodes: 4, 8 Minimum cost in group 2: node 8 s t parent of node [node name] ∑w1(s,node),∑w2(s,node)
  • 46.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 46 1 7 2 5 8 3 6 9 1,4 8,8 2,6 2,8 9,8 3,3 8,6 9,7 3,2 1,4 2,8 4,5 Group 2 Group 3 (1) N (2) 8,6 W (4) 1,4 W (4) 1,4 N (5) 10,11 W (7) 9,12 N (2) 8,6 N (3) 9,10 W (5) 10,12 N (3) 9,10W (6) 18,18 N (5) 10,11 N (6) 12,19 W ((8)) 12,19 W (7) 9,12N ((8)) 12,14 N (8) 12,14 Retrace from t to s s t 4
  • 47.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 47 1 4 7 2 5 8 3 6 9 1,4 9,12 12,14 Optimal path 1-4-7-8 from s to t with accumulated cost (12,14) s t
  • 48.
    VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 5: Global Routing ©KLMH Lienig ©2011SpringerVerlag 48 Thank You