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![20
Non-tree: Spine & Mesh
Applied in Pentium processor
Spines
Clock sinks or local sub-networks
Clock sinks or local sub-networks
Clock sinks or local sub-
networks
Applied in IBM microprocessor
Very effective, huge wire
[Restle et. al, JSSC’01]
[Su et. al, ICCAD’01]
[Kurd et. al. JSSC’01]](https://image.slidesharecdn.com/lecture24clockpower-routing-181217085652/75/Lecture24-clockpower-routing-20-2048.jpg)
![21
Non-tree: Link Perspective
• Non-tree = tree + links
• How to select link pairs is the key problem
• Link = link_capacitors + link_resistor
• Key issue: find the best links that can help the skew variation
reduction the most!
u
w
i
w
u
Rl
C/2 C/2
u w
Rl
C/2
C/2
[Rajaram et al, DAC’04]](https://image.slidesharecdn.com/lecture24clockpower-routing-181217085652/75/Lecture24-clockpower-routing-21-2048.jpg)
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Lecture24 clockpower routing
This document discusses routing of clock and power nets in VLSI physical design automation. It describes how clock and power routing have special considerations compared to other signal nets due to factors like clock skew, IR drop, and being major power consumers. It provides details on clock tree routing techniques like H-trees, MMM algorithm, and GMA algorithm to minimize clock skew. It also discusses power grid routing using mesh structures in multiple metal layers to reduce voltage drop and electromigration issues. Non-tree clock routing and combining clock routing with other optimizations are noted as future trends.
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Introduction to VLSI Physical Design Automation and the focus on clock and power routing.
Distinction between routing issues for clock/power nets vs. signal nets; specialized routers; automatic vs. manual methods.
Need for clock signals in synchronized designs; clock period determined by various time factors affecting design.
Definition of clock skew; its impact on system performance; emphasis on minimizing skew in clock routing.
Critical considerations in clock design including skew, power, noise, and delay, particularly for high frequencies.
Minimization objectives in clock routing: skew, delay, total wire length, and noise.
Global nature of clock nets; importance of routing strategies, buffer insertion, and wire sizing.
Basic structure of clock trees connecting a source to clock sinks, highlighting the layout concept.
Minimizing clock skew with an H-tree structure; challenges in practical application due to non-ideal distributions.
Heuristic strategy using median for terminal arrangement in clock routing to minimize skew.
Bottom-up algorithm approach for minimizing cost through geometric pairing in clock routing.
Detailed method for achieving zero skew in clock designs; mention of further research challenges.
DME strategy emphasizes late merging for minimal wire length; bottom-up and top-down phases outlined.
Advancements in clock skew scheduling and synthesis in response to increasing variability in designs.
Implementation of non-tree clock networks in high-performance processors; focus on links for skew reduction.
Goals of power distribution: current carrying, voltage stability, noise reduction, and layout efficiency.
Focus on power/ground (P/G) routing importance, regularities, priority, and design rules for resource allocation.
Mesh routing for reduced resistance and improved connections; hierarchical designs explained.
Design challenges with multiple metal layers for VDD and GND; implications for standard cell layout.
Modern practices in P/G I/O optimization, capacitor use, and complexities of voltage islands.
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Lecture24 clockpower routing
- 1. 1 VLSI Physical DesignAutomation Prof. David Pan dpan@ece.utexas.edu Office: ACES 5.434 Clock and Power Routing
- 2. 2 Routing of Clockand Power Nets • Different from other signal nets, clock and power are special routing problems – For clock nets, need to consider clock skew as well as delay. – For power nets, need to consider current density (IR drop) • => specialized routers for these nets. • Automatic tools for ASICs • Often manually routed and optimized for microprocessors, with help from automatic tools
- 3. 3 Clock Introduction • Forsynchronized designs, data transfer between functional elements are synchronized by clock signals • Clock signal are generated externally (e.g., by PLL) • Clock period equation dssuskewd ttttodclock peri +++≥ td: Longest path through combinational logic tskew: Clock skew tsu: Setup time of the synchronizing elements tds: Propagation delay within the synchronizing element
- 4. 4 Clock Skew • Clockskew is the maximum difference in the arrival time of a clock signal at two different components. • Clock skew forces designers to use a large time period between clock pulses. This makes the system slower. • So, in addition to other objectives, clock skew should be minimized during clock routing.
- 5. 5 Clock Design Problem •What are the main concerns for clock design? • Skew – No. 1 concern for clock networks – For increased clock frequency, skew may contribute over 10% of the system cycle time • Power – very important, as clock is a major power consumer! – It switches at every clock cycle! • Noise – Clock is often a very strong aggressor – May need shielding • Delay – Not really important – But slew rate is important (sharp transition)
- 6. 6 The Clock RoutingProblem • Given a source and n sinks. • Connect all sinks to the source by an interconnect network (tree or non-tree) so as to minimize: – Clock Skew = maxi,j |ti - tj| – Delay = maxi ti – Total wirelength – Noise and coupling effect
- 7. 7 Clock Design Considerations •Clock signal is global in nature, so clock nets are usually very big – Significant interconnect capacitance and resistance • So what are the techniques? – Routing • Clock tree versus clock mesh (non-tree or grid) • Balance skew and total wire length – Buffer insertion // will be covered in EE382V (Optimization issues in VLSI CAD) • Clock buffers to reduce clock skew, delay, and distortion in waveform. – Wire sizing // will be covered in Opt. Issues in VLSI CAD • To further tune the clock tree/mesh
- 8. 8 Clock trees • Apath from the clock source to clock sinks Clock Source FF FF FF FF FFFF FF FFFF FF
- 9. 9 Clock trees • Apath from the clock source to clock sinks Clock Source FF FF FF FF FFFF FF FFFF FF
- 10. 10 H-Tree Clock Routing 4Points4 Points 16 Points16 Points Tapping PointTapping Point
- 11. 11 H-tree Algorithm • Minimizeskew by making interconnections to subunits equal in length – Regular pattern – The skew is 0 assuming delay is directly proportional to wirelength • Is this always the case??? • Can be used when terminals are evenly distributed – However, this is never the case in practice (due to blockage, and so on) – So strict (pure) H-trees are rarely used – However, still popular for top-level clock network design – Cons: too costly to be used everywhere Can you think of another shape if non-rectilinear wires are allowed?
- 12. 12 Method of Meansand Medians (MMM) • Applicable when the clock terminals are arbitrarily arranged. • Follows a strategy very similar to H-Tree. • Recursively partition the terminals into two sets of equal size (median). Then, connect the center of mass of the whole circuit to the centers of mass of the two sub-circuits (mean). • Clock skew is only minimized heuristically. The resulting tree may not have zero-skew.
- 13. 13 An Example ofMMM centers of masscenters of mass
- 14. 14 Geometric Matching Algorithm (GMA) •MMM is a top-down algorithm, but GMA is a bottom-up algorithm. • Geometric matching of n endpoints: – Construct a set of n/2 line segments connecting n endpoints pairwise. – No two line segments share an endpoint. – The cost is the sum of the edge lengths. • The basic idea is to find a minimum cost geometric matching recursively. • Time complexity is O(n2.5 log n) for n endpoints.
- 15. 15 An Example ofGMA Apply geometricApply geometric matching recursively.matching recursively. H-flippingH-flipping Post-processing Tapping pointTapping point (not necessarily(not necessarily the mid-point)the mid-point) Can give clock tree of zero skew.Can give clock tree of zero skew.
- 16. 16 An Exact ZeroSkew Algorithm • ICCAD 1991 and TCAD 1993, Ren-Song Tsay • A classic paper to manage clock skew • Use Elmore delay model to compute delay • Guarantee zero skew – Can easily to extended for zero skew or bounded skew – Can you think of a method to do it? • Try to minimize wire length, but not done very well – Lots of follow up works to minimize total wire length while maintaining zero skew – DME and its extensions
- 17. 17 Deferred Merge Embedding •As its name implies, DME defers the merging as late as possible, to make sure minimal wire length cost for merging • Independently proposed by several groups – Edahiro, NEC Res Dev, 1991 – Chao et al, DAC’92 – Boese and Kahng, ASIC’92 • DME needs an abstract routing topology as the input • It has a bottom-up phase followed by a top-down process (sounds familiar?)
- 18.
- 19. 19 Some Thoughts/Trend • Clockskew scheduling together with clock tree synthesis – Schedule the timing slack of a circuit to the individual registers for optimal performance and as a second criteria to increase the robustness of the implementation w.r.t. process variation. • Variability is a major nanometer concern • Non-tree clock networks for variation-tolerance – How to analyze it? – The task is to investigate a combined optimization such that clock skew variability is reduced with minimum wirelength penalty
- 20. 20 Non-tree: Spine &Mesh Applied in Pentium processor Spines Clock sinks or local sub-networks Clock sinks or local sub-networks Clock sinks or local sub- networks Applied in IBM microprocessor Very effective, huge wire [Restle et. al, JSSC’01] [Su et. al, ICCAD’01] [Kurd et. al. JSSC’01]
- 21. 21 Non-tree: Link Perspective •Non-tree = tree + links • How to select link pairs is the key problem • Link = link_capacitors + link_resistor • Key issue: find the best links that can help the skew variation reduction the most! u w i w u Rl C/2 C/2 u w Rl C/2 C/2 [Rajaram et al, DAC’04]
- 22.
- 23. 23 Power Distribution • PowerDistribution Network functions – Carry current from pads to transistors on chip – Maintain stable voltage with low noise – Provide average and peak power demands – Provide current return paths for signals – Avoid electromigration & self-heating wearout – Consume little chip area and wire – Easy to lay out
- 24. 24 Power and GroundRouting • Each standard cell or macro has power and ground signals, i.e., Vdd (power) and GND (ground) • They need to be connected as well • You can imagine that they are HUGE NETWORKS! • In general, P/G routings are pretty regular • They have high priority as well – P/G routing resources are usually reserved – When you do global and detailed routing for signal nets, you cannot use up all the routing resources at each metal layers • Normally some design rules will be given (e.g., 40% of top metal layers are reserved for P/G)
- 25. 25 P/G Routing MainObjectives • Routing resource – Need to balance the routing resource for P/G, clock and signals • Voltage drop – Static (IR) and dynamic (L di/dt) voltage drops – More voltage drop means more gate delay – Usually less than 5-10% voltage drop is allowed – So you may need to size P/G wires accordingly • Electrical migration – Too big current may cause EMI problem • Others…
- 26. 26 P/G Mesh (GridDistribution) • Power/Ground mesh will allow multiple paths from P/G sources to destinations – Less series resistance – Hierarchical power and ground meshes from upper metal layers to lower metal layers • All the way to M1 or M2 (stand cells) – Connection of lower layer layout/cells to the grid is through vias
- 27. 27 Using One MetalLayer VDDVDD GNDGND One tree for VDD and another tree for GND.
- 28. 28 Using Two MetalLayers One 2D-grid for VDD and another one for GND: VDDVDD GNDGND M5M5 M4M4
- 29. 29 Gate Array &Standard Cell Design Inter-weaved combs: VDDVDD GNDGND
- 30. 30 Some Thoughts/Trends • P/GI/O pad co-optimization with classic physical design • Decoupling capacitor can reduce P/G related voltage drop – Need to be planned together with floorplanning and placement • Multiple voltage/frequency islands make the P/G problem and clock distributions more challenging
Editor's Notes
- #4 Within most VLSI circuits, data transfer between functional elements is synchronized by the processing clock. Clock frequency can directly determine the performance of a chip. In the case of a microprocessor the clock frequency determines the Instructions Per Second. IPS=f*NIPC. The clock signal is generated external to the chip and provided to the chip through the clock pin. Each functional unit computes and waits for the next clock signal to pass its results to another unit before the next processing cycle Within most VLSI circuits, data transfer between functional elements is synchronized by the processing clock. Clock frequency can directly determine the performance of a chip. In the case of a microprocessor the clock frequency determines the Instructions Per Second. IPS=f*NIPC. The clock signal is generated external to the chip and provided to the chip through the clock pin. Each functional unit computes and waits for the next clock signal to pass its results to another unit before the next processing cycle. Clock should arrive at the same time to all functional units to minimize delay
- #6 Within most VLSI circuits, data transfer between functional elements is synchronized by the processing clock. Clock frequency can directly determine the performance of a chip. In the case of a microprocessor the clock frequency determines the Instructions Per Second. IPS=f*NIPC. The clock signal is generated external to the chip and provided to the chip through the clock pin. Each functional unit computes and waits for the next clock signal to pass its results to another unit before the next processing cycle Within most VLSI circuits, data transfer between functional elements is synchronized by the processing clock. Clock frequency can directly determine the performance of a chip. In the case of a microprocessor the clock frequency determines the Instructions Per Second. IPS=f*NIPC. The clock signal is generated external to the chip and provided to the chip through the clock pin. Each functional unit computes and waits for the next clock signal to pass its results to another unit before the next processing cycle. Clock should arrive at the same time to all functional units to minimize delay
- #9 The goal of a clock tree is to get the clock signal from a clock source to clock sinks. The relative arrival times, shape, and amplitude of the clock signal at the sinks need to meet certain criteria for the circuit to work correctly. Simple wires are susceptible to influences of signals in nearby wires and their own parasitics among other things that may compromise the integrity the signal and cause the signal arriving at the sinks to be unacceptable.
- #10 Buffering, which restores the signal and reduces delay, helps to guarantee the integrity of the clock signal. These are the two steps that are carried out in the clock tree generation steps in the SSHAFT flow.
- #12 The skew can be minimized by making interconnections carrying clocks signal to sub-units equal in length In the case where terminals are arranged symmetrically, as in gate arrays, zero skew achieved by using H-trees
- #18 A manhattan plane is one where the distance between two points is defined by min{d(p,q) p in P and q in Q} Manhattan distance delta(x)+delta(y) Sinks are locations. in the manhattan plane.