This document discusses computer design basics including instruction set architecture, computer architecture, datapaths, and control units. It describes the components of a basic datapath including registers, arithmetic logic units, shifters, and multiplexers. Control signals are organized into a control word to direct datapath operations for executing microinstructions.

1. Chapter 10
Computer Design Basics
Henry Hexmoor 1

2. Henry Hexmoor 2
10-1
 Computer Specification
• Instruction Set Architecture (ISA) - the
specification of a computer's appearance to a
programmer at its lowest level
• Computer Architecture - a high-level
description of the hardware implementing the
computer derived from the ISA
• The architecture usually includes additional
specifications such as speed, cost, and
reliability.

3. Henry Hexmoor 3
Introduction (continued)
 Simple computer architecture decomposed
into:
• Datapath for performing operations
• Control unit for controlling datapath operations
 A datapath is specified by:
• A set of registers
• The microoperations performed on the data
stored in the registers
• A control interface

4. Henry Hexmoor 4
Datapaths
10-2
 Guiding principles for basic datapaths:
• The set of registers
 Collection of individual registers
 A set of registers with common access resources called a
register file
 A combination of the above
• Microoperation implementation
 One or more shared resources for implementing
microoperations
 Buses - shared transfer paths
 Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations
 Shifter - shared resource for implementing shift
microoperations

5. Henry Hexmoor 5
 Four parallel-load
registers (R0-R3)
 Two mux-based
register selectors
 Register destination
decoder
 Mux B for external
constant input
 Buses A and B with external
address and data outputs
 ALU and Shifter with
Mux F for output select
 Mux D for external data input
 Logic for generating status bits
V, C, N, Z
MD select 0 1
MUX D
V
C
N
Z
n
n
n
n
n
n
n
n
n n
n
2 2
n
n
A data B data
Register file
1 0
MUX B Address
Out
Data
Out
Bus A
Bus B
n
n
Function unit
A B n
G select
4
Zero Detect
MF select
n
n
n
F
MUX F
H select
2
n
A B
S2:0 || Cin
Arithmetic/logic
unit (ALU)
G
B
S
Shifter
H
MUX
0
1
2
3
MUX
0
1
2
3
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
Write
D data
D address
2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus D
n
Data In
IL
IR
0 0
0 1
Datapath Example
Figure 10-1

6. Henry Hexmoor 6
 Microoperation: R0 ← R1 + R2
MD select 0 1
MUX D
V
C
N
Z
n
n
n
n
n
n
n
n
n n
n
2 2
n
n
A data B data
Register file
1 0
MUX B Address
Out
Data
Out
Bus A
Bus B
n
n
Function unit
A B n
G select
4
Zero Detect
MF select
n
n
n
F
MUX F
H select
2
n
A B
S2:0 || Cin
Arithmetic/logic
unit (ALU)
G
B
S
Shifter
H
MUX
0
1
2
3
MUX
0
1
2
3
0 1 2 3
Decoder
Load
Load
Load
Load
Load enable
Write
D data
D address
2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus D
n
Data In
IL
IR
0 0
0 1
Datapath Example: Performing a
Microoperation
 Apply 01 to A select to place
contents of R1 onto Bus A
 Apply 10 to B select to place
contents of R2 onto B data and
apply 0 to MB select to place
B data on Bus B
 Apply 0010 to G select to perform
addition G = Bus A + Bus B
 Apply 0 to MF select and 0 to MD
select to place the value of G onto
BUS D
 Apply 00 to Destination select to
enable the Load input to R0
 Apply 1 to Load Enable to force the
Load input to R0 to 1 so that R0 is
loaded on the clock pulse (not shown)
 The overall microoperation requires
1 clock cycle

7. Henry Hexmoor 7
Arithmetic Logic Unit (ALU)
 In this and the next section, we deal with detailed design
of typical ALUs and shifters
 Decompose the ALU into:
• An arithmetic circuit
• A logic circuit
• A selector to pick between the two circuits
 Arithmetic circuit design
• Decompose the arithmetic circuit into:
 An n-bit parallel adder
 A block of logic that selects four choices for the B input to the
adder
 See next slide for diagram

8. Henry Hexmoor 8
Arithmetic Circuit Design
Figure 10-3 and Table 10-1 and table 10-2
(pages 435, 438)
 There are only four functions of B to select as Y in G = A + Y:
• All 0’s
• B
• B
• All 1’s
S1
S0
B
n
B input
logic
n
A
n
X
Cin
Y
n G = X Y + Cin
Cout
n-bit
parallel
adder
Cin = 0 Cin = 1
G = A
G = A + 1
G = A – 1
G = A + B
G = A
G = A + B
G = A + B + 1
G = A + B + 1 Subtraction

9. Henry Hexmoor 9
Logic Circuit
 The text gives a circuit implemented using a multiplexer
plus gates implementing: AND, OR, XOR and NOT
 Here we custom design a circuit for bit Gi by beginning
with a truth table organized as logic operation K-map
and assigning (S1, S0) codes to AND, OR, etc.
 Gi = S0 Ai Bi + S1 Ai Bi
+ S0 Ai Bi + S1 S0 Ai
 Gate input count for
MUX solution > 29
 Gate input count for
above circuit < 20
 Custom design better
S1S0 AND OR XOR NOT
AiBi 0 0 0 1 1 1 1 0
0 0 0 0 0 1
0 1 0 1 1 1
1 1 1 1 0 0
1 0 0 1 1 0

10. Henry Hexmoor 10
Arithmetic Logic Unit (ALU)
 The custom circuit has interchanged the (S1,S0) codes for XOR and NOT
compared to the MUX circuit. To preserve compatibility with the text,
we use the MUX solution.
 Next, use the arithmetic circuit, the logic circuit, and a 2-way
multiplexer to form the ALU. See the next slide for the bit slice diagram.
 The input connections to the arithmetic circuit and logic circuit have
been been assigned to prepare for seamless addition of the shifter,
keeping the selection codes for the combined ALU and the shifter at 4
bits:
• Carry-in Ci and Carry-out Ci+1 go between bits
• Ai and Bi are connected to both units
• A new signal S2 performs the arithmetic/logic selection
• The select signal entering the LSB of the arithmetic circuit, Cin, is
connected to the least significant selection input for the logic circuit,
S0.

11. Henry Hexmoor 11
Arithmetic Logic Unit (ALU)
Figure 10-7
 The next most significant select signals, S0 for the arithmetic circuit and
S1 for the logic circuit, are wired together, completing the two select
signals for the logic circuit.
 The remaining S1 completes the three select signals for the arithmetic
circuit.
Ci Ci + 1
One stage of
arithmetic
circuit
One stage of
logic circuit
2-to-1
MUX
0
1
S
A i
Bi
S0
S1
S2
Ci
G i
A i
Bi
S0
S1
A i
Bi
S0
S1
Cin

12. Henry Hexmoor 12
 Direction: Left, Right
 Number of positions with examples:
• Single bit:
 1 position
 0 and 1 positions
• Multiple bit:
 1 to n – 1 positions
 0 to n – 1 positions
 Filling of vacant positions
• Many options depending on instruction set
• Here, will provide input lines or zero fill
Combinational Shifter Parameters
10-4

13. Henry Hexmoor 13
4-Bit Basic Left/Right Shifter (Figure 10-8)
 Serial Inputs:
• IR for right shift
• IL for left shift
 Serial Outputs
• R for right shift (Same as MSB input)
• L for left shift (Same as LSB input)
 Shift Functions:
(S1, S0) = 00 Pass B unchanged
01 Right shift
10 Left shift
11 Unused
B3
IR IL
S
Serial
output L
Serial
output R
2
B2 B1 B0
H0
H1
H2
H3
S
M
U
X
0 1 2
S
M
U
X
0 1 2
S
M
U
X
0 1 2
S
M
U
X
0 1 2

14. Henry Hexmoor 14
Barrel Shifter
(Figure 10-9)
 A rotate is a shift in which the bits shifted out are inserted into the
positions vacated
 The circuit rotates its contents left from 0 to 3 positions depending on S:
S = 00 position unchanged S = 10 rotate left by 2 positions
S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions
 See Table 10-3 in text for details (page 440)
D3
S0
3 S1 S0
M
U
X
D2 D1 D0
Y0
Y1
Y2
Y3
S1
0
1
2 3 S1 S0
M
U
X
0
1
2 3 S1 S0
M
U
X
0
1
2 3 S1 S0
M
U
X
0
1
2

15. Henry Hexmoor 15
Barrel Shifter (continued)
 Large barrel shifters can be constructed by
using:
1. Layers of multiplexers - Example 64-bit:
 Layer 1 shifts by 0, 16, 32, 48
 Layer 2 shifts by 0, 4, 8, 12
 Layer 3 shifts by 0, 1, 2, 3
 See example in section 12-2 of the text
2. 2 dimensional array circuits designed at the
electronic level

16. Henry Hexmoor 16
Datapath Representation
10-5
 Here we move up one level in the
hierarchy from that datapath
 The registers, and the
multiplexer, decoder, and enable
hardware for accessing them
become a register file
 A register file is an array of fast
registers
 The ALU, shifter, Mux F and
status hardware become a
function unit
 The remaining muxes and buses
which handle data transfers are
at the new level of the hierarchy
Address out
Data out
Constant in
MB select
Bus A
Bus B
FS
V
C
N
Z
MD select
n
D data
Write
D address
A address B address
A data B data
2m
x n
Register file
m
m m
n n
n
n
n
A B
Function
unit
F
4
MUX B
1 0
MUX D
0 1
n n
Data in

17. Henry Hexmoor 17
Datapath Representation (continued)
 In the register file:
• Multiplexer select inputs become
A address and B address
• Decoder input becomes D
address
• Multiplexer outputs become A
data and B data
• Input data to the registers
becomes D data
• Load enable becomes write
 The register file now appears like
a memory based on clocked flip-
flops (the clock is not shown)
 The function unit labeling is quite
straightforward except for FS
Address out
Data out
Constant in
MB select
Bus A
Bus B
FS
V
C
N
Z
MD select
n
D data
Write
D address
A address B address
A data B data
2m
x n
Register file
m
m m
n n
n
n
n
A B
Function
unit
F
4
MUX B
1 0
MUX D
0 1
n
n
Data in

18. Henry Hexmoor 18
Boolean
Equations:
MF = F3 F2
Gi = Fi
Hi = Fi
G Select, H Select, and MF
in T of FS Codes
FS(3:0)
MF
Select
G
Select(3:0)
H
Select(3:0) Microoperation
0000 0 0000 XX
0001 0 0001 XX
0010 0 0010 XX
0011 0 0011 XX
0100 0 0100 XX
0101 0 0101 XX
0110 0 0110 XX
0111 0 0111 XX
1000 0 1 X00 XX
1001 0 1 X01 XX
1010 0 1 X10 XX
1011 0 1 X11 XX
1100 1 XXXX 00
1101 1 XXXX 01
1110 1 XXXX 10
F A

F A 1
+

F A B

F A B 1

F A B

F A B 1

F A 1
-

F A

F A B


F A B


F A B

F A

F B

F sr B

F sl B

+
+ +
+
+ +

Definition of Function Unit Select (FS) Codes
(Table 10-4, page 443))

19. Henry Hexmoor 19
The Control Word
 The datapath has many control inputs
 The signals driving these inputs can be
defined and organized into a control word
 To execute a microinstruction, we apply
control word values for a clock cycle. For
most microoperations, the positive edge of
the clock cycle is needed to perform the
register load
 The datapath control word format and the
field definitions are shown on the next slide

20. Henry Hexmoor 20
The Control Word Fields
 Fields
• DA – D Address (destination)
• AA – AAddress
• BA – B Address (source for MUXB
• MB – Mux B (constant/source
• FS – Function Select
• MD – Mux D
• RW – Register Write
 The connections to datapath are shown in the next slide
Control word
DA AA BA M
B
FS M
D
R
W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

21. Henry Hexmoor 21
Control Word Block Diagram (Figure 10-11)
10
8
14
0
13
11
Bus D
Constant in
n
n
MUX B
1 0
D data
Write
D address
A address B address
A data B data
8 x n
Register file
A B
Function
unit
n
n
n
MUX D
0 1
n
n
Data in
Bus A
Bus B
RW
12
AA
15
DA
n
BA
9
Address out
Data out
V
C
N
Z
7
MD 1
MB 6
4 FS
5
3
2

22. Henry Hexmoor 22
F A
Encoding of Control W
DA, AA, BA MB FS MD RW
Function Code Function Code Function Code Function Code Function Code
R0 000 Register 0 0000 Function 0 No write 0
R1 001 Constant 1 0001 Data In 1 Write 1
R2 010 0010
R3 011 0011
R4 100 0100
R5 101 0101
R6 110 0110
R7 111 0111
1000
1001
1010
1011
1100
1101
1110
F A

F A 1
+

B

F A B 1

F A B

F A B 1

F A 1
-

F A

F A B


F A B


F A B

F A

F B

F sr B

F sl B

+
+ +
+
+ +

Control Word Encoding
Table 10-5

23. Henry Hexmoor 23
Microoperations for the Datapath -
Symbolic Representation
Table 10-6
Micro-
operation DA AA BA MB FS MD RW
R1 R2 R3 Register Function Write
R4 — R6 Register Function Write
R7 R7 — Register Function Write
R1 R0 — Constant Function Write
—— R3 Register — — No Wr ite
R4 —— — — Data in Write
R5 R0 R0 Register Function Write
R1 R2 R3
–
 F A B 1
+ +
=
R4 sl R6
 F sl B
=
R7 R7 1
+
 F A 1
+
=
R1 R0 2
+
 F A B
+
=
Data out R3

R4 Data in

R5 0
 F A B

=

24. Henry Hexmoor 24
m Microoperations from Ta Binary Co o
 Results of simulation of the above on the
next slide
Microoperations for the Datapath - Binary
Representation
Table 10-7
Micro-
operation DA AA BA MB FS MD RW
001 010 011 0 0101 0 1
100 XXX 110 0 1110 0 1
111 111 XXX 0 0001 0 1
001 000 XXX 1 0010 0 1
XXX XXX 011 0 XXXX X 0
100 XXX XXX X XXXX 1 1
101 000 000 0 1010 0 1
R1 R2 R3
–

R4 sl R6

R7 R7 1
+

R1 R0 2
+

Data out R3

R4 Data in

R5 0


25. Henry Hexmoor 25
Datapath Simulation
Figure 10-12
1 4 7 1 0 4 5
2 0 7 0
3 6 0 3 0
X X
2 0 7 0
3 6 0 2 3 0
14 1 2 0 10
2 0 0 1 X
18 18
1 255 2
2
3
4 12 18
5 0
6
7 8
clock
DA
1 4
AA
2
BA
3 6
Constant_in 2
MB
Address_out
Data_out
FS
5
Status_bits
Data_in
MD
RW
reg0 0
reg1
reg2
reg3
reg4
reg5
reg6
reg7
7 8
5

26. Henry Hexmoor 26
Instruction Set Architecture (ISA) for Simple
Computer (SC)
10-7
 A programmable system uses a sequence of instructions to control its
operation
 An typical instruction specifies:
• Operation to be performed
• Operands to use, and
• Where to place the result, or
• Which instruction to execute next
 Instructions are stored in RAM or ROM as a program
 The addresses for instructions in a computer are provided by a program
counter (PC) that can
• Count up
• Load a new address based on an instruction and, optionally, status
information

27. Henry Hexmoor 27
Instruction Set Architecture (ISA) (continued)
 The PC and associated control logic are part of the
Control Unit
 Executing an instruction - activating the necessary
sequence of operations specified by the instruction
 Execution is controlled by the control unit and
performed:
• In the datapath
• In the control unit
• In external hardware such as memory or input/output

28. Henry Hexmoor 28
ISA: Storage Resources
Figure 10-13
 The storage resources are "visible" to the programmer at the lowest
software level (typically, machine or assembly language)
 Storage resources
for the SC =>
 Separate instruction and
data memories imply
"Harvard architecture"
 Done to permit use of
single clock cycle per
instruction implementation
 Due to use of "cache" in
modern computer
architectures, is a fairly
realistic model
Instruction
memory
215x 16
Data
memory
215 x16
Register file
8 x 16
Program counter
(PC)

29. Henry Hexmoor 29
ISA: Instruction Format
 A instruction consists of a bit vector
 The fields of an instruction are subvectors
representing specific functions and having specific
binary codes defined
 The format of an instruction defines the subvectors
and their function
 An ISA usually contains multiple formats
 The SC ISA contains the three formats presented on
the next slide

30. Henry Hexmoor 30
ISA: Instruction Format
Figure 10-14
 The three formats are: Register, Immediate, and Jump and Branch
 All formats contain an Opcode field in bits 9 through 15.
 The Opcode specifies the operation to be performed
 More details on each format are provided on the next three slides
(c) Jump and Branch
(a) Register
Opcode
Destination
register (DR)
Source reg-
ister A (SA)
Source reg-
ister B (SB)
15 9 8 6 5 3 2 0
(b) Immediate
Opcode
Destination
register (DR)
Source reg-
ister A (SA)
15 9 8 6 5 3 2 0
Operand (OP)
Opcode
Source reg-
ister A (SA)
15 9 8 6 5 3 2 0
Address (AD)
(Right)
Address (AD)
(Left)

31. Henry Hexmoor 31
ISA: Instruction Format (continued)
 This format supports instructions represented by:
• R1 ← R2 + R3
• R1 ← sl R2
 There are three 3-bit register fields:
• DR - specifies destination register (R1 in the examples)
• SA - specifies the A source register (R2 in the first
example)
• SB - specifies the B source register (R3 in the first
example and R2 in the second example)
(a) Register
Opcode
Destination
register (DR)
Source reg-
ister A (SA)
Source reg-
ister B (SB)
15 9 8 6 5 3 2 0

32. Henry Hexmoor 32
ISA: Instruction Format (continued)
(b) Immediate
Opcode
Destination
register (DR)
Source reg-
ister A (SA)
15 9 8 6 5 3 2 0
Operand (OP)
 This format supports instructions described by:
• R1 ← R2 + 3
 The B Source Register field is replaced by an Operand field OP
which specifies a constant.
 The Operand:
• 3-bit constant
• Values from 0 to 7
 The constant:
• Zero-fill (on the left of) the Operand to form 16-bit constant
• 16-bit representation for values 0 through 7

33. Henry Hexmoor 33
ISA: Instruction Format (continued)
 This instruction supports changes in the sequence of instruction execution by
adding an extended, 6-bit, signed 2s-complement address offset to the PC value
 The 6-bit Address (AD) field replaces the DR and SB fields
• Example: Suppose that a jump is specified by the Opcode and the PC
contains 45 (0…0101101) and Address contains – 12 (110100). Then the new
PC value will be:
0…0101101 + (1…110100) = 0…0100001 (45 + (– 12) = 33)
 The SA field is retained to permit jumps and branches on N or Z based on the
contents of Source register A
(c) Jump and Branch
Opcode
Source reg-
ister A (SA)
15 9 8 6 5 3 2 0
Address (AD)
(Right)
Address (AD)
(Left)

34. Henry Hexmoor 34
ISA: Instruction Specifications
 The specifications provide:
• The name of the instruction
• The instruction's opcode
• A shorthand name for the opcode called a mnemonic
• A specification for the instruction format
• A register transfer description of the instruction, and
• A listing of the status bits that are meaningful during an
instruction's execution (not used in the architectures defined
in this chapter)

35. Henry Hexmoor 35
ISA: Instruction Specifications (continued)
Instruction Specifications for the SimpleComputer - Part 1
Instruction Opcode Mnemonic Format Description
Status
Bits
Move A 0000000 MOVA RD ,RA R[DR]  R[SA] N, Z
Increment 0000001 INC RD,RA R[DR]  R[SA] + 1 N, Z
Add 0000010 ADD RD,RA,RB R[DR]  R[SA] + R[ SB] N, Z
Subtract 0000101 SUB RD,RA,RB R[DR]  R[SA] - [SB] N, Z
Decrement 0000110 DEC RD,RA R[DR]  R[SA] - 1 N, Z
AND 0001000 AND RD,RA,RB R[DR]  R[SA]  R[SB ] N, Z
OR 0001001 OR RD,RA,RB R[DR]  R[SA]  R[SB] N, Z
Exclusive OR 0001010 XOR RD,RA,RB R[DR]  R[SA]  R[SB] N, Z
NO T 0001011 NO T RD,RA R[DR]  N, Z
R[SA ]
R

36. Henry Hexmoor 36
ISA: Instruction Specifications (continued)
Instruction Specifications for the Simple Computer - Part 2
Instruction Opcode Mnemonic Format Description
St atus
Bits
Move B 0001100 MOVB RD,RB R[DR]  R[SB]
Shift Right 0001101 SHR RD,RB R[DR]  sr R[SB]
Shift Left 0001110 SHL RD,RB R[DR]  sl R[SB]
Load Immediate 1001100 LDI RD, OP R[DR]  zf OP
Add Immediate 1000010 ADI RD,RA,OP R[DR]  R[SA] + zf OP
Load 0010000 LD RD,RA R[DR]  M[SA]
Store 0100000 ST RA,RB M[SA]  R[SB]
Branch on Zero 1100000 BRZ RA,AD if (R[SA] = 0) PC  PC + se AD
Branch on Negative 1100001 BRN RA,AD if (R[SA] < 0) PC  PC + se AD
Jump 1110000 JMP RA PC  R[SA]

37. Henry Hexmoor 37
ISA:Example Instructions and Data in
Memory
Memory Representation of Instructions and Data
Deciimal
Address Memory Contents
Decimal
Opcode Other Fields Operation
25 0000101 001 010 011 5 (Subtract) DR:1, SA:2, SB:3 R1  R2 - R3
35 0100000 000 100 101 32 (Store ) SA:4, SB:5 M[R4]  R5
45 1000010 010 111 011 66 (Add
Immediate)
DR: 2, SA:7, OP:3 R2  R7 +3
55 1100000 101 110 100 96 (Branch
on Zero)
AD: 44, SA:6 If R6 = 0,
PC  PC - 20
70 00000000011000000 Data = 192. After execution of instruction in 35,
Data = 80.

38. Henry Hexmoor 38
Single-Cycle Hardwired Control
10-8
 Based on the ISA defined, design a computer architecture
to support the ISA
 The architecture is to fetch and execute each instruction in
a single clock cycle
 The datapath from Figure 10-11 will be used
 The control unit will be defined as a part of the design
 The block diagram is shown on the next slide

39. Henry Hexmoor 39
Bus A Bus B
Address out
Data out
MW
Data in
MUX B
1 0
MUX D
0 1
DATAPATH
RW
DA
AA
Constant
in
BA
MB
FS
V
C
N
Z
Function
unit
A B
F
MD
Bus D
IR(2:0)
Data in Address
Data
memory
Data out
Register
file
D
A B
Instruction
memory
Address
Instruction
Zero fill
D
A
B
A
A
A
F
S
M
D
R
W
M
W
M
B
Instruction decoder
J
B
Extend
L
P B
C
Branch
Control
V
C
N
Z
J
B
L
P B
C
IR(8:6) || IR(2:0)
PC
CONTROL
Figure 10-15

40. Henry Hexmoor 40
The Control Unit
 The Data Memory has been attached to the Address Out
and Data Out and Data In lines of the Datapath.
 The MW input to the Data Memory is the Memory Write
signal from the Control Unit.
 For convenience, the Instruction Memory, which is not
usually a part of the Control Unit is shown within it.
 The Instruction Memory address input is provided by the
PC and its instruction output feeds the Instruction Decoder.
 Zero-filled IR(2:0) becomes Constant In
 Extended IR(8:6) || IR(2:0) and Bus A are address inputs to
the PC.
 The PC is controlled by Branch Control logic

41. Henry Hexmoor 41
PC Function (continued)
 Branch Control determines the PC transfers based on five of
its inputs defined as follows:
• N,Z – negative and zero status bits
• PL – load enable for the PC
• JB – Jump/Branch select: If JB = 1, Jump, else Branch
• BC – Branch Condition select: If BC = 1, branch for N = 1, else
branch for Z = 1.
 The above is summarize by the following table:
PC Operation PL JB BC
Count Up 0 X X
Jump 1 1 X
Branch on Negative (else Count Up) 1 0 1
Branch on Zero (else Count Up) 1 0 0

42. Henry Hexmoor 42
Instruction Decoder
 The combinational instruction decoder converts the instruction into the
signals necessary to control all parts of the computer during the single
cycle execution
 The input is the 16-bit Instruction
 The outputs are control signals:
• Register file addresses DA, AA, and BA,
• Function Unit Select FS
• Multiplexer Select Controls MB and MD,
• Register file and Data Memory Write Controls RW and MW, and
• PC Controls PL, JB, and BC
 The register file outputs are simply pass-through signals:
DA = DR, AA = SA, and BA = SB
Determination of the remaining signals is more complex.

43. Henry Hexmoor 43
Instruction Decoder (continued)
 The remaining control signals do not depend on the addresses, so must be a
function of IR(13:9)
 Formulation requires examining relationships between the outputs and the
opcodes…
 Observe that for other than branches and jumps, FS = IR(12:9)
 This implies that the other control signals should depend as much as
possible on IR(15:13) (which actually were assigned with decoding in
mind!)
 To make some sense of this, we divide instructions into types as shown in
the table on the next page

44. Henry Hexmoor 44
Instruction Decoder (continued)
TruthTable for Instruction Decoder Logic
Instruction Function Type
Instruction Bits Control Word Bits
15 14 13 9 MB MD RW MW PL JB BC
Function unit operations using
registers
0 0 0 X 0 0 1 0 0 X X
Memory read 0 0 1 X 0 1 1 0 0 X X
Memory write 0 1 0 X 0 X 0 1 0 X X
Function unit operations using
register and constant
1 0 0 X 1 0 1 0 0 X X
Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0
Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 0 1
Unconditional Jump 1 1 1 X X X 0 0 1 1 X

45. Henry Hexmoor 45
Instruction Decoder (continued)
 The types are based on the blocks controlled and the seven signals to be
generated; types can be divided into two groups:
• Datapath and Memory Control (First 4 types)
• PC Control (Last 3 types)
 In Datapath and Memory Control blocks controlled are considered:
• Mux B (1st and 4th types)
• Memory and Mux D (2nd and 3rd types)
• By assigning codes with no or only one 1 for these, implementation of MB,
MD, RW and MW are simplified.
 In Control Unit more of a bit setting approach was used:
• Bit 15 = Bit 14 = 1 were assigned to generate PL
• Bit 13 values were assigned to generate JB.
• Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To
force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL.
 Also, useful bit correlations between values in the two groups were
exploited in assigning the codes.

46. Henry Hexmoor 46
Instruction Decoder (continued)
 The end result by use of the types, careful assignment of
codes, and use of don't cares, yields very simple logic:
 This completes the
design of most of the
essential parts of
the single-cycle
simple computer
19
–17
DA
16
–14
AA
13
–11
BA
10
MB
9–6
FS
5
MD
4
RW
3
MW
2
PL
1
JB
0
BC
Instruction
Opcode DR SA SB
Control word
15 14 13 12 11 10 9 8–6 5–3 2–0