Enzyme, Pharmaceutical Aids, Miscellaneous Last Part of Chapter no 5th.pdf
Cache memory
1.
2. Cache memory is a fast buffer placed between the
processor and main memory to increase the execution
speed of the processor.
The Cache Memory consist of a few kilobytes of
high speed static RAM (SRAM) where as the main
memory consist of a few megabytes of gigabytes of
slower but cheaper Dynamic RAM (DRAM).
4. When the CPU wants to read a byte or word, it output
address on the address bus.
Cache memory check whether the required contents are
available in cache memory.
If it is available, cache controller enables the cache
memory to output the data on the data bus.
If address bytes or data is not present in cache memory,
the cache controller enables the DRAM controller.
The DRAM controller sends the address to main
memory to get the byte. Since DRAM is slower, this
access will require some wait states to be inserted.
The bytes which is read is transferred to CPU as well as
to cache memory. If CPU needs this byte again, it can be
accessed without any wait state.
5. MULTILEVEL CACHE MEMORY
In a multi level Cache system , the small but fast cache is
used first, followed by large and slower caches which are
ultimately followed by even slower main memory.
6. Multilevel caches operate by checking the smallest level
cache first. If address byte is found, it hits, then processor
proceeds with high speed, otherwise next higher cache is
checked, and so on.
Multi level inclusive cache system
The data in L1 cache will also be found in L2 cache.
When external devices in the multiprocessor system wish to
remove a cache line from the processor, the processor
needs to check only the L2 cache.
Multi level exclusive cache system
The exclusive caches, data is present either in L1 or L2
caches. The advantage of exclusive multilevel cache
system is that it can store more data.
