This document describes a 1kW switched mode bench power supply. It uses a switched mode power supply design with a full bridge driver circuit operating at 100kHz to reduce the size of the transformer. A Sepic converter allows the output voltage and current to be varied using duty cycle control. An FPGA controls the system and provides a user interface. It can supply up to 120A across two channels or 60A on one channel. The power supply was designed for high power capability while maintaining efficiency and accuracy.

1. 1kW Switched Mode Bench Power Supply
Texas Tech Undergraduate Labs
Texas Tech University
Summer 2015
Brent Clancy

2. i
Abstract
Providingalarge amountof powerin a limitedsizeisanissue whichcanbe solvedwithaSwitchedMode Power
Supply. Thisisdone byincreasingthe switchingfrequencyof the maintransformerto100kHz. With thisinput,Voltage
and Currentcan be interchangedwithaSepicconverter onthe outputto provide avariable output. Thus,acircuitcan
provide alargeramount of power,while alsobeingmore efficient.

3. ii
Contents
Abstract.....................................................................................................................................................................1
Introduction...............................................................................................................................................................1
Hardware...................................................................................................................................................................2
Power Supply..........................................................................................................................................................2
120V Input Filter.................................................................................................................................................3
PFC Converter.....................................................................................................................................................3
Full Bridge Driver.................................................................................................................................................4
50V Transformer Filter.........................................................................................................................................5
DC/DC Sepic Converter........................................................................................................................................5
High Side Gate Drivers.........................................................................................................................................6
Assembly................................................................................................................................................................7
Aluminum Case...................................................................................................................................................7
Isolation.................................................................................................................................................................7
Optocouplers......................................................................................................................................................8
Gate Drivers........................................................................................................................................................9
FPGA Power......................................................................................................................................................10
24-bit ADC........................................................................................................................................................11
FPGA ................................................................................................................................................................11
FTDI 230XS........................................................................................................................................................12
Software..................................................................................................................................................................13
FPGA Verilog........................................................................................................................................................13
PFC Driver.........................................................................................................................................................13
Full Bridge ZVS Driver........................................................................................................................................14
DC/DC Driver.....................................................................................................................................................15
Python GUI...........................................................................................................................................................16
Conclusion ...............................................................................................................................................................18
References...............................................................................................................................................................19
Appendix I - Budget....................................................................................................................................................1
Appendix II - Gantt Chart.............................................................................................................................................2

4. iii
Figure 1: Both PCBs.........................................................................................................Error! Bookmark not defined.
Figure 3: Mains Input Filter.........................................................................................................................................3
Figure 4: PFC Boost Converter.....................................................................................................................................3
Figure 2: Input Filter on PCB........................................................................................................................................3
Figure 5: Full Bridge Driver and transformer.................................................................................................................4
Figure 6: 50V Output Filter..........................................................................................................................................5
Figure 7: Sepic Converter............................................................................................................................................5
Figure 8: 8.25" x 5.25" Aluminum Case.........................................................................................................................7
Figure 9: Heatsinks .....................................................................................................................................................7
Figure 10: AC Fan........................................................................................................................................................7
Figure 12: PCB Pads for optocouplers...........................................................................................................................8
Figure 11: A Few optocouplers in schematic.................................................................................................................8
Figure 14: PCB Layout of Gate Drivers..........................................................................................................................9
Figure 13: Schematic for Gate Drivers..........................................................................................................................9
Figure 15: ADC088S022 ADC......................................................................................................................................11
Figure 16: ADC088S022 pads on PCB..........................................................................................................................11
Figure 17: SLX9 FPGA ................................................................................................................................................11
Figure 18: PCB Footprints of the FT230XS...................................................................................................................12
Figure 19: FT230XS Schematic...................................................................................................................................12
Figure 20: Boost ConverterVerilog ............................................................................................................................13
Figure 21: ZVS Driver Simulation................................................................................................................................14
Figure 22: ZVS Driver Verilog.....................................................................................................................................15
Figure 23: Python GUI...............................................................................................................................................16
Figure 24: Python Program for GUI ............................................................................................................................17

5. 1
Introduction
This report describes a power supply which can provide a variable killowatt with two channels to
another product by increasing the primary transformer switching frequency to 100kHz. As frequency
increases, the size of the transformer core decreases to a certain point where it is most efficient around 80-
200kHz. With higher frequencies, less current cannot be pushed through the transformer, thus 100kHz is the
magical region for transfer. High side gate drivers are used to provide a signal to the high side FETs. This power
supply also has a dual channel output which can output up to 120 A in parallel, or 60 A for a single channel.
This is done using a Sepic converter whose voltage and current can be controlled using the duty cycle input.
The control for the power supply is provided by a FPGA with a front panel interface. The FPGA is also linked
through USB to a computer, which can provide a higher range of control along with debugging information.
The goal of this power supply is to provide at least 1kW of power with a voltage from 0 to 200VDC and a
current from 0 to 120A. However, with the computer interface, it may also be used to provide an AC signal
that can be any specific shape up to 10kHz.

6. 2
Hardware
Power Supply
In Figure 1, the populatedSMPSboardisshow. Every large exposed trace requires either a large
amount of solder coating or an embedded set of 22 AWG parallel wires in solder. The left side of the
board is the input filter, Boost Converter and SMPS. The middle of the board is the output filter for the
transformer and the DC to DC Sepic (Single Ended primary ended) converters. The right side of the
board after the large white dashed silkscreen is cut off and will be used to isolate the voltages and
control the entire power supply.
Figure 1: SMPS Board

7. 3
120V Input Filter
Figure 3: Mains Input Filter
The filterin Figure 3 removesoutside interference intothe powersupplyandkeepsthe 80-100 kHz power
signalsfromgettingoutof the powersupply. Aside fromfiltering,the varistorandfuse onthe inputhelplimitthe
voltage andcurrenton the inputof the powersupplytomaximize the protectionof the internal circuitfromlightning
strikesandshortcircuits. The Bridge Rectifierconvertsthe 120-240 VACto 170-336 VDC. All partsare ratedfor 20A to
ensure thata short circuitdoesnot burnup the filter. Thispartof the circuitis crucial,because withoutacleaninput,a
cleanoutputof the powersupplycannotbe guaranteed.
BoostConverter
Figure 4: Boost Converter
In Figure 4, the BoostConverterisusedtoforce the outputto alwaysbe 120 VDC. Anaddedbonusto doingthis
isthat the currentisevened outovertime,inwhichitfollowsthe voltagecurve. All partsof thisconverterare doubly
ratedto allowfor240V and 20A of current forthe Full Bridge Driver.The boostconverterisrequiredbecause the output
of the Full Bridge driverwillchange widelybasedonthe inputfromthisboostconverter.
Figure 2: Input Filter on PCB

8. 4
Full BridgeDriver
Figure 5: Full Bridge Driver and transformer
The Full Bridge Driver is the core of the entire power supply using the ZVS Topology. The goal of
the Full Bridge driver is to force an AC signal at a frequency of 86 - 100kHz. The transformer for a 60 Hz 120
VAC system is much bigger, which is why 100kHz allows for smaller transformers with higher efficiency. L4 in
this schematic is used along with CX1 to provide a smooth spike through the main transformer. The ZVS
topology is a topology that solely depends on the phase of Q1 and Q4 to the phase of Q2 and Q3. At 0° phase,
the output power is 0%, while at 180° phase, the output power is 100% with very large 80-100kHz current
spikes. These large voltage spikes are used later in the High Side Gate Driver board.

9. 5
50V TransformerFilter
Figure 6: 50V Output Filter
The 50 V TransformerFilterin Figure 6 essentiallyconvertsthe 80-100kHz AC inputtoDC at 50V. Thisfilterisa
two-stage LCfilter,whichisratedfor40 A to allow for2kW of poweronthe output. A currentsense resistorisusedon
the outputfor ADC Feedback withvoltage andcurrent tothe FPGA.
DC/DC SepicConverter
Figure 7: Sepic Converter
The Sepicconverterisa Single-EndedPrimary-Inductorconverter. Itworksby the dutycycle control onthe first
mosfet. If the dutycycle is25%, L3 will be chargedless,while L1will be chargedmore andthus,more currentissentto
the output. Whenthe duty cycle is85%, L3 will be chargedmore oftenand is more ecstaticwithvoltage throughput,
thushighvoltage issentto the output. Thisconverterallowsforanadjustable voltage andcurrentusingonlydigital
input.The converteralsohasan outputFET whichallowsforconstantvoltage control,whichcansmoothoutthe output
and possibly preventlarge voltagespikes onthe output.

10. 6
HighSideGateDrivers
Figure 8: HighSide Drivers
The High Side gate driversin Figure 8 are usedto drive the highside FETson the switchedmode powersupply.
The High Side FETsare ungrounded.Thismeansthatusingthe DC groundon the SMPS isnot an optionbecause the FETs
will notdrive withoutaGate to source voltage. The lefttwoICsare Digital Isolators(SI8710CC-B-IP),whichuse
capacitorsinsteadthe LEDs usedinan optocoupler. Thisallowsforahighervoltage change,lesspowerusage anda
more accurate digital output.The middle ICsare Gate Drivers,which will bumpupthe isolatedpowerforthe FETdriving.
Finally,the gate driversanddigital isolatorsneedpower.Thisisprovidedbyusingacharge pump.This isprovidedbythe
capacitor inthe figure.Asthe full bridge attemptstodrive,large voltage spikesare shotintothe capacitorand the
ground.The capacitor will slowlycharge up,thusprovidingavoltage forthe highside FETs.

11. 7
Assembly
AluminumCase
Figure 9: 8.25" x 5.25" Aluminum Case
The aluminumcase shownin Figure 9 is8.25" by5.25", whichis2mm largerthanthe greenboardonall sides.
The aluminumsidesare 2.81mm thick,whichisenoughfora 200W powersupply,butsince thispowersupplymust
dissipate atleast500 W and at most 1kW of heat.Thisisassumedbecause the powersupplyisdoublyratedto2kWto
account forunpredictable power losseswhichare accountedforin Figure 11 andFigure 10 witha fan and heatsinks.
Isolation
Figure 11: AC Fan Figure 10: Heatsinks

12. 8
Optocouplers
Figure 13: PCB optocouplers
In Figure 12 and
Figure 12: A Few optocouplers in schematic

13. 9
Figure 13, the optocouplers for isolation are shown which protect the digital system from getting fried by high
voltage. These optocouplers are all biased to enable analog input from the 200V, 50V and differential inputs
for current. The input optocouplers (TLP293-4) have a max frequency input of 10kHz, while the output
optocouplers (TLP2361) have an end frequency of 2 MHz. The optocouplers are separated out by the DC/DC
ground and the 120VDC ground. Power is provided in ......... in which a zener diode is used to force 24 VDC
from the 50V rail and the 120/240VDC rail.

14. 10
Gate Drivers
Figure 15: PCB Layout of Gate Drivers
The Gate Drivers (TD62083APGON) are composed of a 8
Darlington pairs in a single DIP package. The goal for the gate
drivers is to provide a 24 V digital signal to the boost converter, full bridge driver and DC/DC converter Drivers.
3W 200 Ohm resistors are used to pull up, while the darlington pairs pull down, in which the output is
inverted. Each channel in this darlington pair can provide 500mA of current, in which only 100mA is predicted
to be used. The other goal for the Gate Drivers is to buffer the input signal by using the minimal amount of
current on the input with a much larger output.
Figure 14: Schematic for Gate Drivers

15. 11
FPGAPower
The FPGA is a highly sensitive device because the input voltages required must be accurate for the 3.3V
and 1.2V rails with high current. The bonus to having an accurate output to these rails is that the ADC can vary
greatly if the input 3.3V rail is being suppressed by the FPGA's massive current draw. So, to provide these rails
with their required voltage and current requirements, buck converters are used with large output capacitors
and inductors. A Buck converter takes higher voltage with less current and changes it to lower voltage with a
higher current. In the last attempt to power an FPGA, LDOs were used without the consideration of the large
current requirements of the FPGA and the LDOs quickly failed past their current ratings, which made the FPGA
a power sink.

16. 12
24-bitADC
The 24-bit ADC088S022 ADC isa MUX drivenADC inwhichthe channelsare selectedthroughdigital
control providedbythe FPGA. The ADC088S022 ADC wasspecifically chosenforthissystembecause of itscapabilityto
handle 8 channelsof ADCwhile alsobeinga relatively cheap24-bitADC.
FPGA
The Spartan-6 isthe nextgenerationof SpartanFPGAsfromthe Spartan-3.In Figure 18: SLX9 FPGA the
FPGA is shownalongwiththe flashmemoryforprogrammingthe FPGA. The FPGA'smaingoal inthissystemisto
provide digital control of the powersupply.
Figure 16: ADC088S022 ADC
Figure 17: ADC088S022 pads on PCB
Figure 18: SLX9 FPGA

17. 13
FTDI230XS
The FT230XS is a 3MBaud USB to UART driver in
Figure 20. It will be used to control the SMBPS and obtain logging information from the power supply. The USB
input can also externally power the FPGA for debugging.
Figure 19: PCB Footprints of the FT230XS
Figure 20: FT230XS Schematic

18. 14
Software
FPGA Verilog
PFC Driver
The PFC Driver in Figure 21 is just a dual voltage monitor, which detects when the voltage dips
below 120V and forces the voltage to stay a constant 120V. This is done by comparing the input and output
voltages of the boost converter, then setting the duty cycle based on this input.
Figure 21: Boost Converter Verilog

19. 15
Full BridgeZVS Driver
The ZVS Driverisusedto drive the full bridge. Itprovidesfourclocksignalsthatall have a 40% duty
cycle. The verilogcode in Figure 23 worksin the firsttwocyclesof the driver,asshownin Figure 22.
Figure 22: ZVS Driver Simulation

20. 16
Figure 23: ZVS Driver Verilog
DC/DC Driver
The DC to DC Converter Driver drives the two output channels of the power supply. The main goal of
the verilog code is to provide a stable high-power output from the power supply that can select a very specific
current and voltage on the output. The secondary goal of the driver is to provide a high power AC signal, which
can be of any shape up to 10kHz. This is done by obtaining the ADC value from the voltage and current of each
power channel in the supply and setting the duty cycle of the Sepic converters along with setting the constant
voltage on the outputs slightly below the voltage of the Sepic converter outputs. This driver must be incredibly
accurate and reliable as it is the last stage before a user's device is using the output.

21. 17
Python GUI
The Python GUI in Figure 24 is used to set the voltage and current instantly and more accurately on the
switched mode power supply. The debugging section of the python GUI is used to log all of the voltages and
currents obtained from the power supply along with showing the noise of different parts of the power supply.
The Python code in Figure 25 shows how the GUI was created through glade and also shows that there is some
drawing that will be done for each power rail. The goal for this program is to provide accurate information to
the user, while also doing it in a timely manner.
Figure 24: Python GUI

22. 18
Figure 25: Python Program for GUI

23. 19
Conclusion
In Conclusion, this Switched Mode Bench Power Supply must provide at least 1kW of power to a
device, while also having the ability to interchange voltage and current. This is done with parts that are rated
with high current saturation and even higher voltage ratings on capacitors, diodes and FETs. Multiple filters
are used in this power supply to provide more accurate results and to convert AC to DC. An FPGA was chosen
for this project because of the wide range of responsibilities and the high accuracy and reliability required by
any customer. The advantages of using a digital systemin this power supply instead of an analog controller is
that it will not need to be calibrated over time. To provide a higher power rating, better parts must be used in
the construction. As of now, 2kW is possible with the parts used. This was a difficult project, and as such,
completion was not possible in two months.

24. 20
References
[1] PowerEsim,afree (SMPS) switchmode powersupplydesignsoftware andTransformerDesign,MagneticDesign,
Simulation,CalculationSoftware Tool.(n.d.).RetrievedJuly10,2015.

25. A
Appendix I - Budget

26. B
Appendix II - Gantt Chart