3. List of Tables
3.1 PI Modeling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Summary of Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 System specifications used during Experimentation . . . . . . . . . . . . . . 17
4.2 Components with their specification used during Experimentation . . . . . . 25
iii
4. Project Report
on
Design of a Real-Time Stand-Alone System for load
resonant inverters using TMS320F28335
submitted in partial fulfillment of the requirement
for the award of the Degree of
Bachelor of Engineering
in
Electronics & Telecommunication Engineering
by
Jayganesh Rajaraman
Vrajesh Prajapati
Meghna Bhagat
under the guidance of
Dr. Y. S. Rao
Department of Electronics & Telecommunication Engineering
Bharatiya Vidya Bhavan’s
Sardar Patel Institute of Technology
Munshi Nagar, Andheri-West, Mumbai-400058
University of Mumbai
April 2016
5. Certificate
This is to certify that the Project entitled “Design of a Real-Time Stand-Alone System
for load resonant inverters using TMS320F28335” has been completed successfully by Mr.
Jayganesh Rajaraman, Mr. Vrajesh Prajapati and Ms. Meghna Bhagat under the guidance
of Dr. Y. S. Rao for the award of Degree of Bachelor of Engineering in Electronics &
Telecommunication Engineering from University of Mumbai.
Certified by
Dr. Y. S. Rao Dr. Y. S. Rao
Project Guide Head of Department
Dr. Prachi Gharpure
Principal
Department of Electronics & Telecommunication Engineering
Bharatiya Vidya Bhavan’s
Sardar Patel Institute of Technology
Munshi Nagar, Andheri(W), Mumbai-400058
University of Mumbai
April 2016
6. Project approval Certificate
This is to certify that the Project entitled “Design of a Real-Time Stand-Alone System for
load resonant inverters using TMS320F28335” by Mr. Jayganesh Rajaraman, Mr. Vrajesh
Prajapati and Ms. Meghna Bhagat is approved for the award of Degree of Bachelor of En-
gineering in Electronics & Telecommunication Engineering from University of Mumbai.
External Examiner Internal Examiner
(signature) (signature)
Name: Name:
Date: Date:
Seal of the Institute
7. Acknowledgement
We would like to express our special thanks of gratitude to our mentor Dr. Y. S. Rao,
who gave us the opportunity to take up this ambitious industrial project. His guidance
and constant supervision empowered us to face and overcome numerous odds encountered
during execution of this project. We feel fortunate to be mentored by a virtuoso who not only
provided us with constantly challenging problem statements, but also mapped us to necessary
resources to solve these problems. This project gave us an insight of the mechanism and
etiquettes of performing research work and also made use realize the degree of discipline and
commitment required to meet the industrial expectations.
We are highly indebted to Dr. R. R. Sawant for not only providing us complete access to
his original research work but also teaching us all the associated concepts. Dr. R. R. Sawant’s
immense knowledge paved a pivotal role for implementation at Riddhi Heatron Pvt. Ltd.,
designing SMPS and identification and selection of components. His able guidance and
humble nature constantly kept us scintillated and motivated.
We thank professor G. T. Haldankar for assisting us implement our system in Lab and
also providing required safety instructions. We are also thankful to Mr. Prashant Tiwari
with whom we teamed up to develop the customized DSP board.
We express our earnest gratitude to Mr. Parag Gandhi, Riddhi Heatron Pvt.Ltd. for
sponsoring our project and providing technocratic support.
Finally, we are grateful to all our faculty, friends and family members who stood by our
side and provided with moral support during our journey.
3
8. Abstract
As the need for more complex control and friendly user interface is increasing, digital con-
trol implementation is crucial in modern energy conversion systems and power electronic
converters. Load resonant inverters can be controlled by a quasi square wave of variable
pulse width generated by digital signal processor (DSP). It is used to store the required
commands for generating the necessary waveforms to control the frequency of the inverter
through proper design of switching pulses.A digital controller has been implemented which
possess advantages of phase shift control while providing rapid frequency tracking for load
resonant applications. Two applications 1) Induction Heating 2) Switching Mode Power
Supply (SMPS) are discussed in the report.The digital control algorithm has been optimized
in Embedded C Language and implemented on a floating point Digital Signal Processor
TMS320F28335. The DSP alogorithm is experimentally evaluated on load resonant inverter
used for an induction heating system prorotype.
9. Chapter 1
Introduction
The concept of electromagnetic induction has been practiced for non-contact metal heating
processes due to advantages like energy efficiency and environmental cleanliness for domestic
as well as industrial applications. Solid state devices and LRIs are being used for these
systems due to fast and controllable semiconductor devices such as power MOSFETs, IGBTs,
SITs, etc[1]. These systems have been used for a large range of applications like induction
heating, dielectric heating, sonar transmitters, ultrasonic generators, alloy making, brazing,
etc. [2]. The induction heating application of the load resonant inverter has been discussed
in the report.
As high speed Digital Signal Processors have become very common nowadays[3] it is pos-
sible to implement entire controller as a digital control algorithm. To obtain phase tracking,
conventional systems require use of PLLs and does not possess the advantages of digital cir-
cuits. Various attempts have been made to implement PLL using digital controller[4][5][6].
However inherent delay is introduced due to use of PLL due to low pass filter. The fre-
quency tracking circuit can also be implemented by a phase shifter and attenuation network
as discussed in [7].
Another application is SMPS which is an electronic power supply that incorporates a
switching regulator to convert electrical power efficiently. Like other power supplies, an
SMPS transfers power from a source, like mains power, to a load, such as a personal com-
puter, while converting voltage and current characteristics. Unlike a linear power supply,
the pass transistor of a switching-mode supply continually switches between low-dissipation,
full-on and full-off states, and spends very little time in the high dissipation transitions,
which minimizes wasted energy. Ideally, a switched-mode power supply dissipates no power.
Voltage regulation is achieved by varying the ratio of on-to-off time. In contrast, a linear
power supply regulates the output voltage by continually dissipating power in the pass tran-
sistor. This higher power conversion efficiency is an important advantage of a switched-mode
power supply. Switched-mode power supplies may also be substantially smaller and lighter
than a linear supply due to the smaller transformer size and weight.
Switching regulators are used as replacements for linear regulators when higher efficiency,
smaller size or lighter weight are required. They are, however, more complicated; their
switching currents can cause electrical noise problems if not carefully suppressed, and simple
designs may have a poor power factor. This paper discusses design of SMPS load which is a
DC to DC converter.
1
10. We have also discussed the implementation of a fully digitized controller for induction
heaters using digital signal processor TMS320F28335 which is a high speed, high performance
floating point processor[8]. It combines the advantages of two well tested and efficient tech-
niques of closed loop control of load resonant inverters.
1.1 Motivation
Basic problems in control system industries are inflexibility in control-automation, poor
reliability due to component degradation and noise prone circuits resulting in occasional
control-failure. Hence, this motivated implementation of an integrated digital hardware
like Digital Signal Processor (DSP) replacing the complex analog hardware and increases
reliability against aging and noise. The traditional Phase controlled load resonant inverters
use Phase Lock Loop (PLL) for frequency tracking. However it has disadvantage of control
system failure due to delay in frequency control. Thus, we have proposed a digitalized
system with increased reliability and better energy efficiency due to simultaneous frequency
tracking and power regulation. The controller ensures fast frequency control along-with the
desired phase shift control simultaneously. The problem of non-linear phase-shift variation
is solved by slope compensation technique. The system provides scalability as just by coding
the parameters can be changed and modifications can be done without introducing extra
hardware components as in traditional systems.
The proposed Discrete-time control algorithm is implemented on stand-alone system
which can be used for various load resonant applications such as induction heating and
SMPS.
1.2 Objectives
• Replacement of Analog Implementation with Digitalized Discrete-time control.
• Elimination of Traditional PLL for frequency control.
• Implement controller for load Resonant Voltage Source Inverter.
• Achieve Power or Voltage Control and Regulation from 10 to 100 percent with Phase
Shift Controller.
• Optimization of system for increasing efficiency.
• Real Time implementation of a closed loop system with simultaneous frequency and
power tracking.
• Standalone system development.
• Development of customised board with DSP TMS320F28335 as central controller.
• Design of SMPS Load.
• Real time Implementation for Induction Heating Load.
2
11. 1.3 Layout of the Report
A brief chapter by chapter overview is presented here.
Chapter 2: A literature review of analog PLL based controller alongside with discretized
PLL-less controller for Load resonant inverters and different topologies for SMPS.
Chapter 3: The digital controller proposed to control the phase shift for power control and
frequency over a narrow range for obtaining zero voltage switching (ZVS) is described in this
chapter. It also describes a scheme to optimize the software code for DSP.
Chapter 4: In this chapter the integrated software and hardware implementation is discussed
along with SMPS design.
Chapter 5: The Experimental results are elaborated in this chapter.
Chapter 6: Conclusions and discussion on future course of research work.
3
12. Chapter 2
Literature Review
An inverter is an electronic device or circuitry that converts direct current (DC) to alternating
current (AC). Inverters that operates the load at its resonant frequency are Load Resonant
Inverters. The load can be connected eiter in series or parellel or series-parallel configuation.
This is userd for applications such asd induction heating, switched mode power supplies,
sonar transmitters, fluorescent lighting or ultrasonic generators.
2.1 Induction Heating
Induction Heating is most prominent technology used for industrial heating as well as do-
mestic and medical appliances. But almost all of them use an analog apporach for heating
the loads, which results in low efficiency and losses.
The use of a phase-locked loop (PLL) is also common in the control schemes of Induction
Heating inverters. With the use of a phase-locked loop control, the operating frequency is
automatically adjusted to maintain a small constant lagging phase angle under load parame-
ter variation. However, the PLL circuit introduces inherent delay in frequency control due to
filter and ProportionalIntegral (PI) control block. This delay increases switchingstresses and
occasional control system failure. In addition, a problem of non-linear phase-shift variation
is often encountered due to frequency variation in such converter. Basic problems in control
system industries are inflexibility in control-automation, poor reliability due to component
degradation and noise prone circuits resulting in occasional control-failure[2]
Thus, with proposed discrete-time control algorithm for a PSC-PFM control strategy
based on resonant current tracking following advantages are achieved: (1) control simplicity;
(2) efficient frequency tracking as compared to PLL; (3) improved accuracy and linearity in
power regulation due to use of dynamic slope compensation technique; (4) simple discrete
time implementation on DSP which reduces noise and also replaces the complex analog
hardware with small DSP chip. [7]
2.2 Switched Mode Power Supply(SMPS)
SMPS which is an electronic power supply that incorporates a switching regulator to convert
elec- trical power efficiently. Like other power supplies, an SMPS transfers power from a
source, like mains power, to a load, such as a personal computer, while converting voltage
and current characteristics. To reduce the size of power supplies intended for use in modem
4
13. computing systems, it is desirable to raise the operating frequency to reduce the size of
reactive components. To reduce the higher switching losses resulting from higher frequency
operation, resonant power conversion is receiving renewed interest. There are three types of
topologies possible for resonant converters which may be used for high-frequency switching
power supply applications : (1) Series loaded, (2) Parallel loaded and (3) Series-Parallel
loaded.
The main advantage of the series-resonant converter is that the series- resonant capacitors
on the primary side act as a dc block- ing capacitor.For this reason the series-resonant
converter is suitable for high-power ap- plications where a full-bridge converter is desirable.
Another advantage of the series-resonant converter is that the currents in the power devices
decrease as the load decreases.
The series-resonant converter has the main disadvantage that the output voltage cannot
be regulated for the no-load case. Another disadvantage of this converter is that the output
dc filter capacitor must carry high ripple current.
The parallel-resonant converter is suitable for low-out- put-voltage high-output-current
applications. This is due to the fact that the dc filter on the low-voltage-output side of the
transformer is of the inductor input type and, there- fore, dc output capacitors capable of
carrying very high ripple currents are not needed. The main disadvantage of the parallel-
resonant converter is that the current carried by the power FETs and resonant components
is relatively independent of load.
The combination series-parallel converter attempts to take advantage of the best char-
acteristics of the series and the parallel converter while eliminating their weak points (lack
of no-load regulation for the series-resonant con- verter and circulating current independent
of load for the parallel-resonant converter). Thus, the design done is using series-parallel
topology. [12]
5
14. Chapter 3
Process Flow Model and Algorithm
Figure 3.1: System Level Diagram
The proposed digital control consisting of two main blocks: 1. Phase shift controller and
2. Feedback controller. Since the entire system implementation is digital, it provides greater
noise immunity and reliability.
Since high resolution analog to digital converter is used, it is possible to measure very
small fluctuations in current. Phase shift controller is used in this design to overcome the
6
15. drawbacks associated with phase lock loop (PLL).
The Input from AC mains is first connected to a multi tap transformer. This transformer
provides a 15-0-15V output to drive the various PCBs while the other output is used to supply
power for DC bus. This AC signal is passed through a rectifier and filter circuit to generate
required DC bus voltage .
The load generally consist of a series RLC load. In case of Induction Heating, the coil
assumes the role of Inductor while capacitors are connected in series with the coil. The load
current is sensed using a CT or LEM sensor. CT provides a stepped down AC equivalent
version of the load current while the LEM sensor provides a DC voltage as per the calibration.
All the operations performed by the DSP have been described as to be performed by four
logical blocks titled Acquisitionandprocessing, ControlAlgorithm, Timer and Gate pulse
generator.
I(load) indicated the current sensed by CT while V(load) is the sensed quasi square
voltage. These the sensed current and voltage has to be attenuated to desired level. The
current must also be DC shifted by 1.5 V to convert it to unipolar signal to be feed to the
ADC of the DSP. The enunciated current and voltage are represented but i and v respectively.
i and v are then sampled and quantized by the ADC. The Acquisition and pre-processing
block in the 3.1 represents the logic block which will convert the sampled values in the range
0 - 4095 to 0 - 3.0 and also deduct 1.5 from each sampled value to compensate for the DC
shift provided by the Attenuator and level shifter block.
The logical block Control Algorithm represents the entire discrete time controller imple-
mentation including the feedback controller. The details of the discrete time controller and
the feedback PI controller have been discussed in detail in next section .
Timer logic block refers to the initialization and configuration of the CPU timer which
is responsible to trigger the start of conversion and capture. Gate Pulse Generator block
refers to the initialization and updating of the physical GPIO pins where the gate pulses are
obtained.
The DC Level Shifter is required to shift the voltage of gate pulses G1, G2, G3 and G4
from 0-3.3V range to 0-15V range required to drive the Gate Drivers.
3.1 Mathematical Model
The controller is a self generating in nature and thus a starting oscillator is needed to initially
start the inverter current oscillations for the first time. After initial start by forced oscillator
mode, it can be shifted to tracking mode through internal software instruction. A second
order Harmonic Oscillator is implemented for generating initial start-up oscillations. The
discrete-time equations for a sine-cosine oscillator are given as follows:
x(n + 1) = x(n) + ω∆Ts · y(n); x(0) = 0 (3.1)
y(n + 1) = y(n) − ω∆Ts · x(n); y(0) = 1 (3.2)
Where, x is sine wave whereas y is a cosine wave signal, ∆Ts is a sampling time-step and ω
is a desired angular frequency and essentially an input to the oscillator.
3.1.1 Phase Shifter and Attenuator
The sine-cosine generated above is 6 samples phase shifted and attenuated by factor of 0.7
in the algorithm. This new sine-cosine is compared with the old sine-cosine to generate a
7
16. complementary pair of square waves: out1 and out2. Fig.3.2 has the old sine-cosine refered
as i0 and phase shifted and attenuated wave as ipsa whose comparison results in square wave
vsqr.
Figure 3.2: Phase Shifter and Attenuator
3.1.2 Resonant Current Tracking controller
The system is controlled using phase shift method which reduces the control complexity,
enables operation at frequencies beyond 25 kHz, provides improved accuracy and linearity in
power regulation, replacement of analog circuits with simple digital implementation thereby
improving noise immunity[7]. It has also been proved that Phase shift method is better
than other control methods like Phase Frequency Modulation (PFM)[9] thereby making it a
suitable for the proposed controller.
After initial start by harmonic oscillator, changeover to tracking mode is done. The
current sensed from resonant inverter is passed through discrete-time phase shifter and at-
tenuator as described in above section.
The discrete time phase shifter and attenuation block is implemented from following
discrete-time equation:
v(n) = M · {v(n − 1) +
Ts
t
· [i0(n) − v(n − 1)]} (3.3)
where, n is the current time-step, i0 is load current, Ts is a sampling time period, M is
attenuation factor and is a time constant for the phase-shifter. The attenuation factor and
phase shifter time constant has been calculated to for the desired phase angle between the
load current and generated Quasi-square wave[10][3].
3.1.3 Phase shifted PWM Control
Power Regulation
A proportional-integral (PI) feedback controller has been implemented and optimized to suit
the requirement of fast power tracking and operation over wide range of frequencies. The
input voltage and current are fed to the PI controller to calculate the consumed power.
8
17. The instantaneous inverter power can be calculated by taking the product of instan-
taneous inverter voltage and instantaneous inverter current. The inverter voltage can be
calculated indirectly by multiplying the inverter switching function with the sensed dc-bus
voltage. The discrete time equation for power control is given below:
pac(n) = vdc(n) · [G1(n) − G4(n)] · i0(n) (3.4)
The average output power pout can be calculated by passing the instantaneous power through
a first-order low pass filter whose discrete-time equation is similar to Eq.3.3.
The average power thus calculated is compared with a reference power and the error is
passed through a discrete time PI controller. This compensated error signal is called as vpsc.
The time domain equation for the PI controller is given as:
vpsc p(n) = kp · e(n − 1) (3.5)
vpsc i(n) = ki · vpsc i(n − 1) +
Ts
2
· [e(n) + e(n − 1)] (3.6)
vpsc(n) = vpsc p(n) + vpsc i(n) (3.7)
Here, e(n) is the input to the P-I controller, that is essentially an error signal. If the inverter
power is greater than the reference, then the controller responds by reducing the phase shift
angle φ, and vice-versa.
Optimal tuning is obtained by considering the effect of each variable of the controller as
shown in Table 3.1.
Table 3.1: PI Modeling Parameters
Symbol Description Effects
lpf k Filter smoothing factor The maximum value can be 0.001. For lower
value, filtering is better but settling time
increases.
kp Proportional gain, a tuning
parameter
Higher the value of kr, lesser the settling time
but steady state ripple will increase.
ki Integral gain, a tuning parameter Higher the value of ki, steady state response
will have lesser ripple.
The DC component of the delivered power is obtained by filtering the apparent power
through a Low Pass Filter. This DC power is compared with the reference power and the
resulting difference is used by the PI controller to generate an error signal which is used
for comparison with the ramp signal explained in Resonant Current Tracking Controller
Section.
The PI controller has been designed in such a way that the error signal will never over-
shoot the maximum amplitude attained by the ramp signal. Further, the upper threshold
level is set to 0.8V while the lower threshold to 0.2V. This is done in order to avoid large
fluctuations during power tracking which results in better power control and reduced settling
time. The maximum limit has been set to avoid excessive power delivery to the load and to
provide essential dead time.
9
18. Ramp Generation and Slope Compensation
A ramp waveform is generated by integrating the signal vsqr with an integration constant
OR slope: slope.
The integrator output, given by int1 and int2, increases linearly whenever the signal vsqr
is HIGH and is in reset condition for LOW status. The integrator time constant slope1 or
slope of the ramp can-not be fixed at the constant value and should be adjusted dynamically
with the frequency. To get the linear control of the phase-shift controller and hence to
ensure the stability of the power regulation loop, the height of the ramp should be always
maintained constant at unity. This needs to dynamically calculate the value of slope1 at
each resonant cycle.
The following steps are adapted to calculate slope:
• Begin a free running counter sc at the rising edge of the signal vsqr, defined as out1
and out2 for complementary pair.
• Increment sc sample by sample till the falling edge of vsqr is reached.
• The inverse of the counter sc thus obtained after incrementation iteration will give the
required ramp slope.
Thus, the dynamically calculated slope would be used to generate the ramp signals
ramp1 and ramp2. The compensated error signal vpsc(n) is then compared with both the
ramp signals to generate the gating signal G4 with some digital logic. The gating signal G3
is complementary to G4 with adequate dead-time.
The systematic flow with waveforms is as shown in Fig.3.3.
10
20. 3.2 Software Model for Control Algorithm
The flowchart of the algorithm for frequency, phase and power tracking for induction heating
is shown in Fig. 3.4.
Main Routine
(System control loop)
Timer 0 ISR
(Frequency tracking)
Supply
turned ON
Initialize DSP
Timer 0 Interrupt
(Triggered every 2.5µs)
No
Yes
Initialize Timer 0 and Timer 1,
GPIO, EPWM and ADC
Switch
ON ?
Reset gate pulses
Yes First 250
cycles?
Internal harmonic
oscillator
Phase shifter and attenuator
Comparator
Unit Ramp Generator
Enable external interrupts and
Timers
No
Yes
XINT
?
Reset gate pulses and turn
Switch OFF
Unit Ramp Generator
Gate Pulse Generator
Return
Timer 0 ISR
(Frequency tracking)
Timer 1 ISR
(Power control)
Timer 0 Interrupt
(Triggered every 2.5µs)
Timer 1 Interrupt
(Triggered every 10 µs)
NoFirst 250
cycles?
Take sample
form ADC
Phase shifter and attenuator
Comparator
Unit Ramp Generator
Power calculation
Filter
Error amplifier
PI controller
Return Verror
Globally accessible Buffer
Unit Ramp Generator
Gate Pulse Generator
Return
Verror
Figure 3.4: Software Model for Control Algorithm
The implementation of code is divided in following three sections:
3.2.1 Main routine
Here the initialization of the DSP hardware takes place. Then the required modules for the
execution of control logic are initialized. That includes ADC, Timers, EPWM blocks for
ADC triggering and General purpose I/O pins. The systems then waits for the switch to be
turned ON . Once turned ON it with infinitly drive the system till an external interrupt is
received. Interrupt pins are continuously checked for emergency shutdown in case of water
level drop down, no load or overheating conditions.
The frequency and power tracking algorithm are divided into two distinct codes. This
is done because under normal circumstances, it is frequency that varies rapidly but the
variations in power is gradual. Thus frequency tracking must be done at shorter intervals
then power tracking. Hence as shown in Fig.3.4, the Timer0 is triggered over shorter interval
of time than Timer1.
12
21. 3.2.2 Timer0 subroutine
This subroutine is called at every 2.5µs. Soft start is implemented for smooth start. This
segment is responsible for frequnecy and phase tracking. It implements the phase shifter
and attenuator block. Output of this block and the input signal are then compared using a
comparator to give rise to a leading edge square wave with respect to input signal. The most
distinguishing feature of the algorithm is the unity ramp generator (auto slope compensator),
which adjusts itself to unity amplitude irrespective of frequency. Using this wave, the gate
pulse generator produces 4 gate pulses having equal phase shifts and frequency equal to the
input current.
Within the gate pulse generator comparison of the resulting signal with the original signal
results in a square wave v. A ramp waveform is generated by integrating the signal v with and
slope k which is dynamically computed. The integrator output increases linearly whenever
the signal v is HIGH and is in reset condition for LOW status. The height of the ramp
should be always maintained constant at unity to get the linear control of the phase-shift
controller and hence to ensure the stability of the power regulation loop. This necessitates
use of an efficient dynamic slope compensation technique to calculate the value of k for each
cycle.
The ramp is compared with the Error voltage generated from the power controller loop
in every cycle. If the ramp voltage is greater than error voltage, it gives a HIGH status
otherwise LOW. This results in another square wave being generated. The square wave is
then passed through a series of logic gates comprising of AND, OR and XOR and finally
through a D-Flip Flop to generate phase shifted gate pulses to be applied to the two legs
of the IGBTs. These gate pulses have the same frequency as the load current and hence
frequency tracking takes place.
3.2.3 Timer1 subroutine
This subroutine takes input Iac (Load Current), Vac(Load Voltage) and Pref (Reference
Power). Iac and Vac are obtained from on-board high speed ADC of DSP. As this is the
power tracking loop it is a called at a lower frequency of 25µs. The apparent power is
calculated using real time inputs Iac and Vac. It is then passed through a digital low pass
filter to extract the true power. This power is then compared with the reference power to
give an error signal which when processed and normalized results in generation of Verror.
3.3 Code optimization
Due to code optimization, substantial reduction in processing time is possible which would
result in increased operating frequencies. The optimization for time as well as memory has
been achieved to improve the overall performance.
13
22. 3.3.1 Time optimization
• Replace Global to local variables:
The access time for global variable is larger compared to variable defined within the
scope. The compiler must cache the value of a global variable in a register which results
in extra (often unnecessary) loads and stores when globals are in use[11]. Therefore
global variables should not be used inside critical loops. This was practically tested in
our algorithm which had 30 variables .When all variables except those used by plotting
tool were localized, a drastic time reduction of 3µs was accheived.
• Replace float division with integer:
Floating point division requires multiple instruction cycles to execute. In Texas DSP
TMS320F28335, it was practically observed that one float division required approx-
imately 140 assembly instructions to be executed. This can be eliminated if one of
the operands is an integer. In such a case, the floating point division is replaced by
following two steps. 1) Convert the fraction to equivalent fraction such that denomi-
nator is integer value, 2) Multiply numerator with a high power of ten and divide it
by the integer denominator, 3) Multiply the obtained value with inverse power of ten
of the same magnitude as used in step 2. The above set of operations take 500ns for
execution. This results in approximately 50% reduction of execution time of a single
floating point division. As the code consist of multiple floating point divisions, a sig-
nificant time reduction of 3µs was achieved. Additional reduction is execution time is
achieved by replacing entry control check by exit control check.
• Usage of Optimal data-type:
Default variables are treated as variables with double data-type. Float variables con-
sume less memory and fewer registers, and are more efficient. Computation speed can
be increased by using variables with float data-type instead of double. Using word-size
variables helps in faster execution as well as better memory utilization compared to
other data-types. The shift operations performed by the processor to generate 8 and
16 bit registers can be avoided by using int and ‘unsigned int’ for local variables. Thus
32 bit operations require lesser time to execute then 8 bit short integer type.
Table 3.2: Summary of Optimization
Changes
Time
Difference
Final
Time
Reduction of arrays (8 array) 3.6µs 8.4µs
Global to local (35 floating point variables) 3µs 5.4µs
Compiler Level Optimization 1.2µs 4.2µs
Complimentary Signal Computation 1µs 3.2µs
Float to Integer Equivalent Division 900ns 2.3µs
Conditional to logical Computation 700ns 1.6µs
if Statement Reduction 200ns 1.4µs
14
23. 3.3.2 Memory optimization
• Use of generic arrays:
Using generic buffers instead of dedicated buffers of each variable results in significant
reduction in storage space. Four generic floating point buffers are used in this code.
Variables to be monitored are assigned to these buffers eliminating the need to use
separate buffer for each variable to be monitored. Parameters whose current state
depends on the previous state are represented by two variables instead using an array
for the variable.
Table 3.2 summarizes the various optimizations discussed above along with the corre-
sponding reduction in execution time. The final execution time is 1.4µs.
15
24. Chapter 4
Implementation and Design
4.1 Hardware and software components
The DSP TMS320F28335 is a fully integrated evaluation platform from Texas Instruments
and is used as a controller unit for the resonant load inverter under test. This DSP controller
has been selected because of its low cost, embedded floating point unit, high clock speed,
high speed high resolution on-chip ADCs and high performance PWM unit.
In order to meet the specific needs of this application a compact customized board has
been developed. This board features DSP TMS320F28335 as central controller which is
interfaced with a 12-bit DAC and four indicator LEDs. Interfaces for I2C and SPI are also
provided.The board has been designed in such a way that the box connector is pin-to-pin
compatible with Semikron IGBT Gate Driver Module. Fig.4.1 shows the developed board
along with the Texas Instruments XDS100v1 USB Emulator.
Figure 4.1: Customized DSP Board
16
25. The integrated development environment (IDE) used is Code Composer Studio (CCS)
which serves as platform for simulation, emulation and debugging of standalone system for
embedded control systems. The code is flashed onto the chip and debugged through Texas
Instruments XDS100v1 USB Emulator for standalone application.
4.2 Soft Start control
As the input to the controller is the load current itself, when the system is turned ON, the
system requires an appropriate initialization. A part of the code is required for stabilizing
the system once it is switched ON. So initially the soft start code helps the system work
at a constant frequency till the system is stabilized. This works as an open loop system
by using an internal harmonic oscillator for a predetermined time and then switches to the
external input where it then operates as a closed loop system. The soft start is implemented
in timer 0 ISR for first 250 cycles where the inverter is operated at a predefined frequency of
30kHz using Internally generated sine wave. Euler’s equations are used for implementation
of discrete time harmonic oscillator.
Once the system starts operating, samples are acquired through the ADC. The ADC
starts sampling upon receiving a software trigger and can sample upto 16 different analog
input signals. The digital value of the input analog voltage is derived by Eq.4.1
D =
0 when input ≤ 0V
4095 × I−ADCLO
3
when 0V < input < 3V
4095 when input ≥ 3V
(4.1)
where D= Digital Value, I=Input Analog Voltage and ADCLO= Analog Ground
In order to input such sinusoidal AC signal into the DSP controller, offset circuit is
required to range between 0 and 3V converted to 0 and 4095 respectively. This external
offset has to be compensated internally by the code to receive true bidirectional signal.
Table 4.1: System specifications used during Experimentation
Symbol Description Value
lpf k Filter smoothing factor 0.001
kp Proportional gain, a tuning parameter 100
ki Integral gain, a tuning parameter 3300
Vdc DC bus voltage 300V
Pmin Minimum reference power 1kW
Pmax Maximum reference power 10kW
INT1 Timer 1 period ( Frequency tracking period ) 2.5µs
INT2 Timer 2 period ( Power tracking period ) 10µs
Tsample ADC sampling rate 80ns
17
26. 4.3 Experimental setup for Induction heating
Fig.4.2 shows the experimental setup developed in college. The semikron IGBT unit used
has built in gate drivers and air cooling mechanism. The unit has three legs of IGBT modules
and hence can be used for three phase testing. For our project, we have used only two legs
for single phase testing. A 15V supply has to be connected for suppling power to gate driver
while the voltage from auto transformer is used to generate the DC bus voltage. The resulting
quasi square wave on application of gate pulses are observed on the POWERSCOPE.
Technocratic support for prototype development and full power testing is sponsored by
Riddhi Heatron Pvt. Ltd. The setup consist of the following major components:
• Isolation transformer
• Two half bridge SEMIKRON IGBT Modules:
SKM200GB125D along-with two SEMIKRON SkyperPro-32 drivers
• Two Water cooled capacitors of 2.4µ F
• Two Snubber capacitors
• High voltage Rectifier diodes
• Single phase Toroid
• Multi-tap transformer
• Coil with graphite crucible
• Water pump
The Gate pulses generated from the DSP board are connected to the input of SEMIKRON
IGBT gate drivers. The output of gate drivers is connected to appropriate terminals of the
IGBT module. Here care has to be taken that the wires caring gate and emmiter pulses must
be twisted to avoid the effect of noise. The supply from AC mains is connected to high power
diode and capacitor connection to obtain the DC bus voltage. The positive DC bus voltage
is connected to the collector of upper IGBT with the negative to the emitter. The output
from the midpoints of the IGBT modules drives the primary of the isolation transformer.
The isolation transformer provides impedance matching for the load. The secondary consist
of a 1.2µF capacitor and copper coil with an inductance of 21.6µH. The resonant frequency
of about 29 kHz.This setup is shown in Fig.4.3
18
28. 4.4 SMPS design
4.4.1 Resonant Inductor and Capacitor
Fig.4.4 shows the Series-Parallel Topology, where A and B are the points shown in System
Level Diagram Fig.3.1. This is a SMPS load which is placed instead of Induction heating
load discussed before.
Figure 4.4: Series-Parallel Resonant converter
In Fig.4.4 RL is the output load resistance; L is resonant inductor; Cp and Cs are parallel
and series resonant capacitors respectively. Usually they are taken to be of same value, let it
be C. Lf is filter inductor and and Cf is the filter capacitor at the output stage to eliminate
ripples obtained from rectifier bridge and give pure DC voltage. We assume the value of Lf
to be 0.03mH and Cf to be around 220µF. Vp is the DC bus voltage across A and B at
IGBT H-bridge output. It has been calculated to be 300V for single phase, which gives 600V
for three phase. Vs is the desired regulated voltage according to the SMPS application. In
our case we have assumed it to be 48V . Also a Current Transformer with burden resistance
of 10Ω/ 5W is used to sense current.
Let output power be P= 5kW and desired regulated voltage be Vs=48V with DC bus
voltage Vp=600V . Thus, RL is given by Eq.4.2
RL =
V 2
s
P
(4.2)
For series-parallel resonant converter the equivalent secondary resistance is given as :
Rs =
π2
8
RL (4.3)
Operating frequency is taken to be fs=10kHz and quality factor Q is chosen as unity. QThe
quality factor is given as:
Q =
L
C
Rp
(4.4)
20
29. For transformer with turn ratio n :1 (let n=10), Rp is the primary resistance which is given
as:
Rp = n2
Rs (4.5)
The operating frequency fo can be written as :
fs =
1
2π
√
LC
(4.6)
By solving Eq.4.4 and Eq.4.6 values of L and C are found out.
After the calculations as per above steps, final design specifications are:
RL=0.4608Ω , Cp=Cs=0.28µF and L=0.904mH
For safety purposes, the system has been operated on single phase with Vp=300V and
Vs=60V which gives transformer ratio 5:1. Cp=Cs is used as 0.33µF which is standard value
available in market.
4.4.2 Design of Inductor
Figure 4.5: EE core Inductor block diagram
The Resonant inductor and filter inductor is designed using EE ferrite core. The block
diagram of general EE core inductor is as shown in Fig.4.5.
N =
Lv · Im
Ac · Bm
(4.7)
Where, Lv is value of inductor to be designed in Henry, Im is maximum current flowing
through the inductor i.e 6A for resonant inductor L and 25A for filter inductor Lf , Ac is
core area i.e 266mm2
for L and 182mm2
for Lf , and Bm is flux density taken as 0.2T.
According to Area Product Approach Ap ≤ Ap(act),where Ap is Area Product and Ap(act)
is Actual Area Product. Ap and Ap(act) are given by Eq.4.8 and Eq.4.9 respectively.
Ap =
2 · E
Kw · Kc · J · Bm
(4.8)
21
30. Where, E = 0.5·Lv ·Im
2
is the energy, J is current density taken as 3A/mm2
, Kw is window
utilization factor taken as 0.6, Kc is core utilization factor taken as 1 and Bm is Flux density
taken as 0.2T.
Ap(act) = Aw · Ac (4.9)
If Ap ≤ Ap(act) condition is satisfied, the design can be practically implemented. For Resonant
inductor L number of turns comes out to be 100 and for filter inductor Lf it comes 20 turns.
The inductance is calibrated using LCR meter and adding paper or air gap Lg.
4.4.3 Design of Transformer
Figure 4.6: Transformer block diagram
The transformer required is a 5:1 step down transformer with 300V at primary and around
60V at secondary. A soft ferrite core toroid is used upon which primary and secondary are
wound using Teflon wire.
To calculate the number of turns at primary Np we use Eq.4.10.
Np =
Vp
4 · Ac · Bm · fs
(4.10)
Where, Vp is Primary voltage which is the DC bus voltage 300V . Ac is Core area in m2
calculated by taking product of height and thickness of the core, which comes out to be
4.44 × 10−4
m2
. Bm Flux Density selected based upon frequency of operation. Bm has been
taken as 0.2T and operating frequency fs is taken to be 10kHz [13].
Substituting all values Np comes out to be 85 turns. Thus number of turns on secondary
side Ns comes out to be 17 as turn ratio is 5:1.
Using Area Product Approach, the Area Product Ap should be less than or equal to the
Actual Area Product Ap(act). Ap and Ap(act) are given by Eq.4.11 and Eq.4.12 respectively.
Ap =
P · (
√
2 + 1
η
)
4 · Kw · Bm · fs
(4.11)
22
31. Where, P is power taken as 1000W, Kw is window utilization factor taken as 0.6, η is
efficiency taken as 0.9, J is current density taken as 3 × 106
A/m2
, Bm is flux density taken
as 0.2T and fs is operating frequency taken as 10kHz.
Ap(act) = Aw · Ac (4.12)
Where, Aw is window area given by πD2
4
(D = 10.4cm is diameter of window as shown in
Fig.4.6) and Ac is the core area as calculated before is 4.44 × 10−4
m2
.
Thus Ap comes out to be 1.75×10−7
m4
and Ap(act) comes as 37.1×10−7
m4
. As Ap ≤ Ap(act)
condition is satisfied, the design can be practically implemented.
Figure 4.7: Handmade Transformer
The toroid is wrapped with fiber cloth and then 85 turns of primary are wounded on it.
A layer of insulation tape is applied and then 17 turns of secondary are wounded on it. As
current at primary is 5A and secondary is 25A, a wire of larger cross-sectional area is used
at the secondary side. In order to reduce skin effect a twisted pair of multi-stranded Teflon
wires is used at the secondary side. Fig.4.7 shows the transformer thus made.
4.4.4 Design of Current Transformer
A current transformer(CT) produces an alternating current (AC) in its secondary which is
proportional to the AC in its primary. It is used to measure the current in the primary side
of transformer as shown in Fig.4.4. The CT has turn ratio of 1 : N, where N is number
of turns at secondary which are wounded on toroid. As at primary of CT maximum 10A
current will flow ( i.e the current at primary of the transformer which is to be measured)
23
32. Figure 4.8: Transformer block diagram
Figure 4.9: Handmade Current Transformer
and at secondary of CT a burden resistance of 10Ω/5W is connected. So in order to get 1V
at the secondary of CT, N comes out to be 100 turns.
The toroid is wrapped with fiber cloth and then 100 turns of secondary of CT are wounded
on it, and covered with the insulation tape. The wire passing through the CT will act as its
primary and as current produced in secondary is proportional to the current in primary of
CT, the current can be measured by connecting a burden resistance at two end of secondary
of CT. Fig.4.9 shows the CT thus made.
24
33. 4.5 Experimental setup for SMPS
Figure 4.10: Laboratory Steup for SMPS Load
Fig.4.10 shows the complete experimental setup of a working SMPS prototype. The gate
pulses generated are given to the gate driver input. The IGBT module used has built in gate
drivers and also generates the required DC bus voltage. Fig.4.11shows the detailed view of
components the form the SMPS load. the design as well as the details have been discussed
in previous sections.
A summary of all components used in SMPS load with their specification is given in
Table.4.2
Table 4.2: Components with their specification used during Experimentation
Component Specification
Resonant Inductor L 0.9mH; EE - 65
Resonant CapacitorCs = Cp 0.33µF snubber
Current Transformer T- 45 Toroid with 100 turns
Burden Resistance 10Ω / 5W
Transformer T- 150 Toroid with Np=85 and Ns=17
Schottky Diode for Rectifier bridge STPS80150C ; 150V /60A
Filter Inductor 0.03mH; EE - 42
Filter Capacitor Bank of 5 parallel capacitors of 47µF / 160V
25
35. Chapter 5
Experimental Results
The algorithm simply takes a near sinusoidal waveform to produce gate pulses and is in-
dependent of the source of generation of this signal. This gives it the flexibility to operate
different resonant loads such as Induction heaters and SMPS.
5.1 Simulation Results
(a) Slope compensated ramp signal
Time (µs)
Power(W)
Time (µs)
(b) Pref =1.5kW and Pref =3kW
Figure 5.1: The performance of Power Regulation algorithm
27
36. The digital controller has been tested as hardware in loop as well as in Real-time on DSP
TMS320F28335. The results of hardware in loop have been used to verify the analytically
obtained results.
Fig.5.1a shows the output of ramp generator. Due to implementation of dynamic slope
compensation technique, the amplitude always remains unity. As shown in Fig.5.1b, the
actual power is close to the reference power. Fig.5.2 shows the load current and the corre-
sponding quasi-square waveform for reference power of 4kW.
Figure 5.2: Waveforms for Reference Power of 4kW
Fig.5.3 shows the load current and the corresponding quasi-square waveform for reference
power of 3kW.
Figure 5.3: Waveforms for Reference Power of 3kW
5.2 Real-Time Results
Fig.5.4 shows the timing diagram of Timer-1 ISR. The code has been optimized to achieve
an execution time Te of 4µs, 800ns are being utilized for switching between interrupts of
timer and ADC while the rest of 300ns has been given as buffer time to allow the system
to stabilize before the next iteration.Thus the period of ISR (T) is configured to 2.5µs. The
results obtained are in accordance with the results obtained from hardware in loop execution
[10].
The designed controller is tested on an industrial induction heating setup by replacing the
analog controller with this new digital controller. The reference power is varied from 1kW to
28
37. 6kW. The DC bus voltage was fixed to 300V. Table 4.1 gives the values of various parameters
used to obtain the experimental results. The currents and voltages were normalized and used
as input for PI controller.
Figure 5.4: Timing Diagram showing Triggering time (2.5µs) and Execution time (1.4µs)
Fig.5.5 shows the sensed inverter voltage and inverter current waveforms obtained form
experimental setup. From the figure, we see that the quasi square wave leads load current as
proposed in the theory [7]. Implementation of the frequency tracking technique can enable
resonant current tracking upto 40kHz.
The minimum phase shift between the inverter voltage and inverter current is maintained
over a wide range of reference power. This is because the algorithm is designed in such a
way that it automatically forces the frequency to slightly increase for lower duty cycle and
decrease for higher duty cycle to maintain constant phase angle between the inverter rising
edge and the resonant current zero crossing.
29
38. V
i
inv
0
Ch−1: 7A/Div
Ch−2: 100V/Div
(a) at 1.5kW Output Power
i 0
Ch−1: 7A/Div
Ch−2: 100V/Div
Vinv
(b) at 3kW Output Power
i 0
Ch−1: 14A/Div
Ch−2: 100V/Div
Vinv
(c) at 6kW Output Power
Figure 5.5: The Oscillogram showing inverter voltage and current at different powers
30
39. Chapter 6
Conclusion and Future Work
A digital control system of resonant load inverter at laboratory scale is described in detail
including PI modeling, optimization, controller algorithm, simulation and real-time imple-
mentation. We can draw the following conclusions form the results obtained from experi-
mentation:
1. Frequency tracking is acheived without the use of PLL
2. The system is capable of operating over a wide range of reference power.
3. The output quasi square wave always leads the input load current by a constant phase
angle.
4. This system can operate at full power without the need of external pre-regulator.
The presented results conclude that a fully digital control can be acheived using the
proposed controller. Considerable increase in the operating frequency for inverters due to
code optimization is possible. Further, once the parameters for a particular application
are set in the algorithm, it will operate autonomously and will not require any human
intervention. All blocks from signal capture stage to generation of pulses are implemented
on a digital controller. It also has inherent mechanisms to safely turn-off the system in case
of any failure. Thus the overall life of the system is prolonged.
Future scope for extension of this project includes optimization of the code to enable
sampling at even higher rates. The operating frequency can be increased by using multiple
techniques. One technique is to write assembly code directly instead of C-language with
C cross-compiler. But this would increase the programming complexity and difficulty for
maintanence and upgradation of algorithm. Second technique could be interfacing a high
speed ADC with DSP which would execute the algorithm while executing the output stage on
a FPGA. Third approach is using reconfigurable computing where the entire signal processing
and output stage will be executed by a FPGA which would be interfaced with a high speed
ADC resulting in reduced execution time due to parallel processing. Proposed controller can
also be tested for high-power resonant converter for switched-mode power supply.
31
40. Bibliography
[1] Enrique J Dede et. al. “25kW, 50kW generator for induction heating”, IEEE Transactions
on industrial Electronics, 38(3):203-209, 1991
[2] Lucia, Oscar and Maussion, Pascal and Dede, Enrique and Burdio, Jose M. “Induction
Heating Technology and Its Applications: Past Developments, Current Technology and
Future Challenges.” IEEE Transactions on Industrial Electronics, vol. 61, pp. 2509-2520,
2013.
[3] Texas Instrument: Digital Signal Processor Selection [Online]. Available:
http://www.ti.com/lsds/ti/processors/dsp/products.pageparametrics.
[4] Bo You; Jie Wang; Songyang Li, “FPGA-based induction heating with variable modulus
control all-digital Phase-Locked Loop research,” Measurement, Information and Control
(ICMIC), 2013 International Conference, vol.02, no., pp.1099-1102, 16-18 Aug. 2013.
[5] Hui Zhu; Chengyong Wang; Yonglong Peng; Yabin Li, “The study of novel PDM-based
Induction heating frequency tracking control”, Power Electronics and Motion Control
Conference (IPEMC), 2012 7th International, vol.4, no., pp.2893-2897, 2-5 June 2012.
[6] Roy, M.; Sengupta, M., “Application of FPGA based PLL in a CSI fed induction heat-
ing prototype”, Power Electronics, Drives and Energy Systems (PEDES), 2014 IEEE
International Conference , vol., no., pp.1-4, 16-19 Dec. 2014.
[7] Sawant R.R.; Rao Y.S., “A discrete-time controller for Phase Shift Controlled load-
resonant inverter without PLL”, Power Electronics, Drives and Energy Systems (PEDES),
IEEE International Conference , vol., no., pp.1, 4, 16-19 Dec. 2014.
[8] TMS320F28335 (ACTIVE) Delfino Microcontroller[Online]. Available:
http://www.ti.com/product/tms320f28335.
[9] Kubota, Sachio; Yamamoto, Naoki; Shimaoka, Yoshihiro; Ito, Fumio, “Novel power sup-
ply for induction heating with power factor control using phase shift”, Power Electron-
ics and Motion Control Conference (EPE/PEMC), 2012 15th International, vol., no.,
pp.DS1b.15-1-DS1b.15-8, 4-6 Sept. 2012.
[10] Sawant, R.R.; Chame, N.S.; Rana, N.K.,“A New Hybrid Power Control Technique for
Induction Vessel Heating System”, ICIT 2006. IEEE International Conference , vol., no.,
pp.1424, 1429, 15-17 Dec. 2006.
[11] H. Sankaranarayanan and P. Kulkarni, “Source-to-Source Refactoring and Elimination
of Global Variables in C Programs”, Journal of Software Engineering and Applications,
Vol. 6 No. 5, pp. 264-273, 2013.
32
41. [12] Robert L. Steigemald, “Practical Design Methodologies for Load Resonant Converters
Operating Above Resonanace”, GE Corporate RD
[13] Transformer Design with Magnetics Ferrite Cores [Online]. Available: https://www.mag-
inc.com/design/design-guides/Transformer-Design-with-Magnetics-Ferrite-Cores.
33
