This document discusses strategies for optimizing software design on the Blackfin processor to increase performance and reduce power consumption. It describes techniques such as optimizing use of internal memory like L1 instruction and data SRAM, using code overlays, and taking advantage of different power modes. Example implementations for audio and video players are provided to illustrate these concepts.
The document discusses verification of simultaneous multi-threading (SMT) in IBM POWER5 and POWER6 high-performance processors. SMT allows a processor core to execute multiple instruction streams simultaneously, appearing as virtual processor cores to software. Verifying SMT presented significant challenges due to the greatly increased state space from multiple threads. Methodologies evolved from single-thread to leverage traditional symmetric multi-processing approaches applied to single cores. Shared resource conflicts and dynamic thread switching between SMT and single-thread modes required specialized testing.
2010 Honda Civic GX color brochures provided by Atamian Honda located near Boston MA. Find the 2010 Honda Civic GX for sale in Massachusetts; call about our current sales and incentives at 866-312-7474.
2010 Honda Civic GX brochure provided by Checkered Flag Honda located near Virginia Beach, VA. Find the 2010 Honda Civic GX for sale in Virginia; call about our current sales and incentives at (866) 490-FLAG.
Checkered Flag Honda has the inventory to get you on the road and into the perfect vehicle. Our Honda car dealership is stocked with all of the latest models including the new 2010 Civic, Accord, CR-V, Pilot, Insight and many others. Get a great deal on a Honda in Norfolk by calling 866-490-FLAG or visiting Checkered Flag Honda in person.
Overview of the BF609 dual-core Blackfin processor series covering main features including the Pipelined Vision Processor including the hardware and software development tools. By Analog Devices
1. The document discusses various methods for managing memory in the Linux kernel, including physical memory, virtual memory, page tables, and different allocators like kmalloc, vmalloc, and SLAB for allocating memory to processes and the kernel.
2. It explains concepts like physical vs virtual addresses, page tables that map virtual to physical memory, and the Memory Management Unit (MMU) that handles virtual address translation.
3. Different allocators like kmalloc, vmalloc and SLAB are used depending on the size and properties of the memory needed, with kmalloc and SLAB handling physically contiguous memory and vmalloc only requiring virtual contiguity.
All secret codes of samsung mobile phonenendydoank
This document provides a long list of secret codes that can be entered on Samsung mobile phones to access various functions and information. Some of the codes allow users to view software versions, reset network settings, test hardware components, and override locks. Over 80 secret codes are detailed that cover things like viewing IMEI and serial numbers, testing vibrations and sounds, displaying battery and storage information, and resetting language or network settings on Samsung phones.
SlideShare now has a player specifically designed for infographics. Upload your infographics now and see them take off! Need advice on creating infographics? This presentation includes tips for producing stand-out infographics. Read more about the new SlideShare infographics player here: http://wp.me/p24NNG-2ay
This infographic was designed by Column Five: http://columnfivemedia.com/
This document provides tips to avoid common mistakes in PowerPoint presentation design. It identifies the top 5 mistakes as including putting too much information on slides, not using enough visuals, using poor quality or unreadable visuals, having messy slides with poor spacing and alignment, and not properly preparing and practicing the presentation. The document encourages presenters to use fewer words per slide, high quality images and charts, consistent formatting, and to spend significant time crafting an engaging narrative and rehearsing their presentation. It emphasizes that an attractive design is not as important as being an effective storyteller.
The document discusses verification of simultaneous multi-threading (SMT) in IBM POWER5 and POWER6 high-performance processors. SMT allows a processor core to execute multiple instruction streams simultaneously, appearing as virtual processor cores to software. Verifying SMT presented significant challenges due to the greatly increased state space from multiple threads. Methodologies evolved from single-thread to leverage traditional symmetric multi-processing approaches applied to single cores. Shared resource conflicts and dynamic thread switching between SMT and single-thread modes required specialized testing.
2010 Honda Civic GX color brochures provided by Atamian Honda located near Boston MA. Find the 2010 Honda Civic GX for sale in Massachusetts; call about our current sales and incentives at 866-312-7474.
2010 Honda Civic GX brochure provided by Checkered Flag Honda located near Virginia Beach, VA. Find the 2010 Honda Civic GX for sale in Virginia; call about our current sales and incentives at (866) 490-FLAG.
Checkered Flag Honda has the inventory to get you on the road and into the perfect vehicle. Our Honda car dealership is stocked with all of the latest models including the new 2010 Civic, Accord, CR-V, Pilot, Insight and many others. Get a great deal on a Honda in Norfolk by calling 866-490-FLAG or visiting Checkered Flag Honda in person.
Overview of the BF609 dual-core Blackfin processor series covering main features including the Pipelined Vision Processor including the hardware and software development tools. By Analog Devices
1. The document discusses various methods for managing memory in the Linux kernel, including physical memory, virtual memory, page tables, and different allocators like kmalloc, vmalloc, and SLAB for allocating memory to processes and the kernel.
2. It explains concepts like physical vs virtual addresses, page tables that map virtual to physical memory, and the Memory Management Unit (MMU) that handles virtual address translation.
3. Different allocators like kmalloc, vmalloc and SLAB are used depending on the size and properties of the memory needed, with kmalloc and SLAB handling physically contiguous memory and vmalloc only requiring virtual contiguity.
All secret codes of samsung mobile phonenendydoank
This document provides a long list of secret codes that can be entered on Samsung mobile phones to access various functions and information. Some of the codes allow users to view software versions, reset network settings, test hardware components, and override locks. Over 80 secret codes are detailed that cover things like viewing IMEI and serial numbers, testing vibrations and sounds, displaying battery and storage information, and resetting language or network settings on Samsung phones.
SlideShare now has a player specifically designed for infographics. Upload your infographics now and see them take off! Need advice on creating infographics? This presentation includes tips for producing stand-out infographics. Read more about the new SlideShare infographics player here: http://wp.me/p24NNG-2ay
This infographic was designed by Column Five: http://columnfivemedia.com/
This document provides tips to avoid common mistakes in PowerPoint presentation design. It identifies the top 5 mistakes as including putting too much information on slides, not using enough visuals, using poor quality or unreadable visuals, having messy slides with poor spacing and alignment, and not properly preparing and practicing the presentation. The document encourages presenters to use fewer words per slide, high quality images and charts, consistent formatting, and to spend significant time crafting an engaging narrative and rehearsing their presentation. It emphasizes that an attractive design is not as important as being an effective storyteller.
The document discusses IBM Power Systems and POWER7 architecture. It provides an overview of POWER7 performance features including:
- POWER7 has 4 times as many cores per chip compared to POWER6 and a different cache topology with improved latencies.
- Systems can be made from multiple POWER7 chips, with all memory and cache accessible across chips.
- POWER7 introduces simultaneous multi-threading (SMT4) allowing up to 4 instruction streams to execute in parallel per core.
Sun sparc enterprise t5440 server technical presentationxKinAnx
The document provides an agenda for a training course on Sun SPARC Enterprise T5440 rack servers. The agenda includes an introduction, comparison of UltraSPARC T2 and T2 Plus processors, overview of T5440 server features and architecture, memory, networking, I/O expansion, disks, fans, power supplies, Solaris, ILOM 2.0, LDOMs, CRUs/FRUs, tuning and performance, tools and references. It also notes that the information is confidential to Sun Microsystems.
This document provides information about IBM Power Systems servers from 2010. It describes the Power 710, Power 730, Power 720 and Power 740 servers including their processor options, core counts, speeds and I/O capabilities. Power 795 is also mentioned as the highest-end model available at that time, with the Power 780 and Power 755 filling out the mid-range offerings. Details are given about the POWER7 processor architecture, features like Active Memory Expansion, and how Power Systems provide capabilities for performance, throughput, consolidation and energy efficiency.
The one-day training covers technical aspects of NXP's LPC2000 family of ARM7 microcontrollers, including introductions to the ARM7 architecture, LPC2000 devices and development tools. The agenda includes presentations on the ARM7 memory map, peripherals and initialization, as well as examples using evaluation boards and Keil development tools. Supporting slides provide overviews of NXP's ARM-based microcontroller strategy and roadmaps.
The document discusses next generation 8-bit microcontrollers from manufacturers like Atmel and Microchip, outlining their advance features such as larger code memory, lower power consumption, and integrated peripherals. It provides an overview of the AVR and PIC architectures as well as the programming skills needed to work with these microcontrollers, including knowledge of languages like C/C++ and debugging techniques. Selection of a microcontroller depends on requirements and manufacturers offer options across memory sizes, peripherals, and price points.
Sun sparc enterprise t5140 and t5240 servers technical presentationxKinAnx
This document provides an overview of the Sun SPARC Enterprise T5140 and T5240 rack servers. It describes the key technical specifications including the UltraSPARC T2+ dual-socket system architecture with up to 128 threads per server, FB-DIMM memory interface supporting up to 128GB memory, 10GbE and 1GbE networking, PCIe expansion slots, and 1U or 2U rack density with redundant power and cooling. Standard configurations are listed providing various core counts, memory sizes, disk capabilities and power supply options.
The ATmega8 is an 8-bit microcontroller based on the AVR RISC architecture. It achieves high throughput of up to 16 MIPS at 16 MHz through single-cycle execution of powerful instructions. The microcontroller uses a Harvard architecture that separates memory and buses for program and data. It has 8K bytes of flash memory, 512 bytes of EEPROM, and 1K byte of internal RAM. The ATmega8 has three I/O ports (Ports B, C, and D) that can be configured as either inputs or outputs through their associated data direction, pin, and port registers.
ARM was developed in 1983 by Acorn Computers to replace the 6502 processor in BBC microcomputers. It was designed by a small team to be simple and low-power for embedded systems. ARM became very popular due to its low-power consumption and widespread licensing to manufacturers. The ARM architecture uses a load-store design with 32-bit fixed-length instructions and a large register file. It has become dominant in portable devices due to its efficient power-to-performance ratio.
The document provides an overview of the memory hierarchy, bus structure, and additional features of the Blackfin processor core architecture. It describes the Blackfin's use of a memory hierarchy from fast L1 memory to slower L3 memory. It also discusses the internal bus structure, configurable memory that can be used as cache or SRAM, cache management, direct memory access, power management modes, debugging support, and where to find additional resources on Blackfin processors.
This document discusses ARM embedded systems and microprocessors. It covers ARM's RISC design philosophy, instruction set, and embedded system hardware and software components. The hardware components include the ARM processor, controllers, peripherals, and bus architecture. The software components include initialization code, operating systems, and applications. It also describes ARM registers, the program status register, pipelining, exceptions, interrupts, and the instruction set states.
Sun sparc enterprise t5120 and t5220 servers technical presentationxKinAnx
The document provides an agenda and overview of the Sun SPARC Enterprise T5120 and T5220 rack servers. It discusses the UltraSPARC T2 processor featuring up to 8 cores, 64 threads, integrated 10GbE networking and PCIe. It describes the system architecture of the T5x20 servers, including memory, networking, I/O expansion, disks, fans, power supplies and Solaris support. It also covers ILOM 2.0, logical domains, replaceable components, performance tuning tools, and takes questions.
ELCE 2011 - BZ - Embedded Linux Optimization Techniques - How Not To Be SlowBenjamin Zores
This presentation discusses techniques for optimizing embedded Linux systems to improve performance. It covers:
1. Understanding the hardware limitations of embedded devices and selecting appropriate software components.
2. Recognizing that approaches that work for desktop systems are not always suitable for embedded due to resource constraints.
3. Isolating performance bottlenecks through profiling and benchmarks to determine where optimizations are needed.
NuMicro® M480 Series Introduction - Sept.2019Mason Lyu
The NuMicro® M480 series is a high performance, low power microcontroller powered by the Arm® Cortex®-M4F core with DSP extension.
The 512 KB embedded dual bank Flash memory supports OTA (Over-The-Air) firmware upgrade, and the 160 KB embedded SRAM includes 32 KB cache to speed up external SPI Flash code execution.
The 256 KB embedded single bank Flash memory supports up to 4 configurable eXecute-Only-Memory regions, and the 128 KB embedded SRAM provides multi-level retention in standby power-down mode.
The factory pre-loaded bootloader enables Secure Boot functionality to check code integrity inside embedded Flash memory.
The document provides an overview of the Blackfin processor architecture from Analog Devices. It discusses that Blackfin processors combine DSP and microcontroller capabilities on a single core. It describes the Blackfin core components including the arithmetic unit, data registers, addressing unit, and sequencer. It also outlines the Blackfin family processors, development tools, and peripheral features.
The document discusses HPC solutions from HP including purpose-built HPC storage, servers, fabrics, and software infrastructure. It provides details on HP's ProLiant server families including the latest processor offerings, memory technologies, and storage options. Specific server models highlighted include the BL460c Gen8 blade server and SL250s Gen8 half-width tray server. The document also covers HP's Infiniband strategy and portfolio of FDR Infiniband switches, cables, and host channel adapters. Storage solutions mentioned include the HP X9000 network storage and Lustre parallel file systems.
This document summarizes Guillermo Talavera Velilla's PhD thesis defense presentation on optimizing address generation for low-power embedded VLIW processors. The presentation covered:
1) The goal of optimizing energy consumption during address generation for data access in VLIW processors for embedded systems.
2) How embedded systems demand both performance and energy efficiency.
3) Techniques like data transfer and storage exploration that optimize data locality and reduce storage requirements through code transformations.
4) How address calculation and control flow were bottlenecks identified after applying these transformations.
Computer organization & ARM microcontrollers module 3 PPTChetanNaikJECE
The document discusses concepts related to ARM microcontrollers including:
1. The RISC design philosophy aims to deliver simple but powerful instructions that execute in a single cycle at high speeds through placing more intelligence in software than hardware.
2. The ARM architecture uses a RISC design with a load-store architecture, large register set, separated pipelines, and fixed-length instructions.
3. Embedded systems using ARM processors include memory in a hierarchy with cache closer to the processor core and slower secondary memory further away. They also use different memory types like ROM, flash, and DRAM.
The document provides an introduction to the PIC16F877 microcontroller. It discusses that PICs are Harvard architecture microcontrollers made by Microchip with a RISC design. The PIC16F877 has an 8KB program memory, 368 bytes of data memory, and 256 bytes of EEPROM. It features ports, timers, ADC, and communication peripherals. Programming involves writing code, compiling to a hex file, and burning the file onto the PIC's flash memory using a programmer.
Your application has been accepted for an online course offered through Malaviya National Institute of Technology Jaipur. The registration fee is 500 rupees for faculty/students and 1000 rupees for self-employed individuals. To register, you must log in, update your profile, select a course, confirm your registration, and share payment confirmation details with the provided email after paying.
This document provides information on choosing processors and development tools for embedded applications. It discusses different types of processors like microcontrollers, microprocessors, DSPs and FPGAs. It also covers topics like multicore processors, embedded software design flow, hardware design flow, processor selection criteria, embedded development life cycle and more. The goal is to help readers understand the various options available when selecting hardware and tools for their embedded projects.
The document discusses IBM Power Systems and POWER7 architecture. It provides an overview of POWER7 performance features including:
- POWER7 has 4 times as many cores per chip compared to POWER6 and a different cache topology with improved latencies.
- Systems can be made from multiple POWER7 chips, with all memory and cache accessible across chips.
- POWER7 introduces simultaneous multi-threading (SMT4) allowing up to 4 instruction streams to execute in parallel per core.
Sun sparc enterprise t5440 server technical presentationxKinAnx
The document provides an agenda for a training course on Sun SPARC Enterprise T5440 rack servers. The agenda includes an introduction, comparison of UltraSPARC T2 and T2 Plus processors, overview of T5440 server features and architecture, memory, networking, I/O expansion, disks, fans, power supplies, Solaris, ILOM 2.0, LDOMs, CRUs/FRUs, tuning and performance, tools and references. It also notes that the information is confidential to Sun Microsystems.
This document provides information about IBM Power Systems servers from 2010. It describes the Power 710, Power 730, Power 720 and Power 740 servers including their processor options, core counts, speeds and I/O capabilities. Power 795 is also mentioned as the highest-end model available at that time, with the Power 780 and Power 755 filling out the mid-range offerings. Details are given about the POWER7 processor architecture, features like Active Memory Expansion, and how Power Systems provide capabilities for performance, throughput, consolidation and energy efficiency.
The one-day training covers technical aspects of NXP's LPC2000 family of ARM7 microcontrollers, including introductions to the ARM7 architecture, LPC2000 devices and development tools. The agenda includes presentations on the ARM7 memory map, peripherals and initialization, as well as examples using evaluation boards and Keil development tools. Supporting slides provide overviews of NXP's ARM-based microcontroller strategy and roadmaps.
The document discusses next generation 8-bit microcontrollers from manufacturers like Atmel and Microchip, outlining their advance features such as larger code memory, lower power consumption, and integrated peripherals. It provides an overview of the AVR and PIC architectures as well as the programming skills needed to work with these microcontrollers, including knowledge of languages like C/C++ and debugging techniques. Selection of a microcontroller depends on requirements and manufacturers offer options across memory sizes, peripherals, and price points.
Sun sparc enterprise t5140 and t5240 servers technical presentationxKinAnx
This document provides an overview of the Sun SPARC Enterprise T5140 and T5240 rack servers. It describes the key technical specifications including the UltraSPARC T2+ dual-socket system architecture with up to 128 threads per server, FB-DIMM memory interface supporting up to 128GB memory, 10GbE and 1GbE networking, PCIe expansion slots, and 1U or 2U rack density with redundant power and cooling. Standard configurations are listed providing various core counts, memory sizes, disk capabilities and power supply options.
The ATmega8 is an 8-bit microcontroller based on the AVR RISC architecture. It achieves high throughput of up to 16 MIPS at 16 MHz through single-cycle execution of powerful instructions. The microcontroller uses a Harvard architecture that separates memory and buses for program and data. It has 8K bytes of flash memory, 512 bytes of EEPROM, and 1K byte of internal RAM. The ATmega8 has three I/O ports (Ports B, C, and D) that can be configured as either inputs or outputs through their associated data direction, pin, and port registers.
ARM was developed in 1983 by Acorn Computers to replace the 6502 processor in BBC microcomputers. It was designed by a small team to be simple and low-power for embedded systems. ARM became very popular due to its low-power consumption and widespread licensing to manufacturers. The ARM architecture uses a load-store design with 32-bit fixed-length instructions and a large register file. It has become dominant in portable devices due to its efficient power-to-performance ratio.
The document provides an overview of the memory hierarchy, bus structure, and additional features of the Blackfin processor core architecture. It describes the Blackfin's use of a memory hierarchy from fast L1 memory to slower L3 memory. It also discusses the internal bus structure, configurable memory that can be used as cache or SRAM, cache management, direct memory access, power management modes, debugging support, and where to find additional resources on Blackfin processors.
This document discusses ARM embedded systems and microprocessors. It covers ARM's RISC design philosophy, instruction set, and embedded system hardware and software components. The hardware components include the ARM processor, controllers, peripherals, and bus architecture. The software components include initialization code, operating systems, and applications. It also describes ARM registers, the program status register, pipelining, exceptions, interrupts, and the instruction set states.
Sun sparc enterprise t5120 and t5220 servers technical presentationxKinAnx
The document provides an agenda and overview of the Sun SPARC Enterprise T5120 and T5220 rack servers. It discusses the UltraSPARC T2 processor featuring up to 8 cores, 64 threads, integrated 10GbE networking and PCIe. It describes the system architecture of the T5x20 servers, including memory, networking, I/O expansion, disks, fans, power supplies and Solaris support. It also covers ILOM 2.0, logical domains, replaceable components, performance tuning tools, and takes questions.
ELCE 2011 - BZ - Embedded Linux Optimization Techniques - How Not To Be SlowBenjamin Zores
This presentation discusses techniques for optimizing embedded Linux systems to improve performance. It covers:
1. Understanding the hardware limitations of embedded devices and selecting appropriate software components.
2. Recognizing that approaches that work for desktop systems are not always suitable for embedded due to resource constraints.
3. Isolating performance bottlenecks through profiling and benchmarks to determine where optimizations are needed.
NuMicro® M480 Series Introduction - Sept.2019Mason Lyu
The NuMicro® M480 series is a high performance, low power microcontroller powered by the Arm® Cortex®-M4F core with DSP extension.
The 512 KB embedded dual bank Flash memory supports OTA (Over-The-Air) firmware upgrade, and the 160 KB embedded SRAM includes 32 KB cache to speed up external SPI Flash code execution.
The 256 KB embedded single bank Flash memory supports up to 4 configurable eXecute-Only-Memory regions, and the 128 KB embedded SRAM provides multi-level retention in standby power-down mode.
The factory pre-loaded bootloader enables Secure Boot functionality to check code integrity inside embedded Flash memory.
The document provides an overview of the Blackfin processor architecture from Analog Devices. It discusses that Blackfin processors combine DSP and microcontroller capabilities on a single core. It describes the Blackfin core components including the arithmetic unit, data registers, addressing unit, and sequencer. It also outlines the Blackfin family processors, development tools, and peripheral features.
The document discusses HPC solutions from HP including purpose-built HPC storage, servers, fabrics, and software infrastructure. It provides details on HP's ProLiant server families including the latest processor offerings, memory technologies, and storage options. Specific server models highlighted include the BL460c Gen8 blade server and SL250s Gen8 half-width tray server. The document also covers HP's Infiniband strategy and portfolio of FDR Infiniband switches, cables, and host channel adapters. Storage solutions mentioned include the HP X9000 network storage and Lustre parallel file systems.
This document summarizes Guillermo Talavera Velilla's PhD thesis defense presentation on optimizing address generation for low-power embedded VLIW processors. The presentation covered:
1) The goal of optimizing energy consumption during address generation for data access in VLIW processors for embedded systems.
2) How embedded systems demand both performance and energy efficiency.
3) Techniques like data transfer and storage exploration that optimize data locality and reduce storage requirements through code transformations.
4) How address calculation and control flow were bottlenecks identified after applying these transformations.
Computer organization & ARM microcontrollers module 3 PPTChetanNaikJECE
The document discusses concepts related to ARM microcontrollers including:
1. The RISC design philosophy aims to deliver simple but powerful instructions that execute in a single cycle at high speeds through placing more intelligence in software than hardware.
2. The ARM architecture uses a RISC design with a load-store architecture, large register set, separated pipelines, and fixed-length instructions.
3. Embedded systems using ARM processors include memory in a hierarchy with cache closer to the processor core and slower secondary memory further away. They also use different memory types like ROM, flash, and DRAM.
The document provides an introduction to the PIC16F877 microcontroller. It discusses that PICs are Harvard architecture microcontrollers made by Microchip with a RISC design. The PIC16F877 has an 8KB program memory, 368 bytes of data memory, and 256 bytes of EEPROM. It features ports, timers, ADC, and communication peripherals. Programming involves writing code, compiling to a hex file, and burning the file onto the PIC's flash memory using a programmer.
Similar to Blackfin optimization for performance (20)
Your application has been accepted for an online course offered through Malaviya National Institute of Technology Jaipur. The registration fee is 500 rupees for faculty/students and 1000 rupees for self-employed individuals. To register, you must log in, update your profile, select a course, confirm your registration, and share payment confirmation details with the provided email after paying.
This document provides information on choosing processors and development tools for embedded applications. It discusses different types of processors like microcontrollers, microprocessors, DSPs and FPGAs. It also covers topics like multicore processors, embedded software design flow, hardware design flow, processor selection criteria, embedded development life cycle and more. The goal is to help readers understand the various options available when selecting hardware and tools for their embedded projects.
This document provides an introduction to brain computer interfaces (BCI) and the Brainsense EEG headset. It discusses what a BCI is, the different types of BCI systems and sensors used, including invasive and non-invasive options. The document outlines the basic anatomy and functioning of the brain, how EEG signals are measured, and applications of BCI technology such as communication devices for disabled individuals, lie detection, gaming, health and neuroscience research. Finally, it provides an overview of the Brainsense headset, its specifications and capabilities, and examples of software that can be used with it.
The document discusses electric vehicle design using MATLAB. It outlines the key parts of an electric vehicle including the mechanical, electrical, and battery components. It also discusses benefits of electric vehicles like reduced emissions and operational costs. The document proposes using MATLAB modules to model the battery, motors, and mechanical parts for electric vehicle design. It provides examples of electric vehicles and their specifications.
This document discusses image processing and its applications. It provides an overview of libraries like OpenCV, SciPy, NumPy, Scikit-image and PIL that can be used for image processing tasks. It then describes some basic image processing operations like reading, showing, writing and filtering images. Finally, it lists various applications of image processing like object recognition, face recognition, medical imaging, agriculture and more. It concludes with an announcement about an upcoming demo session and question/answer session on the topic.
This document provides information about an event on using the Raspberry Pi for Internet of Things applications. It includes sections on the future of the Internet and IoT, what IoT is, applications of IoT like smart homes and connected cars, specifications of the Raspberry Pi, and a live demo session showing HTTP, MQTT, SMTP, UDP protocols and projects for weather monitoring and object recognition using Raspberry Pi and cloud services. The event is organized by Pantech Solutions and the Institute of Engineering & Technology in Alwar, Rajasthan.
This document discusses an event on Internet of Things using Arduino organized by Pantech Solutions and Dr. Shyama Prasad Mukherjee University. It provides information about the university and Pantech Solutions. The agenda includes topics on the Internet, Internet of Things, cloud computing, applications of IoT, and a live demo of an environment monitoring system using Arduino and ESP8266. It aims to gain knowledge on using these tools to develop IoT applications and systems.
The document summarizes a workshop on brain computer interface (BCI) organized by Pantech Solutions and the National Institute of Technology Karnataka. The workshop covered an overview of BCI, a live demo of a BCI system using an EEG headband to control a robot and applications through Arduino, and a video demo of using BCI with Matlab, Arduino and Raspberry Pi to control devices. The document provides details on the organizing institutions, BCI hardware and software used, and applications discussed.
This document provides an overview of brain-computer interfaces (BCI). It discusses electroencephalography (EEG) and how EEG measures brain electrical activity through electrodes. Different types of BCI devices and electrodes are described. The anatomy of the brain and functional mapping are outlined. Applications of BCI include prosthetic control, communication devices, operator monitoring, forensics, entertainment, health, neuromarketing, and neuroscience. The document also discusses Elon Musk's Neuralink company and its goal of creating brain chips to treat disorders. It concludes with a live demo of a BCI system using an EEG headband and a question/answer session.
This document provides information about a development deep learning architecture event organized by Pantech Solutions and The Institution of Electronics and Telecommunication. The event agenda includes general talks on AI, deep learning libraries, deep learning algorithms like ANN, RNN and CNN, and demonstrations of character recognition and emotion recognition. Details are provided about the organizers Pantech Solutions and IETE, as well as deep learning topics like neural networks, activation functions, common deep learning libraries, algorithms, applications, and the event agenda.
This document summarizes an event organized by Pantech Solutions and the Institution of Electronics and Telecommunication (IETE) on the future of artificial intelligence. The event featured several presentations and demos on topics related to AI, including computer vision with deep learning, natural language processing, machine and deep learning, AI applications in various domains like medical, agriculture, autonomous vehicles, and brain-computer interfaces. It also discussed topics like machine learning, deep learning, AI safety concerns, and examples of AI applications in areas like search engines, social media, e-commerce, music and more. The agenda included presentations on object recognition with YOLO, brain enhancement with BCI technology, and a Python AI demo.
The document discusses gate drive circuits for MOSFETs and IGBTs. It describes the structure and operation of MOSFETs, including turn-on and turn-off mechanisms. Gate driver properties like isolation, amplification, protection and speed enhancement are covered. Design considerations for gate drivers, inductors and PCB layout are provided. Sample applications and design calculations are included to illustrate the design process.
Brainsense is a single-channel, wireless EEG headset created by Pantech Prolabs India Pvt Ltd that monitors brain activity and translates it into meaningful data. It can be used to play cognitive games, measure meditation levels daily, test focus through real-time brain monitoring, research brain-computer interfaces, and read raw brainwaves. Brainsense works across various platforms and with popular brain training apps globally.
The document discusses median filtering for noise removal. Median filtering considers a 3x3 neighborhood around each pixel and replaces the pixel value with the median of that neighborhood. This helps reduce salt and pepper noise. Sample code in C is provided to implement median filtering on an image, taking the median of a 3x3 neighborhood around each pixel and replacing the pixel value. Examples are given of an original noisy image and the same image after median filtering for noise removal.
CCS is an IDE for developing applications on TI DSPs and MCUs. It allows creating and managing projects, compiling and building code, and debugging programs on both software simulators and hardware debuggers. The document discusses starting a new project in CCS, configuring build options, debugging tools like breakpoints and watch variables, and overview compiler sections and the linker configuration file.
This document discusses the generation of different types of waveforms using a TMS320C6745 DSP. It provides programs to generate sine waves, square waves, triangular waves, and sawtooth waves. For each waveform type, it gives the code to generate the waveform signal and output it to a specific memory location. It also notes the required plot settings to view each waveform type.
This document discusses interfacing a UART (Universal Asynchronous Receiver/Transmitter) with a TMS320C6745 digital signal processor (DSP). It provides an introduction to RS-232 standards and UARTs. It describes using a level converter like a MAX232 to convert voltage levels between TTL and RS-232. It shows a schematic for interfacing with a UART and describes UART registers. It provides examples of C code for transmitting and receiving data with a UART on a TMS320C6745 DSP.
The document discusses using GPIO pins on a TMS320C6745 processor to interface with LEDs and switches. It describes the GPIO peripheral features, how to connect an LED to the GPIO pins, the GPIO registers used to configure the pins as inputs or outputs and read/write values. It provides code to blink an LED by writing values to the output data register and read the state of switches by reading the input data register.
The document discusses using the GPIO peripheral on the TMS320C6745 chip to blink an LED by configuring the GPIO pins as outputs and toggling the output data register. It also describes reading the state of DIP switches using the GPIO input data register and displaying the value. The program examples show initializing the GPIO registers, setting up the direction and output values for blinking an LED, and reading the input register to display the DIP switch values.
This document outlines the agenda for a two-day workshop on the TMS320C6745 digital signal processor. Day 1 covers introductions to DSP architecture and the CCS development environment, as well as tutorials on waveform generation, UART interfaces, and image processing techniques. Day 2 focuses on additional image processing topics like discrete wavelet transforms and filters, as well as a valedictory session. The document provides context about the instructor and includes specifications about the TMS320C6745 processor.
GraphRAG for Life Science to increase LLM accuracyTomaz Bratanic
GraphRAG for life science domain, where you retriever information from biomedical knowledge graphs using LLMs to increase the accuracy and performance of generated answers
Introduction of Cybersecurity with OSS at Code Europe 2024Hiroshi SHIBATA
I develop the Ruby programming language, RubyGems, and Bundler, which are package managers for Ruby. Today, I will introduce how to enhance the security of your application using open-source software (OSS) examples from Ruby and RubyGems.
The first topic is CVE (Common Vulnerabilities and Exposures). I have published CVEs many times. But what exactly is a CVE? I'll provide a basic understanding of CVEs and explain how to detect and handle vulnerabilities in OSS.
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Blackfin optimization for performance
1. The World Leader in High Performance Signal Processing Solutions
Blackfin® Optimizations for
Performance and Power Consumption
Presented by:
Merril Weiner
Senior DSP Engineer
2. About This Module
This module describes the different ways to optimize the software
design to increase performance on the Blackfin processor and/or
reduce power consumption for low power applications.
• Example implementations for audio players and video players will
be used to explain the concepts in this module.
• Demo implementation of an audio and video player using these
concepts will be given at the end of this presentation, showing
the performance and power.
• It is recommended that viewers have seen the module Basics of
Building a Blackfin Application and have a working knowledge
of the Blackfin processor.
2 Blackfin Optimizations for Performance and Power Consumption
3. Module Outline
1. Overview
2. Optimizing Internal Memory Use
3. Optimizing External Memory Use
4. Power Modes
5. Demos
3 Blackfin Optimizations for Performance and Power Consumption
4. Overview
4 Blackfin Optimizations for Performance and Power Consumption
5. Strategies
Optimized Software Design = Increased Performance
= More Features or Lower Power Consumption
• Optimized software design means lower MIPS required, allowing
for additional features to be added or to reduce the frequency
(less dynamic power) and voltage (less static power).
• Optimized code is more than just turning on the optimization switch
on the compiler.
How can a system be further optimized?
• Optimize use of internal memory (L1 instruction and L1 data).
• Optimize use of external memory (L3-SDRAM).
• Effective use of power modes.
• Effective use of Blackfin and SDRAM settings.
5 Blackfin Optimizations for Performance and Power Consumption
6. More Features or Lower Power
Blackfin BF531 400 MHz Power
160.0
140.0
120.0
100.0
Power (mW)
80.0
Core Voltage (V)
60.0
0.8
40.0 0.85
0.95
20.0 1.045
1.14
0.0
0 50 100 150 200 250 300 350 400
MIPS
Blackfin BF531 Data Sheet Rev. D and Application Note EE-229
Note: Full on, typical at 25C
6 Blackfin Optimizations for Performance and Power Consumption
7. Software Example—Portable Media Player
Example implementation for the Blackfin family
of a low power portable media player
• Audio-only playback example
• Blackfin BF531
• Audio/video playback example
• Blackfin BF533
• These techniques are applicable across all
Blackfin processors
7 Blackfin Optimizations for Performance and Power Consumption
9. L1 Instruction SRAM vs. I-Cache
When algorithms exceed the BF531
16 kB of L1 I-cache, using I-cache
16 kB
may not be sufficient for optimal Cache or
16 kB
SRAM
SRAM
performance. In these cases,
use L1 instruction SRAM for
overlays. L1 Instruction 32 kB
• Audio decoders < 16 kB instruction BF533
• Video decoders > 16 kB instruction 16 kB
Cache or 64 kB SRAM
SRAM
Using L1 instruction SRAM vs.
L1 I-cache
• Cache-only model L1 Instruction 80 kB
• Turn on I-cache
• Overlay model
• Turn off I-cache
• Use all of L1 instruction as SRAM
• Hybrid model
• Turn on I-cache
• Use remaining L1 instruction as SRAM
9 Blackfin Optimizations for Performance and Power Consumption
10. L1 Instruction SRAM vs. I-Cache (cont.)
Using L1 instruction SRAM vs. L1 I-cache BF531
• Cache-only model 16 kB
16 kB
Cache or
• Only use L1 instruction for I-cache. SRAM
SRAM
• Pros
• Perfect for audio-only applications or where
L1 Instruction 32 kB
all critical modules have < 16 kB code.
• Works well with multiple critical modules.
• Ease of programming.
• Allows for buying a processor with less L1 instruction
(e.g., Blackfin BF531 instead of Blackfin BF533).
• Cons
• May have significantly worse performance when critical modules > 16 kB code.
• Summary
• Good for most cases, especially when critical modules have < 16 kB code space each.
• Only option for µClinux™.
10 Blackfin Optimizations for Performance and Power Consumption
11. L1 Instruction SRAM vs. I-Cache (cont.)
• Overlay model
BF533
• Only use L1 instruction for code overlay.
• Multiple overlays or single overlay. OS,
Drivers, Code Overlays
• Pros etc.
• Increased performance for code placed in
L1 instruction SRAM as code execution may
be delayed if it is not currently in the cache.
L1 Instruction 80 kB
• Cons
• Decreased performance for code that does not fit in
L1 instruction SRAM must be placed in L3.
• Issues
• If all critical code can fit in L1 instruction SRAM, do not use overlays but place code directly in L1
instruction SRAM.
• If multiple critical modules cannot all fit in L1 instruction SRAM, use code overlays and swap the modules
in as needed.
• Noncritical modules are not worth the context switch (swapping into L1 instruction SRAM) and must be
left in L3.
• Need to manage multiple overlays.
• PGO Linker tool available for help with sections and overlays.
• Summary
• Optimal if all critical modules fit in the code overlay space and there is very little or no code executing out
of L3.
11 Blackfin Optimizations for Performance and Power Consumption
12. L1 Instruction SRAM vs. I-Cache (cont.)
• Hybrid model BF533
• Use L1 instruction SRAM and I-cache.
16 kB OS,
• Place as much critical code as Cache etc.
Code Overlays
possible in L1 instruction SRAM overlays.
• Pros
• Excellent performance for critical modules
L1 Instruction 80 kB
placed in L1 instruction SRAM overlays.
• Very good performance for noncritical modules
that use I-cache.
• Cons
• Requires a processor with more than 32 kB of L1 instruction SRAM.
• Issues
• Same as overlay model.
• Summary
• Optimal performance for multiple critical modules > 16 kB and multiple noncritical modules
executing out of L3.
12 Blackfin Optimizations for Performance and Power Consumption
13. L1 Instruction SRAM vs. I-Cache (cont.)
• Video example BF533
• Use hybrid model, the best of both worlds.
8 kB
16 kB
• Memory map Cache
OS, 56 kB Code Overlays
etc.
• Turn on I-cache (16 kB of L1).
• Set aside L1 instruction SRAM for OS
and drivers (8 kB).
L1 Instruction 80 kB
• Remaining L1 instruction SRAM used for
code overlays (56 kB).
• Performance
• Cache-only model—20% performance degradation due to large critical
modules (> 64 kB code).
• Overlay model—10% performance degradation due to huge performance degradation of
noncritical modules (10–50x) executing out of L3.
• Hybrid model—best performance!
13 Blackfin Optimizations for Performance and Power Consumption
14. L1 Data SRAM vs. D-Cache
When data exceed 16 or 32 kB, using BF531
L1 D-cache may not be sufficient 16 kB
SRAM/
for optimal performance. L1 A
Cache
• Allocate memory for each type of data:
• Read-only data (r)—static variables (e.g., tables)
L1 Data 16 kB
• Read/write data (r/w)—state variables
• Temp data (temp)—temporary variables (e.g., internal buffers)
• Audio decoders < 16 kB data
• Video decoders > 32 kB data BF533
• Video post-processing > 32 kB data 16 kB
16 kB
L1 A SRAM/
SRAM
Cache
Using L1 data SRAM vs. L1 D-cache
L1 Data
• Cache-only model 64 kB
• Turn on D-cache 16 kB
16 kB
L1 B SRAM/
• Overlay model Cache
SRAM
• Turn off D-cache
• Use all L1 data as SRAM
• Hybrid model
• Turn on D-cache
• Use remaining L1 data as SRAM
14 Blackfin Optimizations for Performance and Power Consumption
15. L1 Data SRAM vs. D-Cache (cont.)
Using L1 data SRAM vs. L1 D-cache BF531
• Cache-only model 16 kB
L1 A
• Only use L1 data for D-cache. Cache
• Data placement
• All variables (r, r/w, temp) are placed in L3 and
L1 Data 16 kB
let D-cache do its job.
• Pros
• Perfect for audio-only applications or where each critical module uses < the data cache size.
• Works well with multiple critical modules.
• Ease of programming.
• Allows for buying a processor with less L1 data
(e.g., Blackfin BF531 instead of Blackfin BF533).
• Cons
• May have significantly worse performance when each critical module uses > the data
cache size.
• Summary
• Good for most cases, especially when each critical module uses < the data cache size.
• Only option for µClinux.
15 Blackfin Optimizations for Performance and Power Consumption
16. L1 Data SRAM vs. D-Cache (cont.)
• Overlay model
• L1 D-cache is turned off.
BF533
• Data placement:
• Place state variables (r/w) and static variables (r) OS, Temp/Data
L1 A
in L1 data SRAM overlays. etc. Overlay
• Place temp variables (temp) in L1 data SRAM.
L1 Data 64 kB
• Place concurrent buffers in separate 4 kB L1 data
SRAM banks.
• Multiple overlays or single overlay L1 B Temp/Data Overlay
• Pros
• Increased performance for modules that use
L1 data overlays.
• Cons
• Decreased performance for modules where data
must be accessed directly from L3.
16 Blackfin Optimizations for Performance and Power Consumption
17. L1 Data SRAM vs. D-Cache (cont.)
• Overlay model (cont.)
• Issues
BF533
• If all data can fit in L1 data SRAM, do not use overlays
but place data directly in L1 data SRAM. OS, Temp/Data
L1 A
• If multiple critical modules have a total data size > 64 kB etc. Overlay
and cannot fit in L1 data SRAM, use memory overlays
L1 Data 64 kB
to swap the modules’ data in and out as needed.
• Noncritical modules are not worth the context switch
(swapping data into L1 data SRAM) and must leave L1 B Temp/Data Overlay
the data in L3.
• Need to manage multiple overlays.
• PGO Linker tool available for help with sections
and overlays.
• Summary
• Optimal if the data for critical modules fits in the overlay
and if noncritical modules access very little or no L3 data.
17 Blackfin Optimizations for Performance and Power Consumption
18. L1 Data SRAM vs. D-Cache
• Hybrid model
BF533
• L1 D-cache is turned on in write back mode.
Temp/
• Use remaining L1 data for SRAM. 16 kB OS Data
L1 A
• Data Placement Cache etc. Over-
lay
• Place state variables (r/w) in L3 and let D-cache
do its job.
• Place static variables such as critical tables (r)
L1 Data
in L1 data SRAM overlays. 64 kB
• Place temp variables (temp) in L1 data SRAM.
• Place concurrent buffers in separate 4 kB L1 data
SRAM banks.
Temp/
• Pros 16 kB
L1 B Data
Cache Overlay
• Excellent performance for critical modules.
• Very good performance for noncritical modules that use
D-cache only.
• Cons
• Requires a processor with more than 32 kB of L1 data.
• Issues
• Same as overlay model.
• Summary
• Optimal performance for multiple critical modules that use
> 32 kB data and multiple noncritical modules.
18 Blackfin Optimizations for Performance and Power Consumption
19. L1 Data SRAM vs. D-Cache (cont.)
BF531
• Audio example
• Use cache model.
L1 A Cache
• Memory map
• All data is in L3 and D-cache does its job.
• Video example L1 Data 16 kB
• Requires Blackfin processors with 64 kB of L1 data.
• Use hybrid model, the best of both worlds.
• Memory map
BF533
• L1A—16 kB data cache, 8 kB OS and drivers, 8 kB
8 kB temp/overlay. 8 kB Temp/
16 kB
L1 A OS Data
Cache
• L1B—16 kB data cache, 16 kB temp/overlay. etc. Over-
lay
• Performance
• Cache-only model has ~100% system performance degradation.
L1 Data
• Overlay model is 7% better for critical modules, but 64 kB
noncritical modules are much worse for a net ~20% system
performance degradation.
16 kB
• Hybrid model—best performance! L1 B
16 kB Temp/
Cache Data
Overlay
19 Blackfin Optimizations for Performance and Power Consumption
20. Cache and DMAs
Data coherency—outgoing data
• Cache is not automatically flushed.
• Data coherency issue can exist if peripheral DMAs read from
SDRAM where the data is cached and not flushed.
• Cached buffers must either be flushed before starting a peripheral
DMA or be marked as non-cached in the CPLB tables.
Data coherency—incoming data
• Cached data is not automatically updated.
• Data coherency issue can exist if peripheral DMAs write to SDRAM
where the data is cached and not invalidated.
• Cached buffers must either be invalidated when peripheral DMA
updates data or mark data buffers as non-cached in the CPLB tables.
20 Blackfin Optimizations for Performance and Power Consumption
21. Memory Pipelining
MemDMA to bring data into L1 data SRAM
instead of using the D-cache
• Use temp data in L1 data SRAM for I/O buffers.
• Use memory DMAs to asynchronously transfer I/O data.
• Execute code while DMAs are active.
• Fetch next set of data, store last set of data while
working on the current set of data.
• “Pipelining” reduces MIPS by up to 50%.
Video example
• Video post-processing is memory bandwidth limited.
• While working on line n, fetch line n+1 and store line n-1.
• Pipelining reduces MIPS by up to ~40%.
21 Blackfin Optimizations for Performance and Power Consumption
22. L1 Data Scratchpad
L1 data scratchpad is 4 kB for all processors.
• Cannot be used for D-cache.
• Cannot be accessed with DMAs.
• Best use is stack.
For non-OS environments or single task solutions,
place stack in the scratchpad.
For RTOS solutions, each task must have its own stack.
• Place most critical tasks’ stacks or larger stacks in scratchpad.
• Place remaining stacks in L3, allowing for data cache to bring it into L1.
• Experiment.
Video example
• Use VisualDSP++ Kernel (VDK).
• Experimented with which stacks are placed in the
L1 scratchpad Saved ~20 MIPS.
22 Blackfin Optimizations for Performance and Power Consumption
24. Memory Settings
It is important to set memory priorities correctly.
• In most Blackfin processors, the peripheral DMAs can be set to have
higher priority than core access to L3 (instruction and data). This is
critical to avoid peripheral FIFO underruns/overruns.
• Some Blackfin processors allow for even greater control of
DMA priorities.
24 Blackfin Optimizations for Performance and Power Consumption
25. External Memory Banks
Each Blackfin supports at least 1 external memory
bank of SDRAM. 8MB
Bank 0
• Each external SDRAM banks consists of
8MB
4 sub-banks. Bank 1
BF533
• At any time, only 1 page is open in each of 8MB
Bank 2
the 4 sub-banks. 8MB
• Accesses to open pages improve performance. Bank 3
• Accesses to closed pages require closing an open page L3 SDRAM 32MB
and opening a new page (multiple SCLK latency).
• Random accesses to the same SDRAM sub-bank
more than a page-size apart reduce performance.
• Place concurrently accessed buffers in separate
SDRAM sub-banks whenever possible.
• For Mobile SDRAM sub-banks, unused banks can
be placed in self-refresh mode to save power.
25 Blackfin Optimizations for Performance and Power Consumption
26. External Memory Banks (cont.)
Audio example (Mobile SDRAM)
• Place all buffers in one bank.
• Place other banks in self-refresh to save on power.
Video example
• For video decoders/encoders
• Place two input reference frames in separate banks.
• Place output frame in one of the remaining banks.
• Place audio buffers in fourth bank.
• When banks are not set up correctly, performance degrades 100% due to page misses.
• Be careful when changing the physical SDRAM size
as the memory map across banks will change.
26 Blackfin Optimizations for Performance and Power Consumption
27. OS and Contiguous Memory
Some RTOS’s and µClinux require that the memory used by the OS be
a single contiguous block. With these OS’s, the bank of a data buffer
cannot be guaranteed. The following diagram shows how to use three
banks of SDRAM for data buffers while leaving over half of the memory
for the OS.
System Memory System Memory
Bank 0 Bank 0
Bank 1 Bank 1
Bank 2 Bank 2
Data Buffers
Data Buffers Bank 3 Bank 3
27 Blackfin Optimizations for Performance and Power Consumption
28. Power Modes
28 Blackfin Optimizations for Performance and Power Consumption
29. Hibernate and Sleep Modes
Hibernate mode
• Best power savings for non-real-time systems.
• This mode should be used for long idle periods when peripherals
are not used continuously.
• Core power and core clock are turned off.
• L1 memory and registers are not maintained.
• Consumes only ~50 uA of current by saving core static and dynamic power.
• Wake up on RTC or user input and takes ~600 us (300 us h/w + 300 us s/w).
Sleep mode
• Best power savings for real-time systems.
• This mode should be used within the RTOS or system idle routine for
shorter idle periods or when peripherals are used continuously.
• Core power is kept on, and core clock is turned off.
• Peripherals continue to run; L1 memory and all registers are maintained.
• Saves dynamic power.
• Wake up configurable on any interrupt and takes 10 CCLK cycles
(40 ns at 250 MHz, 185 ns at 54 MHz).
29 Blackfin Optimizations for Performance and Power Consumption
30. Hibernate and Sleep Modes (cont.)
Deep sleep mode
• Specific peripheral interrupts including the RTC can wake up the processor.
• Not as convenient as sleep mode and power consumption is not much.
30 Blackfin Optimizations for Performance and Power Consumption
31. Frequency and Voltage
In order to conserve power on the Blackfin, be aware of the different
tiers of speed and voltage. Here’s an example:
• <= 250 MHz 0.80 V
• <= 280 MHz 0.85 V
• <= 333 MHz 0.95 V
• <= 363 MHz 1.045 V
• <= 400 MHz 1.14 V
(refer to your processor datasheet)
The static current on a Blackfin is directly related to voltage
and temperature.
• To reduce static power, set the lowest voltage that allows for the necessary
MIPS for the current application.
The dynamic current on a Blackfin is directly related to clock cycles
per second.
• Set the frequency to the maximum speed allowed by the voltage level.
• Sleep when idle to reduce the dynamic power.
31 Blackfin Optimizations for Performance and Power Consumption
32. Frequency and Voltage Audio
Audio example (Blackfin BF531 400 MHz)
• Audio decode plus post-processing consumes 54 MIPS.
• Set voltage = 0.8 V, Core clock = 243 MHz.
• Sleep 78% of the time.
• Audio DMA frame completion interrupts wake-up processor.
• Consumes ~17 mW core (dynamic + static) at 25C.
Blackfin BF531 400 MHz Power
160.0
140.0
400 MIPS
1.14V
120.0 >150mW
Power (mW)
100.0
54 MIPS
1.14V
80.0 ~50mW
Core
60.0 Voltage (V)
0.8
40.0 0.85
250 MIPS
0.95
20.0 54 MIPS 0.8V 1.045
0.8V ~45mW
17mW 1.14
0.0
0 50 100 150 200 250 300 350 400
MIPS
32 Blackfin Optimizations for Performance and Power Consumption
33. Frequency and Voltage Video 1 QVGA
Video example 1 (Blackfin BF533 600 MHz)
• QVGA decode example consumes 183 MIPS.
• Set voltage = 0.8 V, Core clock = 243 MHz.
• Sleep 25% of the time.
• Consumes ~58 mW core (dynamic + static) at 25C.
600 MIPS
1.2 V
Blackfin BF533 600 MHz Power >320 mW
350.0
183 MIPS
300.0 1.2 V
~180 mW
Power (mW)
250.0
200.0
Core
Voltage (V)
150.0
0.8
0.85
100.0
0.95
50.0 1.045
1.2
0.0
0 50 100 150 200 250 300 350 400 450 500 550 600
183 MIPS
MIPS
250 MIPS
0.8 V 0.8 V
~58 mW ~70 mW
33 Blackfin Optimizations for Performance and Power Consumption
34. Frequency and Voltage Video 2
Video example 2 (Blackfin BF533 600 MHz)
• WQVGA (480 x 270) decode example with graphics consumes 303 MIPS.
• Set voltage = 0.85 V, Core clock = 351 MHz.
• Sleep 14% of the time.
• Consumes ~88 mW core (dynamic + static) at 25C.
600 MIPS
1.2 V
Blackfin BF533 600 MHz Power >320 mW
350.0 303 MIPS
1.2 V
~225 mW
300.0
Power (mW)
250.0
200.0 Core
Voltage (V)
150.0
0.8
0.85
100.0
0.95
303 MIPS 375 MIPS 1.045
50.0 0.85 V 0.85 V
~88 mW ~100 mW 1.2
0.0
0 50 100 150 200 250 300 350 400 450 500 550 600
MIPS
34 Blackfin Optimizations for Performance and Power Consumption
35. System Power and External Memory Speed
Reducing external memory speed reduces system power consumption.
• System performance degrades when memory accesses exceed half total
memory bandwidth.
• Calculate number of memory accesses per second in order to calculate
minimum memory bandwidth.
• Adjust system clock so that total memory bandwidth is twice necessary
memory accesses per second.
• May need to reduce the VCO to lower the system clock (SCLK) sufficiently
to save on external memory power consumption.
• Since modifying the VCO affects the CCLK, ensure that the CCLK is fast enough
to execute applications.
Audio example
• Memory accesses
= 96 kbps + 48 kHz samples x 4 bytes/sample x 4 (decode and output + post-proc)
= 0.4 million accesses per second
0.8 MHz minimum
• CCLK = 243 MHz, could set PLL_DIV to the max SCLK 8.1 MHz.
• To lower memory power consumption further, lower VCO to 54 MHz.
CCLK = 54 MHz and set SCLK to about 2.7 MHz.
35 Blackfin Optimizations for Performance and Power Consumption
36. System Power and External Memory Speed (cont.)
Balance reduction of memory speed against core performance for lowest
system power consumption.
• Slowing down memory speed can cause MIPS to increase.
• Make sure that MIPS does not exceed MHz.
• Balance power savings for memory against power loss for core.
• Optimize memory use.
• When pipelining code execution with DMA memory transfers, use DMA frame completion
interrupts and sleep while waiting for DMA to complete saving on dynamic power.
• If the interrupt overhead is too great, then polling is necessary. Slow down CCLK to reduce the
amount of time spent polling for DMAs to complete saving on dynamic power.
• Experiment.
36 Blackfin Optimizations for Performance and Power Consumption
37. System Power and External Memory Speed (cont.)
Video example
• QVGA decode at 500 kbps
• Memory accesses
= 500 kbps + 320 x 240 x 12 bpp x 3 ref frames x 30 fps (decode) + 320 x 240 x (12 bpp + 18 bpp) x
30 fps (post-proc) + 320 x 240 x 3 bpp x 60 fps (display)
= 17 million accesses per second
35 MHz minimum
• If VCO = CCLK = 243 MHz, then PLL_DIV = 0x0007 and SCLK = ~35 MHz
• Due to memory bandwidth limited nature of some modules, SCLK = 35 MHz as
opposed to SCLK > 100 MHz will cause DMAs to take 3x as long and MIPS will
increase 200%!
• Due to a high number of interrupts, more efficient to poll for interrupts to complete.
• Setting PLL_DIV = 0x4 is optimum for core dynamic power while PLL_DIV = 0x7
is optimum for memory power consumption. Best solution is PLL_DIV = 0x5
(default value).
• Reduce CCLK: Set VCO = CCLK = 216 MHz, PLL_DIV = 0x5 SCLK = 43.2 MHz
• Experiment
37 Blackfin Optimizations for Performance and Power Consumption
38. External Memory Banks for Mobile SDRAM
Memory power consumption is directly related to the number of
active banks.
• For example, with 1.8 V Mobile SDRAM, one bank consumes ~1 mW
in self-refresh mode as opposed to ~20 mW in active mode.
• Place as many banks in self-refresh as possible for the task at hand.
• Balance power consumed by MIPS against power consumed by
memory banks.
• 1 bank = ~20 mW = ~85 MIPS (for 0.8–0.85 V)
• If reducing by one bank causes a performance degradation < 85 MIPS,
place the bank in self-refresh.
• Blackfin processors allow one, two, or four active banks.
• May place two or three banks in self-refresh for power savings.
38 Blackfin Optimizations for Performance and Power Consumption
39. External Memory Banks for Mobile SDRAM (cont.)
Audio example
• Audio decode + audio post-processing example = 54 MIPS with one bank
• Keep one bank active and place three banks in self-refresh for a net savings
of ~60 mW system wide!
Video example
• QVGA video example = 183 MIPS with four banks
• Video solution with 3 banks suffers 22 MIPS degradation < 85 MIPS. Definitely
worth it!
• Video solution with 2 banks suffers 212 MIPS degradation > 170 MIPS.
Not worth it.
• Keeping three banks active is not an option, and keeping only two banks
active is not worth it.
• Keep all four banks active.
39 Blackfin Optimizations for Performance and Power Consumption
40. Conclusion
To fully optimize your system for increased performance and/or reduced
power consumption, it requires a diligent look at:
• Voltage and frequency settings
• L1 settings and use
• L3 settings and use
• Power modes
• Experiment
Blackfin processor architecture is filled with many ways to increase
performance beyond initial expectations.
40 Blackfin Optimizations for Performance and Power Consumption
41. For Additional Information
Analog Devices website which has links to white papers, manuals, data
sheets, FAQs, Knowledge Base, sample code, development tools and
much more:
• www.analog.com/blackfin
For specific questions click on the “Ask a question” button.
41 Blackfin Optimizations for Performance and Power Consumption
42. Demos
42 Blackfin Optimizations for Performance and Power Consumption
43. Demos
Example implementation for the Blackfin family of a low power
portable media player
• BF533 EZ-KIT Lite®
Audio only example
• AAC-LC audio decode
• Audio sample rate converter
• 54 MHz, 0.8 V, ~39 mW (~17 mW = BF531) core power for audio-only playback
Audio/Video example
• QVGA MPG4 ASP
• Video post-processing with alpha graphics blending
• AAC-LC audio decode
• Audio sample rate converter
• 243 MHz, 0.8 V, ~70 mW core power for audio/video playback
This software was created for demonstration purposes only and is not available for distribution.
43 Blackfin Optimizations for Performance and Power Consumption