This document provides information about semiconductor materials and semiconductor devices. It discusses: 1. Semiconductors like silicon have electrical properties between conductors and insulators, with few free electrons. Doping semiconductors by adding impurity atoms can produce more free electrons or holes. 2. A PN junction diode is formed by joining a p-type and n-type semiconductor. It allows current to pass easily in one direction but blocks it in the other direction. 3. A transistor is a three-terminal semiconductor device that can amplify or switch electronic signals. Bipolar junction transistors (BJTs) have three terminals - base, collector, and emitter - and come in NPN

1. Agricultural Engineering College & Research Institute
B.Tech. (Agricultural Engineering)
BAE 207-Applied Electronics and Instrumentation (2+1)
II Year / IV Semester-2017 Batch
Study Material
Prepared By:
Er.K.Balaji (P&FE)

2. Lecture-1
Semiconductor materials such as silicon (Si), germanium (Ge) and gallium arsenide (GaAs),
have electrical properties somewhere in the middle, between those of a “conductor” and an
“insulator”. They are not good conductors nor good insulators (hence their name “semi”-
conductors). They have very few “free electrons” because their atoms are closely grouped
together in a crystalline pattern called a “crystal lattice” but electrons are still able to flow, but
only under special conditions.
The ability of semiconductors to conduct electricity can be greatly improved by replacing or
adding certain donor or acceptor atoms to this crystalline structure thereby, producing more free
electrons than holes or vice versa.
The process of adding donor or acceptor atoms to semiconductor atoms (the order of 1 impurity
atom per 10 million (or more) atoms of the semiconductor) is called Doping. Thus doped silicon
is no longer pure. These donor and acceptor atoms are collectively referred to as “impurities”,
and by doping a silicon material with sufficient numbers of impurities, we can turn it into either
an N-type or a P-type semiconductor material.
Antimony (symbol Sb) as well as Phosphorus (symbol P), are frequently used as a pentavalent
additive to silicon for N-type region.
Boron (B) or aluminium (Al), having three valence electrons, can be used. The
latter elements are also called trivalent impurities for P-type region.
A PN-junction diode is formed when a p-type semiconductor is fused to an n-type semiconductor
creating a potential barrier voltage across the diode junction.
A PN Junction Diode is one of the simplest semiconductor devices around, and which has the
characteristic of passing current in only one direction only. However, unlike a resistor, a diode
does not behave linearly with respect to the applied voltage as the diode has an exponential
current-voltage ( I-V ) relationship and therefore we cannot described its operation by simply
using an equation such as Ohm’s law.
There are two operating regions and three possible “biasing” conditions for the
standard Junction Diode and these are:
 1. Zero Bias – No external voltage potential is applied to the PN junction diode.

3.  2. Reverse Bias – The voltage potential is connected negative, (-ve) to the P-type material
and positive, (+ve) to the N-type material across the diode which has the effect
of Increasing the PN junction diode’s width.
 3. Forward Bias – The voltage potential is connected positive, (+ve) to the P-type material
and negative, (-ve) to the N-type material across the diode which has the effect
of Decreasing the PN junction diodes width.
Zero Biased Junction Diode
 When a diode is connected in a Zero Bias condition, no external potential energy is
applied to the PN junction. However if the diodes terminals are shorted together, a few
holes (majority carriers) in the P-type material with enough energy to overcome the
potential barrier will move across the junction against this barrier potential. This is
known as the “Forward Current” and is referenced as IF
Forward Bias:
If a suitable positive voltage (forward bias) is applied between the two ends of the PN junction, it
can supply free electrons and holes with the extra energy they require to cross the junction as the
width of the depletion layer around the PN junction is decreased.
Reverse Bias:
By applying a negative voltage (reverse bias) results in the free charges being pulled away from
the junction resulting in the depletion layer width being increased. This has the effect of
increasing or decreasing the effective resistance of the junction itself allowing or blocking
current flow through the diode.

4. Junction Diode Symbol and Static I-V Characteristics

5. The point at which this sudden increase in current takes place is represented on the static I-V
characteristics curve above as the “knee” point.
Sometimes this avalanche effect has practical applications in voltage stabilising circuits where a
series limiting resistor is used with the diode to limit this reverse breakdown current to a preset
maximum value thereby producing a fixed voltage output across the diode.
Half Wave Rectification
A rectifier is a circuit which converts the Alternating Current (AC) input power into a Direct
Current (DC) output power. The input power supply may be either a single-phase or a multi-
phase supply with the simplest of all the rectifier circuits being that of the Half Wave Rectifier.
The power diode in a half wave rectifier circuit passes just one half of each complete sine wave
of the AC supply in order to convert it into a DC supply. Then this type of circuit is called a
“half-wave” rectifier because it passes only half of the incoming AC power supply as shown
below.
Half Wave Rectifier Circuit
During each “positive” half cycle of the AC sine wave, the diode is forward biased as the anode
is positive with respect to the cathode resulting in current flowing through the diode.
Since the DC load is resistive (resistor, R), the current flowing in the load resistor is therefore
proportional to the voltage (Ohm´s Law), and the voltage across the load resistor will therefore
be the same as the supply voltage, VS (minus Vƒ), that is the “DC” voltage across the load is
sinusoidal for the first half cycle only so VOUT = VS.

6. During each “negative” half cycle of the AC sinusoidal input waveform, the diode is reverse
biased as the anode is negative with respect to the cathode. Therefore, NO current flows through
the diode or circuit. Then in the negative half cycle of the supply, no current flows in the load
resistor as no voltage appears across it so therefore, Vout = 0.
The variation of the rectified output waveform between this “ON” and “OFF” condition
produces a waveform which has large amounts of “ripple” which is an undesirable feature. The
resultant DC ripple has a frequency that is equal to that of the AC supply frequency.
Very often when rectifying an alternating voltage we wish to produce a “steady” and continuous
DC voltage free from any voltage variations or ripple. One way of doing this is to connect a large
value Capacitor across the output voltage terminals in parallel with the load resistor as shown
below. This type of capacitor is known commonly as a “Reservoir” or Smoothing Capacitor.

7. Half-wave Rectifier with Smoothing Capacitor
When rectification is used to provide a direct voltage (DC) power supply from an alternating
(AC) source, the amount of ripple voltage can be further reduced by using larger value capacitors
but there are limits both on cost and size to the types of smoothing capacitors used.
Full Wave Rectifier Circuit
The full wave rectifier circuit consists of two power diodes connected to a single load resistance
(RL) with each diode taking it in turn to supply current to the load. When point A of the

8. transformer is positive with respect to point C, diode D1 conducts in the forward direction as
indicated by the arrows.
When point B is positive (in the negative half of the cycle) with respect to point C,
diode D2 conducts in the forward direction and the current flowing through resistor R is in the
same direction for both half-cycles. As the output voltage across the resistor R is the phasor sum
of the two waveforms combined, this type of full wave rectifier circuit is also known as a “bi-
phase” circuit.
The Diode Bridge Rectifier
The four diodes labelled D1 to D4 are arranged in “series pairs” with only two diodes conducting
current during each half cycle. During the positive half cycle of the supply,
diodes D1 and D2 conduct in series while diodes D3 and D4 are reverse biased and the current
flows through the load as shown below.
The Positive Half-cycle

9. During the negative half cycle of the supply, diodes D3 and D4 conduct in series, but
diodes D1 and D2 switch “OFF” as they are now reverse biased. The current flowing through the
load is the same direction as before.
The Negative Half-cycle
As the current flowing through the load is unidirectional, so the voltage developed across the
load is also unidirectional the same as for the previous two diode full-wave rectifier, therefore
the average DC voltage across the load is 0.637Vmax.
Typical Bridge Rectifier
However in reality, during each half cycle the current flows through two diodes instead of just
one so the amplitude of the output voltage is two voltage drops ( 2*0.7 = 1.4V ) less than the

10. input VMAX amplitude. The ripple frequency is now twice the supply frequency (e.g. 100Hz for a
50Hz supply or 120Hz for a 60Hz supply.)
Although we can use four individual power diodes to make a full wave bridge rectifier, pre-made
bridge rectifier components are available “off-the-shelf” in a range of different voltage and
current sizes that can be soldered directly into a PCB circuit board or be connected by spade
connectors.
The image to the right shows a typical single phase bridge rectifier with one corner cut off. This
cut-off corner indicates that the terminal nearest to the corner is the positive or +veoutput
terminal or lead with the opposite (diagonal) lead being the negative or -ve output lead. The
other two connecting leads are for the input alternating voltage from a transformer secondary
winding.
The Smoothing Capacitor
We saw in the previous section that the single phase half-wave rectifier produces an output wave
every half cycle and that it was not practical to use this type of circuit to produce a steady DC
supply. The full-wave bridge rectifier however, gives us a greater mean DC value (0.637 Vmax)
with less superimposed ripple while the output waveform is twice that of the frequency of the
input supply frequency.
We can improve the average DC output of the rectifier while at the same time reducing the AC
variation of the rectified output by using smoothing capacitors to filter the output waveform.
Smoothing or reservoir capacitors connected in parallel with the load across the output of the full

11. wave bridge rectifier circuit increases the average DC output level even higher as the capacitor
acts like a storage device as shown below.
Lecture 3:
Transistor:
Transistor is a semiconductor device used to amplify or switch electronic signals and
electrical power. It is composed of semiconductor material usually with at least three
terminals for connection to an external circuit.
A transistor performs the same function as a vacuum tube triode, but using semiconductor
junctions instead of heated electrodes in a vacuum chamber. It is the fundamental building
block of modern electronic devices and found everywhere in modern electronic systems.
Transistor Basics:
A transistor is a three terminal device. Namely,
Base: This is responsible for activating the transistor.
Collector: This is the positive lead.
Emitter: This is the negative lead.
Types:
1.UJT
2.BJT
3.FET
Bipolar Junction Transistor:
If we now join together two individual signal diodes back-to-back, this will give us two PN-
junctions connected together in series that share a common P or N terminal. The fusion of these
two diodes produces a three layer, two junction, three terminal device forming the basis of
a Bipolar Junction Transistor, or BJT for short.
Then bipolar transistors have the ability to operate within three different regions:
• Active Region – the transistor operates as an amplifier and Ic = β*Ib
• Saturation – the transistor is “Fully-ON” operating as a switch and Ic = I(saturation)
• Cut-off – the transistor is “Fully-OFF” operating as a switch and Ic = 0

12. What are the terminals in BJT?
• The Bipolar Transistor basic construction consists of two PN-junctions producing three
connecting terminals with each terminal being given a name to identify it from the other
two. These three terminals are known and labelled as the Emitter ( E ), the Base ( B ) and
the Collector ( C ) respectively.
How BJT can act as a switch?
• Bipolar Transistors are current regulating devices that control the amount of current
flowing through them from the Emitter to the Collector terminals in proportion to the
amount of biasing voltage applied to their base terminal, thus acting like a current-
controlled switch. As a small current flowing into the base terminal controls a much
larger collector current forming the basis of transistor action.
• The principle of operation of the two transistor types PNP and NPN, is exactly the same
the only difference being in their biasing and the polarity of the power supply for each
type.
Construction Of PNP and NPN Transistor:
The construction and circuit symbols for both the PNP and NPN bipolar transistor are given
above with the arrow in the circuit symbol always showing the direction of “conventional
current flow” between the base terminal and its emitter terminal. The direction of the arrow
always points from the positive P-type region to the negative N-type region for both
transistor types, exactly the same as for the standard diode symbol.

13. Operating Point in Transistor
Definition: The point which is obtained from the values of the IC (collector current) or
VCE (collector-emitter voltage) when no signal is given to the input is known as the operating
point or Q-point in a transistor. It is called operating point because variations of IC (collector
current) and VCE (collector-emitter voltage) takes place around this point when no signal is
applied to the input.
The operating point is also called quiescent (silent) point or simply Q-point because it is a point
on IC – VCE characteristic when the transistor is silentor no input signal is applied to the circuit.
The operating point can be easily obtained by the DC load line method. The DC load line is
explained below.

14. Let, determines the operating point of particular base circuit current IB. According to the load
line condition, the OA = VCE = VCC and OB = IC = VCC/RCis shown on the output characteristic
curve above. The point Q is the operating point where the DC load line intersects the base
current IB at the output characteristic curves in the absence of input signal.
Where IC= OD mA
VCE = OC volts.
The position of the Q-point depends on the applications of the transistor. If the transistor is used
as a switch then for open switch the Q-point is in the cutoff region, and for the close switch, the
Q-point is in the saturation region. The Q-point lies in the middle of the line for the transistor
which operates as an amplifier.
Lecture 4 :
We know that generally the transistor has three terminals – emitter (E), base (B) and collector.
But in the circuit connections we need four terminals, two terminals for input and another two
terminals for output. To overcome these problems we use one terminal as common for both input
and output actions. Using this property we construct the circuits and these structures are called
transistor configurations. Generally the transistor configurations are three types they are common
base (CB) configuration, common collector (CC) configuration and common emitter (CE)
configuration. The behavior of these three configurations with respect to gain is given below.
 Common Base (CB) Configuration: no current gain but voltage gain
 Common Collector (CC) Configuration: current gain but no voltage gain
 Common Emitter (CE) Configuration: current gain and voltage gain

15. Common Base Configuration
In this configuration we use base as common terminal for both input and output signals. The
configuration name itself indicates the common terminal. Here the input is applied between the
base and emitter terminals and the corresponding output signal is taken between the base and
collector terminals with the base terminal grounded. Here the input parameters are VEB and
IE and the output parameters are VCB and IC. The input current flowing into the emitter terminal
must be higher than the base current and collector current to operate the transistor, therefore the
output collector current is less than the input emitter current.
The current gain is generally equal or less than to unity for this type of configuration. The input
and output signals are in-phase in this configuration. The amplifier circuit configuration of this
type is called as non-inverting amplifier circuit. The construction of this configuration circuit is
difficult because this type has high voltage gain values.
The input characteristics of this configuration are looks like characteristics of illuminated photo
diode while the output characteristics represents a forward biased diode. This transistor
configuration has high output impedance and low input impedance. This type of configuration
has high resistance gain i.e. ratio of output resistance to input resistance is high. The voltage gain
for this configuration of circuit is given below.
AV = Vout/Vin = (IC*RL) / (IE*Rin)
Current gain in common base configuration is given as
α = Output current/Input current
α = IC/IE

16. The common base circuit is mainly used in single stage amplifier circuits, such as microphone
pre amplifier or radio frequency amplifiers because of their high frequency response. The
common base transistor circuit is given below.
Input Characteristics
Input characteristics are obtained between input current and input voltage with constant output
voltage. First keep the output voltage VCB constant and vary the input voltage VEB for different
points then at each point record the input current IE value. Repeat the same process at different
output voltage levels. Now with these values we need to plot the graph between IEand
VEB parameters. The below figure show the input characteristics of common base configuration.
The equation to calculate the input resistance Rin value is given below.
Rin = VEB / IE (when VCB is constant)

17. Output Characteristics
The output characteristics of common base configuration are obtained between output current
and output voltage with constant input current. First keep the emitter current constant and vary
the VCB value for different points, now record the IC values at each point. Repeat the same
process at different IE values. Finally we need to draw the plot between VCB and IC at constant
IE. The below figure show the output characteristics of common base configuration. The equation
to calculate the output resistance value is given below.
Rout = VCB / IC (when IE is constant)
Common Collector Configuration

18. In this configuration we use collector terminal as common for both input and output signals. This
configuration is also known as emitter follower configuration because the emitter voltage follows
the base voltage. This configuration is mostly used as a buffer. These configurations are widely
used in impedance matching applications because of their high input impedance.
In this configuration the input signal is applied between the base-collector region and the output
is taken from the emitter-collector region. Here the input parameters are VBC and IB and the
output parameters are VEC and IE. The common collector configuration has high input
impedance and low output impedance. The input and output signals are in phase. Here also the
emitter current is equal to the sum of collector current and the base current. Now let us calculate
the current gain for this configuration.
Current gain,
Ai = output current/Input current
Ai = IE/IB
Ai = (IC + IB)/IB
Ai = (IC/IB) + 1
Ai = β + 1

19. The common collector transistor circuit is shown above. This common collector configuration is
a non inverting amplifier circuit. The voltage gain for this circuit is less than unity but it has
large current gain because the load resistor in this circuit receives both the collector and base
currents.
Input Characteristics
The input characteristics of a common collector configuration are quite different from the
common base and common emitter configurations because the input voltage VBC is largely
determined by VEC level. Here,
VEC = VEB + VBC
VEB = VEC – VBC
The input characteristics of a common-collector configuration are obtained between inputs
current IB and the input voltage VCB at constant output voltage VEC. Keep the output voltage
VEC constant at different levels and vary the input voltage VBC for different points and record the
IB values for each point. Now using these values we need to draw a graph between the
parameters of VBC and IB at constant VEC.
Output Characteristics
The operation of the common collector circuit is same as that of common emitter circuit. The
output characteristics of a common collector circuit are obtained between the output voltage
VEC and output current IE at constant input current IB. In the operation of common collector
circuit if the base current is zero then the emitter current also becomes zero. As a result no
current flows through the transistor

20. If the base current increases then the transistor operates in active region and finally reaches to
saturation region. To plot the graph first we keep the IB at constant value and we will vary the
VEC value for various points, now we need to record the value of IE for each point. Repeat the
same process for different IB values. Now using these values we need to plot the graph between
the parameters of IE and VCE at constant values of IB. The below figure show the output
characteristics of common collector.
Common Emitter Configuration
In this configuration we use emitter as common terminal for both input and output. This common
emitter configuration is an inverting amplifier circuit. Here the input is applied between base-
emitter region and the output is taken between collector and emitter terminals. In this
configuration the input parameters are VBE and IB and the output parameters are VCEand IC.
This type of configuration is mostly used in the applications of transistor based amplifiers. In this
configuration the emitter current is equal to the sum of small base current and the large collector
current. i.e. IE = IC + IB. We know that the ratio between collector current and emitter current
gives current gain alpha in Common Base configuration similarly the ratio between collector
current and base current gives the current gain beta in common emitter configuration.

21. Now let us see the relationship between these two current gains.
Current gain (α) = IC/IE
Current gain (β) = IC/IB
Collector current IC =α IE = βIB
This configuration is mostly used one among all the three configurations. It has medium input
and output impedance values. It also has the medium current and voltage gains. But the output
signal has a phase shift of 1800 i.e. both the input and output are inverse to each other.
Input Characteristics
The input characteristics of common emitter configuration are obtained between input current
IB and input voltage VBE with constant output voltage VCE. Keep the output voltage VCEconstant
and vary the input voltage VBE for different points, now record the values of input current at each
point. Now using these values we need to draw a graph between the values of IB and VBE at
constant VCE. The equation to calculate the input resistance Rin is given below.

22. Rin = VBE/IB (when VCE is at constant)
Output Characteristics
The output characteristics of common emitter configuration are obtained between the output
current IC and output voltage VCE with constant input current IB. Keep the base current IBconstant
and vary the value of output voltage VCE for different points, now note down the value of
collector IC for each point. Plot the graph between the parameters IC and VCE in order to get the
output characteristics of common emitter configuration. The equation to calculate the output
resistance from this graph is given below.
Rout = VCE/IC (when IB is at constant)

23. Lecture 5:
Classification of Amplifiers:
Amplifier classes are mainly lumped into two basic groups. The first are the classically
controlled conduction angle amplifiers forming the more common amplifier classes of A, B,
AB and C, which are defined by the length of their conduction state over some portion of the
output waveform, such that the output stage transistor operation lies somewhere between being
“fully-ON” and “fully-OFF”.
Lecture 5:
Class A Amplifier
Common emitter amplifiers are the most commonly used type of amplifier as they can have a
very large voltage gain.
The transistor is always biased “ON” so that it conducts during one complete cycle of the input
signal waveform producing minimum distortion and maximum amplitude of the output signal.
This means then that the Class A Amplifier configuration is the ideal operating mode, because
there can be no crossover or switch-off distortion to the output waveform even during the
negative half of the cycle. Class A power amplifier output stages may use a single power
transistor or pairs of transistors connected together to share the high load current. Consider
the Class A amplifier circuit below.

24. Single Stage Amplifier Circuit
This is the simplest type of Class A power amplifier circuit. It uses a single-ended transistor for
its output stage with the resistive load connected directly to the Collector terminal. When the
transistor switches “ON” it sinks the output current through the Collector resulting in an
inevitable voltage drop across the Emitter resistance thereby limiting the negative output
capability.
The efficiency of this type of circuit is very low (less than 30%) and delivers small power
outputs for a large drain on the DC power supply. A Class A amplifier stage passes the same
load current even when no input signal is applied so large heatsinks are needed for the output
transistors.
Darlington Transistor.
These types of devices are basically two transistors within a single package, one small “pilot”
transistor and another larger “switching” transistor. The big advantage of these devices are that
the input impedance is suitably large while the output impedance is relatively low, thereby
reducing the power loss and therefore the heat within the switching device.

25. The overall current gain Beta (β) or hfe value of a Darlington device is the product of the two
individual gains of the transistors multiplied together and very high β values along with high
Collector currents are possible compared to a single transistor circuit.
To improve the full power efficiency of the Class A amplifier it is possible to design the circuit
with a transformer connected directly in the Collector circuit to form a circuit called
a Transformer Coupled Amplifier. The transformer improves the efficiency of the amplifier by
matching the impedance of the load with that of the amplifiers output using the turns ratio ( n ) of
the transformer and an example of this is given below.
The r.m.s. Collector voltage is given as:

26. The r.m.s. Collector current is given as:
The r.m.s. Power delivered to the load (Pac) is therefore given as:
Class B Amplifier
Class-B Amplifiers use two or more transistors biased in such a way so that each transistor only
conducts during one half cycle of the input waveform

27. To improve the full power efficiency of the previous Class A amplifier by reducing the wasted
power in the form of heat, it is possible to design the power amplifier circuit with two transistors
in its output stage producing what is commonly termed as a Class B Amplifier also known as
a push-pull amplifier configuration.
Push-pull amplifiers use two “complementary” or matching transistors, one being an NPN-type
and the other being a PNP-type with both power transistors receiving the same input signal
together that is equal in magnitude, but in opposite phase to each other. This results in one
transistor only amplifying one half or 180o of the input waveform cycle while the other transistor
amplifies the other half or remaining 180o of the input waveform cycle with the resulting “two-
halves” being put back together again at the output terminal.
Then the conduction angle for this type of amplifier circuit is only 180o or 50% of the input
signal. This pushing and pulling effect of the alternating half cycles by the transistors gives this
type of circuit its amusing “push-pull” name, but are more generally known as the Class B
Amplifier as shown below.
The circuit above shows a standard Class B Amplifier circuit that uses a balanced center-tapped
input transformer, which splits the incoming waveform signal into two equal halves and which
are 180o out of phase with each other. Another center-tapped transformer on the output is used to
recombined the two signals providing the increased power to the load. The transistors used for
this type of transformer push-pull amplifier circuit are both NPN transistors with their emitter
terminals connected together.
Here, the load current is shared between the two power transistor devices as it decreases in one
device and increases in the other throughout the signal cycle reducing the output voltage and
current to zero. The result is that both halves of the output waveform now swings from zero to

28. twice the quiescent current thereby reducing dissipation. This has the effect of almost doubling
the efficiency of the amplifier to around 70%.
Assuming that no input signal is present, then each transistor carries the normal quiescent
collector current, the value of which is determined by the base bias which is at the cut-off point.
If the transformer is accurately center tapped, then the two collector currents will flow in
opposite directions (ideal condition) and there will be no magnetization of the transformer core,
thus minimizing the possibility of distortion.
When an input signal is present across the secondary of the driver transformer T1, the transistor
base inputs are in “anti-phase” to each other as shown, thus if TR1 base goes positive driving the
transistor into heavy conduction, its collector current will increase but at the same time the base
current of TR2 will go negative further into cut-off and the collector current of this transistor
decreases by an equal amount and vice versa. Hence negative halves are amplified by one
transistor and positive halves by the other transistor giving this push-pull effect.
Unlike the DC condition, these alternating currents are ADDITIVE resulting in the two output
half-cycles being combined to reform the sine-wave in the output transformers primary winding
which then appears across the load.
Class B Amplifier operation has zero DC bias as the transistors are biased at the cut-off, so each
transistor only conducts when the input signal is greater than the Base-emittervoltage. Therefore,
at zero input there is zero output and no power is being consumed. This then means that the
actual Q-point of a Class B amplifier is on the Vce part of the load line as shown below.
Class B Output Characteristics Curves

29. The Class B Amplifier has the big advantage over their Class A amplifier cousins in that no
current flows through the transistors when they are in their quiescent state (ie, with no input
signal), therefore no power is dissipated in the output transistors or transformer when there is no
signal present unlike Class A amplifier stages that require significant base bias thereby
dissipating lots of heat – even with no input signal present.
So the overall conversion efficiency ( η ) of the amplifier is greater than that of the equivalent
Class A with efficiencies reaching as high as 70% possible resulting in nearly all modern types
of push-pull amplifiers operated in this Class B mode.
Working Principle of Class C Amplifier
Fig. 4 – Circuit Diagram of Class C Power Amplifier
As shown in the above circuit diagram, Resistor Rb connects to the transistor Q1 base. A biasing
resistor which connects to the base of Q1 try to pulls the base of transistor further downwards
and set the operating pointer dc bias point below the cut-off point (In cutoff the collector current
is ICO which will be of micro amperes order and hence can be assumed to be zero) in the DC load
line. The dc load line is the locus of IC and VCE at which BJT remains in active region.
The reason for the major portion of the input signal is absent in the output signal is that the
transistor will start conducting only after the input signal amplitude has risen above the base
emitter voltage (Vbe~0.7V) and according to the result the downward bias voltage caused by Rb.
As shown in Figure 4, inductor L1 and capacitor C1 forms a tuned circuit which is also called a
tank circuit. LC circuits are used either for generating signals at a particular frequency, or
picking out a signal at a particular frequency from a more complex signal which extract the
required signal from the pulsed output of the transistor.
A series of current pulses is produced by the transistor (active element) according to the input
which flow through the resonant circuit. The tank circuit oscillates in the frequency of the input
signal by selecting the proper value of L and C. All other frequencies are attenuated by tank
circuit and the tank circuit oscillates in one frequency.

30. The required frequency is obtained by using a suitably tuned load. The output signal noise can be
eliminated by using additional filters. For transferring the power to the load from the tank circuit,
a coupling transformer is used.
Fig. – Characteristics of Class C Amplifier
As shown in Figure , it can be observed that the operating point is placed some way below the
cut-off point in the DC load-line and so only a fraction of the input waveform is available at the
output.
Applications of Class C Amplifier
Class C Amplifier is used in: –
 RF oscillators.
 RF amplifier.
 FM transmitters.
 Booster amplifiers.
 High frequency repeaters.
 Tuned amplifiers etc.
Advantages of Class C Amplifier
The advantages of Class C Amplifier are as follows: –
 Higher efficiency.
 Best result in RF applications.
 Physical size is suitable for given power

31. Disadvantages of Class C Amplifier
The disadvantages of Class C Amplifier are as follows: –
 Poor linearity.
 Not suitable for audio applications.
 Lot of noise and RF interference.
 To obtain ideal inductors and coupling transformers it is very difficult.
 Not good dynamic range.
Lecture 6:
JFET Construction and Operation
A schematic representation of an n channel JFET is shown in Figure. An n-type channel is
formed between two p-type layers which are connected to the gate. Majority carrier electrons
flow from the source and exit the drain, forming the drain current. The pn junction is reverse
biased during normal operation, and this widens the depletion layers which extend into
the n channel only (since the doping of the p regions is much larger than that of the n channel).
As the depletion layers widen, the channel narrows, restricting current flow.
Figure: n-channel JFET structure.

32. When , there is little voltage drop along the length of the channel, and the
depletion regions are parallel, Figure 119. As vGS is increased negatively, they eventually touch
reducing iD to zero. The value of vGS at which this occurs is called the pinch-off
voltage, Vp (or vGS(off)).
Figure: n-channel JFET structure for showing parallel depletion
regions.
When , there is a voltage drop along the length of the channel, and the
depletion regions are no longer parallel, but are closer together towards the drain, Figure 120.

33. As vDS is increased, they will touch (pinch-off) towards the drain, and the drain current iD can
increase no longer. At the threshold of pinch-off, vGS-vDS=Vp. As vDS is further
increased, iD remains constant, and the JFET is in its current saturation region, the normal mode
of operation. (This constant current region is a characteristic feature of any transistor, FET or
BJT.) The channel shape remains unchanged, with a small region of touch near the drain, and
further increases in vDS occurs across this small region.
Figure: n-channel JFET structure for showing non-parallel depletion
regions.
FETS are high input impedance devices, and so (due to the reverse bias pn junctions).

34. Lecture 7:
The MOSFET
MOSFET’s operate the same as JFET’s but have a gate terminal that is electrically isolated from
the conductive channel.
The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET
in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main
semiconductor n-channel or p-channel by a very thin layer of insulating material usually silicon
dioxide, commonly known as glass.
This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor. The
isolation of the controlling Gate makes the input resistance of the MOSFETextremely high way
up in the Mega-ohms ( MΩ ) region thereby making it almost infinite.
As the Gate terminal is electrically isolated from the main current carrying channel between the
drain and source, “NO current flows into the gate” and just like the JFET, the MOSFET also acts
like a voltage controlled resistor where the current flowing through the main channel between the
Drain and Source is proportional to the input voltage. Also like the JFET, the MOSFETs very
high input resistance can easily accumulate large amounts of static charge resulting in
the MOSFET becoming easily damaged unless carefully handled or protected.
Like the previous JFET tutorial, MOSFETs are three terminal devices with
a Gate, Drainand Source and both P-channel (PMOS) and N-channel (NMOS) MOSFETs are
available. The main difference this time is that MOSFETs are available in two basic forms:

35.  Depletion Type – the transistor requires the Gate-Source voltage, ( VGS ) to switch the
device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch.
 Enhancement Type – the transistor requires a Gate-Source voltage, ( VGS ) to switch the
device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open”
switch.
The symbols and basic construction for both configurations of MOSFETs are shown below.
The four MOSFET symbols above show an additional terminal called the Substrate and is not
normally used as either an input or an output connection but instead it is used for grounding the
substrate. It connects to the main semiconductive channel through a diode junction to the body or
metal tab of the MOSFET.

36. Basic MOSFET Structure and Symbol
The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction
FET. Both the Depletion and Enhancement type MOSFETs use an electrical field produced by a
gate voltage to alter the flow of charge carriers, electrons for n-channel or holes for P-channel,
through the semiconductive drain-source channel. The gate electrode is placed on top of a very
thin insulating layer and there are a pair of small n-type regions just under the drain and source
electrodes.
We saw in the previous tutorial, that the gate of a junction field effect transistor, JFET must be
biased in such a way as to reverse-bias the pn-junction. With a insulated gate MOSFET device
no such limitations apply so it is possible to bias the gate of a MOSFET in either polarity,
positive (+ve) or negative (-ve).
This makes the MOSFET device especially valuable as electronic switches or to make logic
gates because with no bias they are normally non-conducting and this high gate input resistance
means that very little or no control current is needed as MOSFETs are voltage controlled
devices. Both the p-channel and the n-channel MOSFETs are available in two basic forms,
the Enhancement type and the Depletion type.
Depletion-mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement mode types is
normally switched “ON” (conducting) without the application of a gate bias voltage. That is the
channel conducts when VGS = 0 making it a “normally-closed” device. The circuit symbol shown
above for a depletion MOS transistor uses a solid channel line to signify a normally closed
conductive channel.

37. For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will deplete
(hence its name) the conductive channel of its free electrons switching the transistor “OFF”.
Likewise for a p-channel depletion MOS transistor a positive gate-source voltage, +VGS will
deplete the channel of its free holes turning it “OFF”.
In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and
more current. While a -VGS means less electrons and less current. The opposite is also true for
the p-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed”
switch.
Depletion-mode N-Channel MOSFET and circuit Symbols
The depletion-mode MOSFET is constructed in a similar way to their JFET transistor
counterparts were the drain-source channel is inherently conductive with the electrons and holes
already present within the n-type or p-type channel. This doping of the channel produces a
conducting path of low resistance between the Drain and Source with zero Gate bias.

38. Enhancement-mode MOSFET
The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the
depletion-mode type. Here the conducting channel is lightly doped or even undoped making it
non-conductive. This results in the device being normally “OFF” (non-conducting) when the
gate bias voltage, VGS is equal to zero. The circuit symbol shown above for an enhancement
MOS transistor uses a broken channel line to signify a normally open non-conducting channel.
For the n-channel enhancement MOS transistor a drain current will only flow when a gate
voltage ( VGS ) is applied to the gate terminal greater than the threshold voltage ( VTH ) level in
which conductance takes place making it a transconductance device.
The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons
towards the oxide layer around the gate thereby increasing or enhancing (hence its name) the
thickness of the channel allowing more current to flow. This is why this kind of transistor is
called an enhancement mode device as the application of a gate voltage enhances the channel.
Increasing this positive gate voltage will cause the channel resistance to decrease further causing
an increase in the drain current, ID through the channel. In other words, for an n-channel
enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGSturns the
transistor “OFF”. Thus the enhancement-mode MOSFET is equivalent to a “normally-open”
switch.
The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device is
“OFF” and the channel is open. The application of a negative (-ve) gate voltage to the p-type
eMOSFET enhances the channels conductivity turning it “ON”. Then for an p-channel
enhancement mode MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the transistor
“ON”.

39. Enhancement-mode N-Channel MOSFET and Circuit Symbols
Enhancement-mode MOSFETs make excellent electronics switches due to their low “ON”
resistance and extremely high “OFF” resistance as well as their infinitely high input resistance
due to their isolated gate. Enhancement-mode MOSFETs are used in integrated circuits to
produce CMOS type Logic Gates and power switching circuits in the form of as PMOS (P-
channel) and NMOS (N-channel) gates. CMOS actually stands for Complementary
MOS meaning that the logic device has both PMOS and NMOS within its design.
Lecture 8:
A thyristor is a four layer solid-state semiconductor device with P and N type material.
Whenever a gate receives a triggering current then it starts’ conducting until the voltage across
the thyistor device is under forward bias. So it acts as a bistable switch under this condition. To
control the large amount of current of the two leads we have to design a three lead thyristor by
combining the small amount of current to that current. This process is known as control lead. If

40. the potential difference between the two leads is under breakdown voltage, then a two lead
thyristor is used to switch on the device.
Thyristor Circuit Symbol
Thyistor circuit symbol is as given below. It has three terminals Anode, cathode and gate.
There are three states in a thyristor
 Reverse blocking mode– In this mode of operation, the diode will block the voltage which is
applied.
 Forward blocking mode– In this mode, the voltage applied in a direction makes a diode to
conduct. But conduction will not happen here because the thyristor has not triggered.
 Forward conducting mode– The thyristor has triggered and current will flow through the
device until the forward current reaches below the threshold value which is known as
“Holding current”.
Thyristor Layer Diagram
Thyristor consists of three p-n junctions namely J1, J2, and J3.If the anode is at a positive
potential with respect to the cathode and the gate terminal is not triggered with any voltage then
J1 and J3 will be under forward bias condition. While J2 junction will be under reverse bias
condition. So J2 junction will be in the off state (no conduction will take place). If the increase in
voltage across anode and cathode beyond the VBO(Breakdown voltage) then avalanche
breakdown occurs for J2 and then thyristor will be in ON state (starts conducting).
f a VG (Positive potential) is applied to the gate terminal, then a breakdown occurs at the junction
J2 which will be of low value VAK. The thyristor can switch to ON state, by selecting a proper
value VG. Under avalanche breakdown condition, the thyristor will conduct continuously without
taking consideration of gate voltage, until and unless,
 The potential VAK is removed or
 Holding current is greater than the current flowing through the device
Here VG– Voltage pulse which is the output voltage of the UJT relaxation oscillator.
Thyristor switching circuits
 DC Thyristor Circuit
 AC Thyristor circuit

41. DC Thyristor Circuit
When connected to the DC supply, to control the larger DC loads and current we use thyristor.
The main advantage of thyristor in a DC circuit as a switch gives a high gain in current. A small
gate current can control large amounts of anode current, so the thyristor is known as a current
operated device.
Thyristor switching circuits
 DC Thyristor Circuit
 AC Thyristor circuit
DC Thyristor Circuit
When connected to the DC supply, to control the larger DC loads and current we use thyristor.
The main advantage of thyristor in a DC circuit as a switch gives a high gain in current. A small
gate current can control large amounts of anode current, so the thyristor is known as a current
operated device.
Thyristor switching circuits
 DC Thyristor Circuit
 AC Thyristor circuit
DC Thyristor Circuit
When connected to the DC supply, to control the larger DC loads and current we use thyristor.
The main advantage of thyristor in a DC circuit as a switch gives a high gain in current. A small
gate current can control large amounts of anode current, so the thyristor is known as a current
operated device.

42. AC Thyristor Circuit
When connected to the AC supply, thyristor acts differently because it is not same as DC
connected circuit. During one half of a cycle, thyristor used as an AC circuit causing it to turn off
automatically due to its reverse biased condition.
Types of Thyristors
Based on turn on and turn off capabilities the thyristors are classified into the following types:
 Silicon controlled thyristor or SCRs
 Gate turn off thyristors or GTOs
 Emitter turn off thyristors or ETOs
 Reverse conducting thyristors or RCTs
 Bidirectional Triode Thyristors or TRIACs
 MOS turn off thyristors or MTOs
 Bidirectional phase controlled thyristors or BCTs
 Fast switching thyristors or SCRs
 Light activated silicon controlled rectifiers or LASCRs
 FET controlled thyristors or FET-CTHs
 Integrated gate commutated Thyristors or IGCTs
SCR:In many ways the Silicon Controlled Rectifier, SCR or just Thyristor as it is more
commonly known, is similar in construction to the transistor.

43. It is a multi-layer semiconductor device, hence the “silicon” part of its name. It requires a gate
signal to turn it “ON”, the “controlled” part of the name and once “ON” it behaves like a
rectifying diode, the “rectifier” part of the name. In fact the circuit symbol for
the thyristor suggests that this device acts like a controlled rectifying diode.
However, unlike the junction diode which is a two layer ( P-N ) semiconductor device, or the
commonly used bipolar transistor which is a three layer ( P-N-P, or N-P-N ) switching device,
the Thyristor is a four layer ( P-N-P-N ) semiconductor device that contains three PN junctions
in series, and is represented by the symbol as shown.
Like the diode, the Thyristor is a unidirectional device, that is it will only conduct current in one
direction only, but unlike a diode, the thyristor can be made to operate as either an open-circuit
switch or as a rectifying diode depending upon how the thyristors gate is triggered. In other
words, thyristors can operate only in the switching mode and cannot be used for amplification.
The silicon controlled rectifier SCR, is one of several power semiconductor devices along with
Triacs (Triode AC’s), Diacs (Diode AC’s) and UJT’s (Unijunction Transistor) that are all
capable of acting like very fast solid state AC switches for controlling large AC voltages and
currents. So for the Electronics student this makes these very handy solid state devices for
controlling AC motors, lamps and for phase control.
The operating voltage-current I-V characteristics curves for the operation of a Silicon
Controlled Rectifier are given as:

44. Thyristor I-V Characteristics Curves
Lecture 9:
Operational Amplifier Basics
Operational Amplifiers, or Op-amps as they are more commonly called, are one of the basic
building blocks of Analogue Electronic Circuits

45. Operational amplifiers are linear devices that have all the properties required for nearly ideal DC
amplification and are therefore used extensively in signal conditioning, filtering or to perform
mathematical operations such as add, subtract, integration and differentiation.
An Operational Amplifier, or op-amp for short, is fundamentally a voltage amplifying device
designed to be used with external feedback components such as resistors and capacitors between
its output and input terminals. These feedback components determine the resulting function or
“operation” of the amplifier and by virtue of the different feedback configurations whether
resistive, capacitive or both, the amplifier can perform a variety of different operations, giving
rise to its name of “Operational Amplifier”.
An Operational Amplifier is basically a three-terminal device which consists of two high
impedance inputs. One of the inputs is called the Inverting Input, marked with a negative or
“minus” sign, ( – ). The other input is called the Non-inverting Input, marked with a positive or
“plus” sign ( + ).
A third terminal represents the operational amplifiers output port which can both sink and source
either a voltage or a current. In a linear operational amplifier, the output signal is the
amplification factor, known as the amplifiers gain ( A ) multiplied by the value of the input
signal and depending on the nature of these input and output signals, there can be four different
classifications of operational amplifier gain.
 Voltage – Voltage “in” and Voltage “out”
 Current – Current “in” and Current “out”
 Transconductance – Voltage “in” and Current “out”
 Transresistance – Current “in” and Voltage “out”
Equivalent Circuit of an Ideal Operational Amplifier

46. Op-amp Parameter and Idealised Characteristic
 Open Loop Gain, (Avo)
o Infinite – The main function of an operational amplifier is to amplify the input
signal and the more open loop gain it has the better. Open-loop gain is the gain of the
op-amp without positive or negative feedback and for such an amplifier the gain will
be infinite but typical real values range from about 20,000 to 200,000.
 Input impedance, (ZIN)
o Infinite – Input impedance is the ratio of input voltage to input current and is
assumed to be infinite to prevent any current flowing from the source supply into the
amplifiers input circuitry ( IIN = 0 ). Real op-amps have input leakage currents from
a few pico-amps to a few milli-amps.
 Output impedance, (ZOUT)
o Zero – The output impedance of the ideal operational amplifier is assumed to be
zero acting as a perfect internal voltage source with no internal resistance so that it
can supply as much current as necessary to the load. This internal resistance is
effectively in series with the load thereby reducing the output voltage available to
the load. Real op-amps have output impedances in the 100-20kΩ range.
 Bandwidth, (BW)
o Infinite – An ideal operational amplifier has an infinite frequency response and can
amplify any frequency signal from DC to the highest AC frequencies so it is
therefore assumed to have an infinite bandwidth. With real op-amps, the bandwidth
is limited by the Gain-Bandwidth product (GB), which is equal to the frequency
where the amplifiers gain becomes unity.
 Offset Voltage, (VIO)

47. o Zero – The amplifiers output will be zero when the voltage difference between the
inverting and the non-inverting inputs is zero, the same or when both inputs are
grounded. Real op-amps have some amount of output offset voltage.
From these “idealized” characteristics above, we can see that the input resistance is infinite,
so no current flows into either input terminal (the “current rule”) and that the differential
input offset voltage is zero (the “voltage rule”). It is important to remember these two properties
as they will help us understand the workings of the Operational Amplifier with regards to the
analysis and design of op-amp circuits.
However, real Operational Amplifiers such as the commonly available uA741, for example do
not have infinite gain or bandwidth but have a typical “Open Loop Gain” which is defined as the
amplifiers output amplification without any external feedback signals connected to it and for a
typical operational amplifier is about 100dB at DC (zero Hz). This output gain decreases linearly
with frequency down to “Unity Gain” or 1, at about 1MHz and this is shown in the following
open loop gain response curve.
An “ideal” or perfect operational amplifier is a device with certain special characteristics such
as infinite open-loop gain AO, infinite input resistance RIN, zero output resistance ROUT, infinite
bandwidth 0 to ∞ and zero offset (the output is exactly zero when the input is zero).
There are a very large number of operational amplifier IC’s available to suit every possible
application from standard bipolar, precision, high-speed, low-noise, high-voltage, etc, in either
standard configuration or with internal Junction FET transistors.
Operational amplifiers are available in IC packages of either single, dual or quad op-amps within
one single device. The most commonly available and used of all operational amplifiers in basic
electronic kits and projects is the industry standard μA-741.

48. Lecture 10:
Stages in OPAMP:
An equivalent circuit of an operational amplifier that models some resistive non-ideal
parameters.

49. Ideal op-amps
An equivalent circuit of an operational amplifier that models some resistive non-ideal
parameters.
An ideal op-amp is usually considered to have the following characteristics:
 Infinite open-loop gain G = vout / vin
 Infinite input impedance Rin, and so zero input current
 Zero input offset voltage
 Infinite output voltage range
 Infinite bandwidth with zero phase shift and infinite slew rate
 Zero output impedance Rout
 Zero noise
 Infinite common-mode rejection ratio (CMRR)
 Infinite power supply rejection ratio.
Lecture 11:
Applications of OP-AMP:
Inverting Amplifier:

50. The circuit shown above is an inverting amplifier with the Non inverting input connected to the
ground. Two resistors R1 and R2 are connected in the circuit in such a fashion that R1 feeds the
input signal while R2 returns the output to the Inverting input. Here when the input signal is
positive the output will be negative and vice versa. The voltage change at the output relative to
the input depends on the ratio of the resistors R1 and R2. R1 is selected as 1K and R2 as 10K. If
the input receives 1 volt, then there will be 1 mA current through R1 and the output will have to
become – 10 volts in order to supply 1 mA current through R2 and to maintain zero voltage at
the Inverting input.
Therefore the voltage gain is R2/R1. That is 10K/1K = 10
Non-inverting Amplifier:
The circuit shown above is a Non inverting amplifier. Here the Non inverting input receives the
signal while the Inverting input is connected between R2 and R1. When the input signal moves
either positive or negative, the output will be in phase and keeps the voltage at the inverting input
same as that of Non inverting input. The voltage gain in this case will be always higher than 1
so (1+R2/R1).
Summing Amplifier
The term summing amplifier is also named as adder, which is used to add two signal voltages.
The circuit of the voltage adder is so simple to construct and it enables to add many signals
together. These kind of amplifiers is used in a wide range of electronic circuits. For instance, on
a precise amplifier you have to add a small voltage to terminate the offset error of the operational
amplifier. An audio mixer is another example to add the waveforms together from various

51. channels before sending the mixed signal to a recorder. You can add or change the i/p or the gain
without messing up with the i/ps of the gain. Just recollect that the circuit of the inverting
summing amplifier changes the input signals.
Summing Amplifier Circuit
The summing amplifier circuit is shown below. In the circuit below Va, Vb and Vc are input
signals. These input signals are given to the inverting terminal of the operational amplifier
using input resistors like Ra, Rb and Rc. In the above manner, the number of input signals can be
given to the inverting i/p. Here, Rf is feedback resistor and RL is the load resistor. Noninverting
terminal of the operational amplifier is given to the ground terminal using Rm resistor. By
applying KCL at node V2 we can get the following equation.
V0 = -(Va + Vb + Vc)

52. Summing Amplifier Applications
Summing amplifier is a versatile device, used to combine the signals. These amplifiers add the
signals directly or scale them to fit some prearranged combination rule.
 These amplifiers are used in an audio mixer to add different signals with equal gains
 There are various resistors are used at the input of the summing amplifier to give a
weighted sum. This can be used to change a binary number to a voltage in an AC (digital
to analog converter)
 This amplifier is used to apply a DC offset voltage with an AC signal voltage. This
process can be done in an LED modulation circuit to maintain the LED in its linear
operating range.
Lecture 12:
The basic operational amplifier differentiator circuit produces an output signal which is the first
derivative of the input signal.
This operational amplifier circuit performs the mathematical operation of Differentiation, that is
it “produces a voltage output which is directly proportional to the input voltage’s rate-of-change
with respect to time“. In other words the faster or larger the change to the input voltage signal,
the greater the input current, the greater will be the output voltage change in response, becoming
more of a “spike” in shape.
As with the integrator circuit, we have a resistor and capacitor forming an RC Networkacross the
operational amplifier and the reactance ( Xc ) of the capacitor plays a major role in the
performance of a Op-amp Differentiator.

53. The Integrator Amplifier
The integrator Op-amp produces an output voltage that is both proportional to the amplitude and
duration of the input signal

54. By replacing this feedback resistance with a capacitor we now have an RC Network connected
across the operational amplifiers feedback path producing another type of operational amplifier
circuit commonly called an Op-amp Integrator circuit, the Op-amp Integrator is an
operational amplifier circuit that performs the mathematical operation of Integration, that is we
can cause the output to respond to changes in the input voltage over time as the op-amp
integrator produces an output voltage which is proportional to the integral of the input voltage.
The Differential Amplifier
The differential amplifier amplifies the voltage difference present on its inverting and non-
inverting inputs

55. If all the resistors are all of the same ohmic value, that is: R1 = R2 = R3 = R4 then the circuit
will become a Unity Gain Differential Amplifier and the voltage gain of the amplifier will be
exactly one or unity. Then the output expression would simply be Vout = V2 – V1.

56. Instrumentation Amplifier
Instrumentation Amplifiers (in-amps) are very high gain differential amplifiers which have a
high input impedance and a single ended output. Instrumentation amplifiers are mainly used to
amplify very small differential signals from strain gauges, thermocouples or current sensing
devices in motor control systems.
Unlike standard operational amplifiers in which their closed-loop gain is determined by an
external resistive feedback connected between their output terminal and one input terminal,
either positive or negative, “instrumentation amplifiers” have an internal feedback resistor that is
effectively isolated from its input terminals as the input signal is applied across two differential
inputs, V1 and V2.
The instrumentation amplifier also has a very good common mode rejection ratio, CMRR (zero
output when V1 = V2) well in excess of 100dB at DC. A typical example of a three op-amp
instrumentation amplifier with a high input impedance ( Zin ) is given below:
High Input Impedance Instrumentation Amplifier
The two non-inverting amplifiers form a differential input stage acting as buffer amplifiers with a
gain of 1 + 2R2/R1 for differential input signals and unity gain for common mode input signals.
Since amplifiers A1 and A2 are closed loop negative feedback amplifiers, we can expect the
voltage at Va to be equal to the input voltage V1. Likewise, the voltage at Vb to be equal to the
value at V2.
As the op-amps take no current at their input terminals (virtual earth), the same current must
flow through the three resistor network of R2, R1 and R2 connected across the op-amp outputs.

57. This means then that the voltage on the upper end of R1 will be equal to V1and the voltage at the
lower end of R1 to be equal to V2.
This produces a voltage drop across resistor R1 which is equal to the voltage difference between
inputs V1 and V2, the differential input voltage, because the voltage at the summing junction of
each amplifier, Va and Vb is equal to the voltage applied to its positive inputs.
However, if a common-mode voltage is applied to the amplifiers inputs, the voltages on each
side of R1 will be equal, and no current will flow through this resistor. Since no current flows
through R1 (nor, therefore, through both R2 resistors, amplifiers A1 and A2will operate as unity-
gain followers (buffers). Since the input voltage at the outputs of amplifiers A1 and A2 appears
differentially across the three resistor network, the differential gain of the circuit can be varied by
just changing the value of R1.
The voltage output from the differential op-amp A3 acting as a subtractor, is simply the
difference between its two inputs ( V2 – V1 ) and which is amplified by the gain of A3which
may be one, unity, (assuming that R3 = R4). Then we have a general expression for overall
voltage gain of the instrumentation amplifier circuit as:
Instrumentation Amplifier Equation
Op-amp Comparator
The comparator is an electronic decision making circuit that makes use of an operational
amplifiers very high gain in its open-loop state, that is, there is no feedback resistor.
The Op-amp comparator compares one analogue voltage level with another analogue voltage
level, or some preset reference voltage, VREF and produces an output signal based on this voltage

58. comparison. In other words, the op-amp voltage comparator compares the magnitudes of two
voltage inputs and determines which is the largest of the two.
Lecture 13:
REGULATED POWER SUPPLY
Regulated power supply is an electronic circuit that is designed to provide a constant dc voltage
of predetermined value across load terminals irrespective of ac mains fluctuations or load
variations.
Regulated Power Supply – Block Diagram
A regulated power supply essentially consists of an ordinary power supply and a voltage
regulating device, as illustrated in the figure. The output from an ordinary power supply is fed to
the voltage regulating device that provides the final output. The output voltage remains constant
irrespective of variations in the ac input voltage or variations in output (or load) current.
1. Load Regulation – The load regulation or load effect is the change in regulated output
voltage when the load current changes from minimum to maximum value.
Load regulation = Vno-load - Vfull-load
Vno-load refers to the Load Voltage at no load
Vfull-load refers to the Load voltage at full load.

59. From the above equation we can understand that when Vno-load occurs the load resistance is
infinite, that is, the out terminals are open circuited. Vfull-load occurs when the load resistance is
of the minimum value where voltage regulation is lost.
% Load Regulation = [(Vno-load - Vfull-load)/Vfull-load] * 100
2. Minimum Load Resistance – The load resistance at which a power supply delivers its full-
load rated current at rated voltage is referred to as minimum load resistance.
Minimum Load Resistance = Vfull-load/Ifull-load
The value of Ifull-load, full load current should never increase than that mentioned in the
datasheet of the power supply.
The Zener Diode:
A Semiconductor Diode blocks current in the reverse direction, but will suffer from premature
breakdown or damage if the reverse voltage applied across becomes too high
the Zener Diode or “Breakdown Diode”, as they are sometimes referred too, are basically the
same as the standard PN junction diode but they are specially designed to have a low and

60. specified Reverse Breakdown Voltage which takes advantage of any reverse voltage applied to
it.
The Zener diode behaves just like a normal general-purpose diode consisting of a silicon PN
junction and when biased in the forward direction, that is Anode positive with respect to its
Cathode, it behaves just like a normal signal diode passing the rated current.
However, unlike a conventional diode that blocks any flow of current through itself when reverse
biased, that is the Cathode becomes more positive than the Anode, as soon as the reverse voltage
reaches a pre-determined value, the zener diode begins to conduct in the reverse direction.
This is because when the reverse voltage applied across the zener diode exceeds the rated voltage
of the device a process called Avalanche Breakdown occurs in the semiconductor depletion layer
and a current starts to flow through the diode to limit this increase in voltage.
The current now flowing through the zener diode increases dramatically to the maximum circuit
value (which is usually limited by a series resistor) and once achieved, this reverse saturation
current remains fairly constant over a wide range of reverse voltages. The voltage point at which
the voltage across the zener diode becomes stable is called the “zener voltage”, ( Vz ) and for
zener diodes this voltage can range from less than one volt to a few hundred volts.
The point at which the zener voltage triggers the current to flow through the diode can be very
accurately controlled (to less than 1% tolerance) in the doping stage of the diodes semiconductor
construction giving the diode a specific zener breakdown voltage, ( Vz ) for example, 4.3V or
7.5V. This zener breakdown voltage on the I-V curve is almost a vertical straight line.

61. Lecture 14:
A voltage regulator is designed to automatically ‘regulate’ voltage level. It basically steps down
the input voltage to the desired level and keeps that in that same level during the supply. This
makes sure that even when a load is applied the voltage doesn’t drop.
Thus, a voltage regulator is used for two reasons:-
1. To regulate or vary the output voltage of the circuit.
2. To keep the output voltage constant at the desired value in-spite of variations in the supply
voltage or in the load current.
Zener Controlled Transistor Voltage Regulator
A zener controlled voltage regulator is used when the efficiency of a regulated power supply
becomes very low due to high current. There are two kinds of zener controlled transistor voltage
regulators.

62. Zener Controlled Transistor Series Voltage Regulator
Such a circuit is also named an emitter follower voltage regulator. It is called so because the
transistor used is connected in an emitter follower configuration. The circuit consists of an N-P-
N transistor and a zener diode. As shown in the figure below, the collector and emitter terminals
of the transistor are in series with the load. Thus this regulator has the name series in it. The
transistor used is a series pass transistor.
The output of the rectifier that is filtered is then given to the input terminals and regulated output
voltage Vload is obtained across the load resistor Rload. The reference voltage is provided by the
zener diode and the transistor acts as a variable resistor, whose resistance varies with the
operating conditions of base current, Ibase.
The main principle behind the working of such a regulator is that a large proportion of the
change in supply or input voltage appears across the transistor and thus the utput voltage tends to
remain constant.
The output voltage can thus be written as
Vout = Vzener – Vbe
The transistor base voltage Vbase and the zener diode voltage Vzener are equal and thus the
value of Vbase remains almost constant.
Operation
When the input supply voltage Vin increases the output voltage Vload also increases. This
increase in Vload will cause a reduced voltage of the transistor base emitter voltage Vbe as the

63. zener voltage Vzener is constant. This reduction in Vbe causes a decrease in the level of
conduction which will further increase the collector-emitter resistance of the transistor and thus
causing an increase in the transistor collector-emitter voltage and all of this causes the output
voltage Vout to reduce. Thus, the output voltage remains constant. The operation is similar when
the input supply voltage decreases.
The next condition would be the effect of the output load change in regard to the output voltage.
Let us consider a case where the current is increased by the decrease in load resistance Rload.
This causes a decrease in the value of output voltage and thus causes the transistor base emitter
voltage to increase. This causes the collector emitter resistance value to decrease due to an
increase in the conduction level of the transistor. This causes the input current to increase slightly
and thus compensates for the decrease in the load resistance Rload.
The biggest advantage of this circuit is that the changes in the zener current are reduced by a
factor β and thus the zener effect is greatly reduced and a much more stabilized output is
obtained.
The output voltage of the series regulator is Vout = Vzener – Vbe. The load current Iload of the
circuit will be the maximum emitter current that the transistor can pass. For a normal transistor
like the 2N3055, the load current can go upto 15A. If the load current is zero or has no value,
then the current drawn from the supply can be written as Izener + Ic(min). Such an emitter
follower voltage regulator is more efficient than a normal zener regulator. A normal zener
regulator that has only a resistor and a zener diode has to supply the base current of the
transistor.
Limitations
The limitations listed below has proved the use of this series voltage regulator only suitable for
low output voltages.
1. With the increase in room temperature, the values of Vbe and Vzener tend to decrease. Thus the
output voltage cannot be maintained a constant. This will further increase the transistor base
emitter voltage and thus the load.
2. There is no option to change the output voltage in the circuit.
3. Due to the small amplification process provided by only one transistor, the circuit cannot provide
good regulation at high currents.
4. When compared to other regulators, this regulator has poor regulation and ripple suppression
with respect to input variations.
5. The power dissipation of a pass transistor is large because it is equal to Vcc Ic and almost all
variation appears at Vce and the load current is approximately equal to collector current. Thus

64. for heavy load currents pass transistor has to dissipate a lot of power and, therefore, becoming
hot.
Zener Controlled Transistor Shunt Voltage Regulator
The image below shows the circuit diagram of a shunt voltage regulator. The circuit consists of
an NPN transistor and a zener diode along with a series resistor Rseries that is connected in
series with the input supply. The zener diode is connected across the base and the collector of the
transistor which is connected across the output.
Operation
As there is a voltage drop in the series resistance Rseries the unregulated voltage is also
decreased along with it. The amount of voltage drop depends on the current supplied t the load
Rload. The value of the voltage across the load depends on the zener diode and the transistor
base emitter voltage Vbe.
Thus, the output voltage can be written as
Vout = Vzener + Vbe = Vin – I.Rseries
The output remains nearly a constant as the values of Vzener and Vbe are nearly constant. This
condition is explained below.

65. When the supply voltage increases, the output voltage and base emitter voltage of transistor
increases and thus increases the base current Ibase and therefore causes an increase in the
collector current Icoll (Icoll = β.Ibase).
Thus, the supply voltage increases causing an increase in supply current, which inturn causes a
voltage drop i the series resistance Rseries and thereby decreasing the output voltage. This
decrease will be more than enough to compensate for the initial increase in output voltage. Thus,
the output remains nearly a constant. The working explained above happens in reverse if the
supply voltage decreases.
When the load resistance Rload decreases, the load current Iload increases due to the decrease in
currents through base and collector Ibase and Icoll. Thus, there will not be any voltage drop
across Rseries and the input current remains constant. Thus, the output voltage will remain
constant and will be the difference of the supply voltage and the voltage drop in the series
resistance. It happens in reverse if there is an increase in load resistance.
Limitations
The series resistor causes a huge amount of power loss.
1. The supply current flow will be more through the transistor than it is to be through the load.
2. The circuit may have problems regarding over voltage mishaps.
Op-amp voltage regulator
VL=VZ·(1+R2/R1)
VL voltage (which is the voltage applied to the load) is directly proportional to the Zener voltage.
As far as the Zener voltage remains stable, VL also remains stable. Additionally, the voltage
applied to the load, can be easily adjusted by adjusting R1, R2 or both of them. For continues

66. voltage adjustment, R1 and R2 should replaced by a potentiometer, having its wiper at the non-
inverting input of the op-amp, and its other leads at the ground and the VL line, respectively.
Lecture 15:
Op-ampbased Clippers
A clipper is an electronic circuit that produces an output by removing a part of the input above
or below a reference value. That means, the output of a clipper will be same as that of the input
for other than the clipped part. Due to this, the peak to peak amplitude of the output of a clipper
will be always less than that of the input.
The main advantage of clippers is that they eliminate the unwanted noise present in the
amplitude of an ac signal.
Clippers can be classified into the following two types based on the clipping portion of the
input.
 Positive Clipper
 Negative Clipper
These are discussed in detail as given below −
Positive Clipper
A positive clipper is a clipper that clips only the positive portion(s) of the input signal.
The circuit diagramof positive clipper is shown in the following figure −

67. In the circuit shown above, a sinusoidal voltage signal VtVt is applied to the non-inverting
terminal of the op-amp. The value of the reference voltage VrefVrefcan be chosen by varying
the resistor R2R2.
The operation of the circuit shown above is explained below −
 If the value of the input voltage ViVi is less than the value of the reference
voltage VrefVref, then the diode D1 conducts. Then, the circuit given above behaves as
a voltage follower. Therefore, the output voltage V0V0 of the above circuit will be
same as that of the input voltage ViVi, for ViVi < VrefVref.
 If the value of the input voltage ViVi is greater than the value of reference
voltage VrefVref, then the diode D1 will be off. Now, the op-amp operates in an open
loop since the feedback path was open. Therefore, the output voltage V0V0 of the above
circuit will be equal to the value of the reference voltage VrefVref, for ViVi > VrefVref.
The input wave form and the corresponding output wave form of a positive clipper for a
positive reference voltage VrefVref, are shown in the following figure −

68. Negative Clipper
A negative clipper is a clipper that clips only the negative portion(s) of the input signal. You
can obtain the circuit of the negative clipper just by reversing the diode and taking the reverse
polarity of the reference voltage, in the circuit that you have seen for a positive clipper.
The circuit diagram of a negative clipper is shown in the following figure −

69. In the above circuit, a sinusoidal voltage signal ViVi is applied to the non-inverting terminal of
the op-amp. The value of the reference voltage Vref
can be chosen by varying the resistor R2R2.
The operation of a negative clipper circuit is explained below −
If the value of the input voltage VtVt is greater than the value of reference voltage VrefVref,
then the diode D1 conducts. Then, the above circuit behaves as a voltage follower. Therefore,
the output voltage V0V0 of the above circuit will be same as that of the input
voltage ViVi for ViVi> VrefVref.
If the value of the input voltage ViVi is less than the value of reference voltage , then the diode
D1 will be off. Now, the op-amp operates in an open loop since the feedback path is open.
Therefore, the output voltage V0V0 of the above circuit will be equal to the value of reference
voltage ,VrefVref for ViVi < VrefVref.
The input wave form and the corresponding output wave form of a negative clipper, for a
negative reference voltage VrefVref, are shown in the following figure −

70. Op-ampbased Clampers
A clamper is an electronic circuit that produces an output, which is similar to the input but with
a shift in the DC level. In other words, the output of a clamper is an exact replica of the input.
Hence, the peak to peak amplitude of the output of a clamper will be always equal to that of the
input.
Clampers are used to introduce or restore the DC level of input signal at the output. There
are two types of op-amp based clampers based on the DC shift of the input.
 Positive Clamper
 Negative Clamper
This section discusses about these two types of clampers in detail.

71. Positive Clamper
A positive clamper is a clamper circuit that produces an output in such a way that the input
signal gets shifted vertically by a positive DC value.
The circuit diagram of a positive clamper is shown in the following figure −
In the above circuit, a sinusoidal voltage signal, ViVi is applied to the inverting terminal of op-
amp through a network that consists of a capacitor C1C1 and a resistor R1R1. That means, AC
voltage signal is applied to the inverting terminal of the op-amp.
The DC reference voltage VrefVref is applied to the non-inverting terminal of the op-amp. The
value of reference voltage VrefVref can be chosen by varying the resistor R2R2. In this case,
we will get a reference voltage VrefVref of a positive value.
The above circuit produces an output, which is the combination (resultant sum) of the
sinusoidal voltage signal ViVi and the reference voltage VrefVref. That means, the clamper
circuit produces an output in such a way that the sinusoidal voltage signal ViVi gets shifted
vertically upwards by the value of reference voltage VrefVref.
The input wave form and the corresponding output wave form of positive clamper are shown in
above figure −

72. From the figure above, you can observe that the positive clamper shifts the applied input
waveform vertically upward at the output. The amount of shift will depend on the value of the
DC reference voltage.
Negative Clamper
A negative clamper is a clamper circuit that produces an output in such a way that the input
signal gets shifted vertically by a negative DC value.
The circuit diagram of negative clamper is shown in the following figure −

73. In the above circuit, a sinusoidal voltage signal ViVi is applied to the inverting terminal of the
op-amp through a network that consists of a capacitor C1 and resistor R1R1. That means, AC
voltage signal is applied to the inverting terminal of the op-amp.
The DC reference voltage VrefVref is applied to the non-inverting terminal of the op-amp.The
value of reference voltage VrefVref can be chosen by varying the resistor R2R2. In this case,we
will get reference voltage VrefVref of a negative value.
The above circuit produces an output, which is the combination (resultant sum) of sinusoidal
voltage signal ViVi and reference voltage VrefVref. That means, the clamper circuit produces
an output in such a way that the sinusoidal voltage signal ViVi gets shifted vertically
downwards by the value of reference voltage VrefVref.
The input wave form and the corresponding output wave form of a negative clamper are shown
in the following figure −

74. We can observe from the output that the negative clamper shifts the applied input
waveform vertically downward at the output. The amount of shifting will depend on the value
of DC reference voltage.
Filters are electronic circuits that allow certain frequency components and / or reject some
other. You might have come across filters in network theory tutorial. They are passive and are
the electric circuits or networks that consist of passive elements like resistor, capacitor, and (or)
an inductor.

75. This chapter discusses about active filters in detail.
Types ofActive Filters
Active filters are the electronic circuits, which consist of active element like op-amp(s) along
with passive elements like resistor(s) and capacitor(s).
Active filters are mainly classified into the following four types based on the band of
frequencies that they are allowing and / or rejecting −
 Active Low Pass Filter
 Active High Pass Filter
 Active Band Pass Filter
 Active Band Stop Filter
Active Low Pass Filter
If an active filter allows (passes) only low frequency components and rejects (blocks) all other
high frequency components, then it is called as an active low pass filter.
The circuit diagram of an active low pass filter is shown in the following figure −

76. We know that the electric network, which is connected to the non-inverting terminal of an op-
amp is a passive low pass filter. So, the input of a non-inverting terminal of an opamp is the
output of a passive low pass filter.
Observe that the above circuit resembles a non-inverting amplifier. It is having the output of a
passive low pass filter as an input to the non-inverting terminal of op-amp. Hence, it produces
an output, which is (1+RfR1)(1+RfR1) times the input present at the non-inverting terminal.
We can choose the values of RfRf and R1R1 suitably in order to obtain the desired gain at the
output. Suppose, if we consider the resistance values of RfRf and R1R1 as zero ohms and
infinity ohms, then the above circuit will produce a unity gain low pass filter output.
Active High Pass Filter
If an active filter allows (passes) only high frequency components and rejects (blocks) all other
low frequency components, then it is called an active high pass filter.
The circuit diagram of an active high pass filter is shown in the following figure −
We know that the electric network, which is connected to the non-inverting terminal of an op-
amp is a passive high pass filter. So, the input of a non-inverting terminal of opamp is the
output of passive high pass filter.

77. Now, the above circuit resembles a non-inverting amplifier. It is having the output of a passive
high pass filter as an input to non-inverting terminal of op-amp. Hence, it produces an output,
which is (1+RfR1)(1+RfR1) times the input present at its non-inverting terminal.
We can choose the values of RfRf and R1R1 suitably in order to obtain the desired gain at the
output. Suppose, if we consider the resistance values of RfRf and R1R1 as zero ohms and
infinity ohms, then the above circuit will produce a unity gain high pass filter output.
Active Band Pass Filter
If an active filter allows (passes) only one band of frequencies, then it is called as an active
band pass filter. In general, this frequency band lies between low frequency range and high
frequency range. So, active band pass filter rejects (blocks) both low and high frequency
components.
The circuit diagram of an active band pass filter is shown in the following figure
Observe that there are two parts in the circuit diagram of active band pass filter: The first part
is an active high pass filter, while the second part is an active low pass filter.
The output of the active high pass filter is applied as an input of the active low pass filter.That
means, both active high pass filter and active low pass filter are cascaded in order to obtain the
output in such a way that it contains only a particular band of frequencies.
The active high pass filter, which is present at the first stage allows the frequencies that are
greater than the lower cut-off frequency of the active band pass filter. So, we have to choose
the values of RBRB and CBCB suitably, to obtain the desired lower cut-off frequency of the
active band pass filter.

78. Similarly, the active low pass filter, which is present at the second stage allows the frequencies
that are smaller than the higher cut-off frequency of the active band pass filter. So, we have to
choose the values of RARA and CACA suitably in order to obtain the desired higher cut-off
frequency of the active band pass filter.
Hence, the circuit in the diagram discussed above will produce an active band pass filter output.
Active Band Stop Filter
If an active filter rejects (blocks) a particular band of frequencies, then it is called as an active
band stop filter. In general, this frequency band lies between low frequency range and high
frequency range. So, active band stop filter allows (passes) both low and high frequency
components.
The block diagram of an active band stop filter is shown in the following figure −
Observe that the block diagram of an active band stop filter consists of two blocks in its first
stage: an active low pass filter and an active high pass filter. The outputs of these two blocks are
applied as inputs to the block that is present in the second stage. So, the summing
amplifier produces an output, which is the amplified version of sum of the outputs of the active
low pass filter and the active high pass filter.
Therefore, the output of the above block diagram will be the output of an active band stop ,
when we choose the cut-off frequency of low pass filter to be smaller than cut-off frequency of
a high pass filter.
The circuit diagram of an active band stop filter is shown in the following figure −

79. Observe that we got the above circuit diagram of active band stop filter by replacing the blocks
with the respective circuit diagrams in the block diagram of an active band stop filter.
Lecture 16:
In oscillator is an electronic circuit that produces a periodic signal. If the oscillator produces
sinusoidal oscillations, it is called as a sinusoidal oscillator. It converts the input energy from a
DC source into an AC output energy of a periodic signal. This periodic signal will be having a
specific frequency and amplitude.
The block diagram of a sinusoidal oscillator is shown in the following figure −

80. The above figure mainly consists of two blocks: an amplifier and a feedback network.The
feedback network takes a part of the output of amplifier as an input to it and produces a voltage
signal. This voltage signal is applied as an input to the amplifier.
The block diagram of a sinusoidal oscillator shown above produces sinusoidal oscillations,
when the following two conditions are satisfied −
 The loop gain AvβAvβ of the above block diagram of sinusoidal oscillator must be
greater than or equal to unity. Here, AvAv and ββ are the gain of amplifier and gain of
the feedback network, respectively.
 The total phase shift around the loop of the above block diagram of a sinusoidal
oscillator must be either 00 or 3600.
LC Oscillator Basics

81. Oscillators are electronic circuits that generate a continuous periodic waveform at a precise
frequency
An Oscillator is basically an Amplifier with “Positive Feedback”, or regenerative feedback (in-
phase) and one of the many problems in electronic circuit design is stopping amplifiers from
oscillating while trying to get oscillators to oscillate.
Oscillators work because they overcome the losses of their feedback resonator circuit either in
the form of a capacitor, inductor or both in the same circuit by applying DC energy at the
required frequency into this resonator circuit. In other words, an oscillator is a an amplifier
which uses positive feedback that generates an output frequency without the use of an input
signal.
Oscillator Gain Without Feedback
Oscillator Gain With Feedback
Lecture 16:

82. Op-amp Multivibrator
The Op-amp Multivibrator is a non-inverting op-amp circuit that produces its own input signal
with the aid of an RC feedback network
The Op-amp Multivibrator is an astable oscillator circuit that generates a rectangular output
waveform using an RC timing network connected to the inverting input of the operational
amplifier and a voltage divider network connected to the other non-inverting input.
Op amp bistable Multivibrator:
This is easy to use an operational amplifier as a bistable multivibrator. An incoming waveform is
converted into short pulses and these are used to trigger the operational amplifier to change
between its two saturation states. To prevent small levels of noise triggering the circuit,
hysteresis is introduced into the circuit, the level being dependent upon the application required.
The operational amplifier bistable multivibrator uses just five components, the operational
amplifier, a capacitor and three resistors.

83. The bistable circuit has two stable states. These are the positive and negative saturation voltages
of the operational amplifier operating with the given supply voltages. The circuit can then be
switched between them by applying pulses. A negative going pulse will switch the circuit into
the positive saturation voltage, and a positive going pulse will switch it into the negative state.
Waveforms for the bistable multivibrator circuit
It is very easy to calculate the points at which the circuit will trigger. The positive going pulses
need to be greater than Vo-Sat through the potential divider, i.e. -Vsat x R3 / (R2 + R3), and
similarly the negative going pulses will need to be greater than +Vsat through the potential
divider, i.e. +Vsat x R3 / (R2 + R3). If they are not sufficiently large then the bistable will not
change state.
Op-amp Monostable
Op-amp Monostable Multivibrators are electronic circuits which produces a single timed
rectangular output pulse when externally triggered.

84. Op-amp Monostable Circuit
In this inverting operational amplifier configuration, some of the output signal (called the
feedback fraction) is fed back to the inverting input of the operational amplifier via the resistive
network.
In this basic inverting configuration the feedback fraction is therefore negative as it is fed back to
the inverting input. This negative feedback configuration between the output and the inverting
input terminal forces the differential input voltage towards zero.
The result of this negative feedback is that the op-amp produces an amplified output signal
which is 180o out-of-phase with the input signal. So an increase in the inverting terminal
voltage, -V fed back from the output causes a decrease in the output voltage, VOproducing a
balanced and stable amplifier operating within its linear region.
Op-amp Monostable Waveforms

85. Op-amp Monostable Timing Period
The charging recovery time is given as:
Applications of mono stable multivibrator. The monostable multivibrator is used as delay
and timing circuits. It is often used to trigger another pulse generator. It is used for regenerating
old and worn out pulses.
Applications of Astable Multivibrators. Theapplications of Astable multivibrators involve in
radio gears to transmit and receive radio signals and also in time, morse code generators and
some systems which require a square wave like analog integrated circuits and TV broadcasts.
Applications of Bistable Multivibrator. BistableMultivibrators have several applications like
frequency dividers, as a storage device in computer memories or counters but they are most
excellent used in circuits like Latches and Counter.

86. Lecture 18:
Number System and base conversions | Digital
Electronics
Digital electronics, digital technology or digital(electronic) circuits are electronics that
operate ondigital signals. In contrast, analog circuits manipulate analog signals whose
performance is more subject to manufacturing tolerance, signal attenuation and noise.
Electronic and Digital systems may use a variety of different number systems, (e.g. Decimal,
Hexadecimal, Octal, Binary).
A number N in base or radix b can be written as:
(N)b = dn-1 dn-2 — — — — d1 d0 . d-1 d-2 — — — — d-m
In the above, dn-1 to d0 is integer part, then follows a radix point, and then d-1 to d-m is fractional
part.
dn-1 = Most significant bit (MSB)
d-m = Least significant bit (LSB)
How to convert a number from one base to another?
Follow the example illustrations:
1. Decimal to Binary
(10.25)10

87. Note: Keep multiplying the fractional part with 2 until decimal part 0.00 is obtained.
(0.25)10 = (0.01)2
Answer: (10.25)10 = (1010.01)2
2. Binary to Decimal
(1010.01)2
1×23
+ 0x22
+ 1×21
+ 0x20
+ 0x2 -1
+ 1×2 -2
= 8+0+2+0+0+0.25 = 10.25
(1010.01)2 = (10.25)10
3. Decimal to Octal
(10.25)10
(10)10 = (12)8
Fractional part:
0.25 x 8 = 2.00
Note: Keep multiplying the fractional part with 8 until decimal part .00 is obtained.
(.25)10 = (.2)8
Answer: (10.25)10 = (12.2)8
4. Octal to Decimal
(12.2)8
1 x 81
+ 2 x 80
+2 x 8-1
= 8+2+0.25 = 10.25
(12.2)8 = (10.25)10

88. 5. Hexadecimal and Binary
To convert from Hexadecimal to Binary, write the 4-bit binary equivalent of hexadecimal.
(3A)16 = (00111010)2
To convert from Binary to Hexadecimal, group the bits in groups of 4 and write the hex for the
4-bit binary. Add 0's to adjust the groups.
1111011011
(001111011011 )2 = (3DB)16
Boolean Algebra:

89. Logic Gates:
Lecture 19:
Difference between combinational and sequential circuit
Prerequisite – Combinational circuits using Decoder, Introduction of Sequential Circuits
Combinational circuits are defined as the time independent circuits which do not depends upon
previous inputs to generate any output are termed as combinational circuits. Sequential
circuits are those which are dependent on clock cycles and depends on present as well as past
inputs to generate any output.
Combinational Circuit –
1. In this output depends only upon present input.
2. Speed is fast.
3. It is designed easy.
4. There is no feedback between input and output.
5. This is time independent.
6. Elementary building blocks: Logic gates
7. Used for arithmetic as well as boolean operations.
8. Combinational circuits don’t have capability to store any state.
9. As combinational circuits don’t have clock, they don’t require triggering.
10. These circuits do not have any memory element.
11. It is easy to use and handle.
Examples – Encoder, Decoder, Multiplexer, Demultiplexer

90. Block Diagram –
Sequential Circuit –
1. In this output depends upon present as well as past input.
2. Speed is slow.
3. It is designed tough as compared to combinational circuits.
4. There exists a feedback path between input and output.
5. This is time dependent.
6. Elementary building blocks: Flip-flops
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.
11. It is not easy to use and handle.
Examples – Flip-flops, Counters
Block Diagram –
Binary Adder
Binary Adders are arithmetic circuits in the form of half-adders and full-addersb used to add
together two binary digits
A Half Adder Circuit

91. A half adder is a logical circuit that performs an addition operation on two binary digits. The half
adder produces a sum and a carry value which are both binary digits.
Half Adder Truth Table with Carry-Out
From the truth table of the half adder we can see that the SUM (S) output is the result of
the Exclusive-OR gate and the Carry-out (Cout) is the result of the AND gate. Then the Boolean
expression for a half adder is as follows.
For the SUM bit:
SUM = A XOR B = A ⊕ B
For the CARRY bit:
CARRY = A AND B = A.B
One major disadvantage of the Half Adder circuit when used as a binary adder, is that there is no
provision for a “Carry-in” from the previous circuit when adding together multiple data bits.
For example, suppose we want to add together two 8-bit bytes of data, any resulting carry bit
would need to be able to “ripple” or move across the bit patterns starting from the least
significant bit (LSB). The most complicated operation the half adder can do is “1 + 1” but as the
half adder has no carry input the resultant added value would be incorrect. One simple way to
overcome this problem is to use a Full Adder type binary adder circuit.
A Full Adder Circuit

92. The main difference between the Full Adder and the previous Half Adder is that a full adder
has three inputs. The same two single bit data inputs A and B as before plus an additional Carry-
in (C-in) input to receive the carry from a previous stage as shown below.
Full Adder Block Diagram
Then the full adder is a logical circuit that performs an addition operation on three binary digits
and just like the half adder, it also generates a carry out to the next addition column. Then
a Carry-in is a possible carry from a less significant digit, while a Carry-out represents a carry to
a more significant digit.
In many ways, the full adder can be thought of as two half adders connected together, with the
first half adder passing its carry to the second half adder as shown.
Full Adder Logic Diagram
As the full adder circuit above is basically two half adders connected together, the truth table for
the full adder includes an additional column to take into account the Carry-in, CINinput as well as
the summed output, S and the Carry-out, COUT bit.

93. Full Adder Truth Table with Carry
Then the Boolean expression for a full adder is as follows.
For the SUM (S) bit:
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
For the CARRY-OUT (Cout) bit:
CARRY-OUT = A AND B OR Cin(A XOR B
Flip Flops:
Flip flops are actually an application of logic gates. With the help of Boolean logic you can
create memory with them. Flip flops can also be considered as the most basic idea of a Random
Access Memory [RAM]. When a certain input value is given to them, they will be remembered
and executed, if the logic gates are designed correctly. A higher application of flip flops is
helpful in designing better electronic circuits.
The most commonly used application of flip flops is in the implementation of a feedback circuit.
As a memory relies on the feedback concept, flip flops can be used to design it.
There are mainly four types of flip flops that are used in electronic circuits. They are
1. The basic Flip Flop or S-R Flip Flop
2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop
1. S-R Flip Flop
The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND
gates. These flip flops are also called S-R Latch.

94.  S-R Flip Flop using NOR Gate
The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are
also two outputs, Q and Q’. The diagram and truth table is shown below.
S-R Flip Flop using NOR Gate
From the diagram it is evident that the flip flop has mainly four states. They are
S=1, R=0—Q=1, Q’=0
This state is also called the SET state.
S=0, R=1—Q=0, Q’=1
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the value of S.
S=0, R=0—Q & Q’ = Remember
If both the values of S and R are switched to 0, then the circuit remembers the value of S and R
in their previous state.

95. S=1, R=1—Q=0, Q’=0 [Invalid]
This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be
compliments of each other. Normally, this state must be avoided.
 S-R Flip Flop using NAND Gate
The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.
S-R Flip Flop using NAND Gate
Like the NOR Gate S-R flip flop, this one also has four states. They are
S=1, R=0—Q=0, Q’=1
This state is also called the SET state.
S=0, R=1—Q=1, Q’=0
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the compliment value of S.

96. S=0, R=0—Q=1, & Q’ =1 [Invalid]
If both the values of S and R are switched to 0 it is an invalid state because the values of both Q
and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must
be avoided.
S=1, R=1—Q & Q’= Remember
If both the values of S and R are switched to 1, then the circuit remembers the value of S and R
in their previous state.
 Clocked S-R Flip Flop
It is also called a Gated S-R flip flop.
The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem
can be overcome by using a bistable SR flip-flop that can change outputs when certain invalid
states are met, regardless of the condition of either the Set or the Reset inputs. For this, a clocked
S-R flip flop is designed by adding two AND gates to a basic NOR Gate flip flop. The circuit
diagram and truth table is shown below.

97. Clocked S-R Flip Flop
A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is
‘0’, the outputs of both the AND Gates remain ‘0’. As soon as a pulse is given the value of CP
turns ‘1’. This makes the values at S and R to pass through the NOR Gate flip flop. But when the
values of both S and R values turn ‘1’, the HIGH value of CP causes both of them to turn to ‘0’
for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate.
Thus either of the two states may be caused, and it depends on whether the set or reset input of
the flip-flop remains a ‘1’ longer than the transition to ‘0’ at the end of the pulse. Thus the
invalid states can be eliminated.
2. D Flip Flop
The circuit diagram and truth table is given below.

98. D Flip Flop
D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From the
figure you can see that the D input is connected to the S input and the complement of the D input
is connected to the R input. The D input is passed on to the flip flop when the value of CP is ‘1’.
When CP is HIGH, the flip flop moves to the SET state. If it is ‘0’, the flip flop switches to the
CLEAR state.
To know more about the triggering of flip flop click on the link below.
TAKE A LOOK : TRIGGERING OF FLIP FLOPS
TAKE A LOOK : MASTER-SLAVE FLIP FLOP CIRCUIT
3. J-K Flip Flop
The circuit diagram and truth-table of a J-K flip flop is shown below.

99. J-K Flip Flop
A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is
that the intermediate state is more refined and precise than that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.
So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.
The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as a
feedback to the input of the AND along with other inputs like K and clock pulse [CP]. So, if
the value of CP is ‘1’, the flip flop gets a CLEAR signal and with the condition that the value of

100. Q was earlier 1. Similarly output Q’ of the flip flop is given as a feedback to the input of the
AND along with other inputs like J and clock pulse [CP]. So the output becomes SET when the
value of CP is 1 only if the value of Q’ was earlier 1.
The output may be repeated in transitions once they have been complimented for J=K=1 because
of the feedback connection in the JK flip-flop. This can be avoided by setting a time duration
lesser than the propagation delay through the flip-flop. The restriction on the pulse width can be
eliminated with a master-slave or edge-triggered construction.
Lecture 20:
Counters:
A counter is basically used to count the number of clock pulses applied to a flip-flop. It can also
be used for Frequency divider, time measurement, frequency measurement, distance
measurement and also for generating square waveforms. In this, the flip-flops are asynchronous
counters and are supplied with different clock signals, there may be a delay in producing output.
Also, a few numbers of logic gates are needed to design asynchronous counters. So they are
elementary in design and also are less expensive.
Ripple counter –
A n-bit ripple counter can count up to 2n states. It is also known as MOD n counter. It is known
as ripple counter because of the way the clock pulse ripples its way through the flip-flops. Some
of the features of ripple counter are:
1. It is an asynchronous counter.
2. Different flip-flops are used with a different clock pulse.
3. All the flip-flops are used in toggle mode.
4. Only one flip-flop is applied with an external clock pulse and another flip-flop clock is
obtained from the output of the previous flip-flop.
5. The flip-flop applied with external clock pulse act as LSB (Least Significant Bit) in the
counting sequence.
A counter may be an up counter that counts upwards or can be a down counter that counts
downwards or can do both i.e.count up as well as count downwards depending on the input
control. The sequence of counting usually gets repeated after a limit. When counting up, for n-bit
counter the count sequence goes from 000, 001, 010, … 110, 111, 000, 001, … etc. When
counting down the count sequence goes in the opposite manner: 111, 110, … 010, 001, 000, 111,
110, … etc.
A 3-bit Ripple counter using JK flip-flop –

101. In the circuit shown in above figure, Q0(LSB) will toggle for every clock pulse because JK flip-
flop works in toggle mode when both J and K are applied 1, 1 or high input. The following
counter will toggle when the previous one changes from 1 to 0
Truth Table –
The 3-bit ripple counter used in the circuit above has eight different states, each one of which
represents a count value. Similarly, a counter having n flip-flops can have a maximum of 2 to the
power n states. The number of states that a counter owns is known as its mod (modulo) number.
Hence a 3-bit counter is a mod-8 counter.
A mod-n counter may also be described as a divide-by-n counter. This is because the most
significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for
every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock
pulse). Thus, the above counter is an example of a divide-by-4 counter.
Timing diagram – Let us assume that the clock is negative edge triggered so above counter will
act as an up counter because the clock is negative edge triggered and output is taken from Q.
Counters are used very frequently to divide clock frequencies and their uses mainly involve in
digital clocks and in multiplexing. The widely known example of the counter is parallel to serial
data conversion logic.
Ring Counter:
The output of a shift register is fed back to the input. a ring counter results. The data pattern
contained within the shift register will recirculate as long as clock pulses are applied. For
example, the data pattern will repeat every four clock pulses in the figure below. However, we
must load a data pattern. All 0‘s or all 1‘s doesn’t count.

102. Decade Counter:
BCD or Decade Counter Circuit
A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And it resets for
every new clock input. As it can go through 10 unique combinations of output, it is also called as
“Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010, 1011, 1110,
1111, 0000, and 0001 and so on.

103. 4 bit binary counter will act as decade counter by skipping any six outputs out of the 16 (24)
outputs. There are some available ICs for decade counters which we can readily use in our
circuit, like 74LS90. It is an asynchronous decade counter.
The above figure shows a decade counter constructed with JK flip flop. The J output and K
outputs are connected to logic 1. The clock input of every flip flop is connected to the output of
next flip flop, except the last one.
The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to all the flip
flops. This ripple counter can count up to 16 i.e. 24.
Decade Counter Operation
When the Decade counter is at REST, the count is equal to 0000. This is first stage of the counter
cycle. When we connect a clock signal input to the counter circuit, then the circuit will count the
binary sequence. The first clock pulse can make the circuit to count up to 9 (1001). The next
clock pulse advances to count 10 (1010).
Then the ports X1 and X3 will be high. As we know that for high inputs, the NAND gate output
will be low. The NAND gate output is connected to clear input, so it resets all the flip flop stages
in decade counter. This means the pulse after count 9 will again start the count from count 0.

104. Truth Table of Decade Counter
The above table describes the counting operation of Decade counter. It represents the count of
circuit for decimal count of input pulses. The NAND gate output is zero when the count reaches
10 (1010).
The count is decoded by the inputs of NAND gate X1 and X3. After count 10, the logic gate
NAND will trigger its output from 1 to 0, and it resets all flip flops.
Applications:
 Alarm Clock, Set AC Timer, Set time in camera to take the picture, flashing light indicator in
automobiles, car parking control etc.
 Counting the time allotted for special process or event by the scheduler.
Lecture 21:
Digital logic | Encoders and Decoders
Encoder, Decoders
Binary code of N digits can be used to store 2N distinct elements of coded information. This is
what encoders and decoders are used for. Encoders convert 2N lines of input into a code of N
bits and Decoders decode the N bits into 2N lines.
1. Encoders –
An encoder is a combinational circuit that converts binary information in the form of a 2Ninput

105. lines into N output lines, which represent N bit code for the input. For simple encoders, it is
assumed that only one input line is active at a time.
As an example, let’s consider Octal to Binary encoder. As shown in the following figure, an
octal-to-binary encoder takes 8 input lines and generates 3 output lines.
Truth Table –
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0

106. D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
1 0 0 0 0 0 0 0 1 1 1
As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active; 010
when D2 is active and so on.
Implementation –
From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7.
Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5, 6 or 7.
Hence, the Boolean functions would be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as follows:
One limitation of this encoder is that only one input can be active at any given time. If more than
one inputs are active, then the output is undefined. For example, if D6 and D3 are both active,
then, our output would be 111 which is the output for D7. To overcome this, we use Priority
Encoders.
Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000 which actually
is the output for D0 active. In order to avoid this, an extra bit can be added to the output, called
the valid bit which is 0 when all inputs are 0 and 1 otherwise.
Priority Encoder –
A priority encoder is an encoder circuit in which inputs are given priorities. When more than one

107. inputs are active at the same time, the input with higher priority takes precedence and the output
corresponding to that is generated.
Let us consider the 4 to 2 priority encoder as an example.
From the truth table, we see that when all inputs are 0, our V bit or the valid bit is zero and
outputs are not used. The x’s in the table show the don’t care condition, i.e, it may either be 0 or
1. Here, D3 has highest priority, therefore, whatever be the other inputs, when D3 is high, output
has to be 11. And D0 has the lowest priority, therefore the output would be 00 only when D0 is
high and the other input lines are low. Similarly, D2 has higher priority over D1 and D0 but
lower than D3 therefore the output would be 010 only when D2 is high and D3 are low (D0 &
D1 are don’t care).
Truth Table –
D3 D2 D1 D0 X Y V
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
Implementation –
It can clearly be seen that the condition for valid bit to be 1 is that at least any one of the inputs
should be high. Hence,
V = D0 + D1 + D2 + D3
For X:

108. => X = D2 + D3
For Y:
=> Y = D1 D2’ + D3
Hence, the priority 4-to-2 encoder can be realized as follows:
2. Decoders –
A decoder does the opposite job of an encoder. It is a combinational circuit that converts n lines
of input into 2n lines of output.
Let’s take an example of 3-to-8 line decoder.
Truth Table –

109. X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’

110. D7 = X Y Z
Hence,
D to A converter:
R-2R ladder D/A converter, Resistors of only two value (R and 2R) are used. Now in bellow see
the simple ladder network.

111. In ladder circuit the output voltage is also weighted sum of the corresponding digital input. Let
take an example to understand how it works? As we can see the above network is a 4-bit ladder
network so we take an example to convert analog signal correspond of 1000digital bit.
For 1000 bit we can see only MSB got 1 and rest all bits got 0. See the bellow picture to
understand how it work if it got 1000.
Now see at node1 (N1) resistor 2R connecting in b4 parallel with resistor 2R. And those 2R
parallel 2R resistors make equivalent register of R shown in bellow diagram.

112. Now for N2 same thing happen B3 series with 2R and parallel with R + R resistors. It will also
make equivalent resistor R at N3. See the bellow diagram
Repeating the same process we got equivalent of R resistor at N4.

113. Now at N4, if we calculate the output analog equivalent voltage then we will get
VA = VR*2R/(R+R+2R)
= VR/2
Thus when bit 1000 the output is VR/2. Similarly it can be found that using above process for bit
0100 the output will be VR/4, for bit 0010 output will be VR/8 and for bit 0001 output will be
VR/16.
By using superposition theorem we can find in any n-bit ladder network the output voltage will
be
VA = VR/21 + VR/22 + VR/23 + ……. + VR/2n
Where n is the total number of bits at the input.
Now see the practical circuit arrangement of 4-bit R-2R ladder D/A converter using op amp.

114. The inverting input terminal of the op amp work as a summing amplifier for the ladder inputs. So
we can get out put voltage by bellow equation.
V0 = VR*(RF/R)[b1/21 + b2/22 + b3/23 + b4/24]
Successive Approximation ADC (Analog to Digital Converter)
Successive approximation ADC is the advanced version of Digital ramp type ADC which is
designed to reduce the conversion and to increase speed of operation. The major draw of digital
ramp ADC is the counter used to produce the digital output will be reset after every sampling
interval. The normal counter starts counting from 0 and increments by one LSB in each count,
this result in 2N clock pulses to reach its maximum value.
In successive approximation ADC the normal counter is replaced with successive approximation
register as shown in below figure.

115. Successive Approximation ADC
The successive approximation register counts by changing the bits from MSB to LSB according
to input. The detailed operation is shown below.
Operation of 3 bit Successive Approximation ADC
The output of SAR is converted to analog out by the DAC and this analog output is compared
with the input analog sampled value in the Opamp comparator. This Opamp provides an high or
low clock pulse based on the difference through the logic circuit. In very first case the 3 bit SAR
enables its MSB bit as high i.e. ‘1’ and the result will be “100”. This digita output is converted to
analog value and compared with input sampled voltage (Vin). If the deference is positive i.e. if
the sampled input is high then the SAR enables the next bit from MSB and result will be “110”.
Now if the output is negative i.e. if the input sampled voltage is less than the SAR resets the last
set bit and sets the next bit and resultant output in this case will be “101” which will definitely
approximately equal to the input analog value. The counting sequence is explained by the
following counter flow chat as shown in below.
Successive Approximation ADC Counter Flow chat

116. SAR ADC input output flow voltage graph
Conversion time of Successive Approximation ADC
By observing above 3 bit example it is illustrated for a 3 bit ADC the conversion time will be 3
clock pulses. Then;
N bit Successive Approximation ADC conversion time = 3T (T- clock pulse).
So to avoid aliasing effect the next sample of input signal should be taken after 3 clock pulses.
Important note on Successive Approximation ADC
In Counter type or digital ramp type ADC the time taken for conversion depends on the
magnitude of the input, but in SAR the conversion time is independent of the magnitude of the
input sampled value.
Advantages of Successive Approximation ADC
 Speed is high compared to counter type ADC.
 Good ratio of speed to power.
 Compact design compared to Flash Type and it is inexpensive.
Disadvantages of Successive Approximation ADC
 Cost is high because of SAR
 Complexity in design.
Applications
The SAR ADC will used widely data acquisition techniques at the sampling rates higher than
10KHz